JPH05114622A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05114622A JPH05114622A JP30405091A JP30405091A JPH05114622A JP H05114622 A JPH05114622 A JP H05114622A JP 30405091 A JP30405091 A JP 30405091A JP 30405091 A JP30405091 A JP 30405091A JP H05114622 A JPH05114622 A JP H05114622A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor device
- bus bar
- pad
- ground potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 ＬＯＣパッケージ方式を採る半導体装置にお
けるパルス性の電源ノイズを抑制し、その動作を安定化
する。
【構成】 電源電圧又は接地電位を供給するためのバン
プパッドＢＰ１及びＢＰ２等と電源バスバーＢＢＣ又は
接地バスバーＢＢＳとの間を、ＣＣＢ技術を用いてバン
プ結合し、その他のボンディングパッドＰＡＤとリード
フレームＬＦの対応するインナーリードとの間を、従来
通りボンディングワイヤＢＷを介して結合する。これに
より、電源電圧又は接地電位供給用のパッドと電源バス
バー又は接地バスバーとの結合部における寄生インダク
タンスを低減し、半導体装置におけるパルス性の電源ノ
イズを抑制することができる。
(57) [Abstract] [Purpose] To suppress pulsed power supply noise in a semiconductor device adopting the LOC package system and stabilize its operation. [Structure] Bump pads BP1 and BP2 for supplying a power supply voltage or a ground potential and a power supply bus bar BBC or a ground bus bar BBS are bump-bonded using CCB technology, and other bonding pads PAD and lead frame LF. The corresponding inner leads are connected to each other via bonding wires BW as in the conventional case. As a result, the parasitic inductance in the coupling portion between the pad for supplying the power supply voltage or the ground potential and the power supply bus bar or the ground bus bar can be reduced, and the pulsed power supply noise in the semiconductor device can be suppressed.
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置に関する
もので、例えば、ＬＯＣ（Ｌｅａｄ ＯｎＣｈｉｐ）パ
ッケージ方式を採る半導体装置に利用して特に有効な技
術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when applied to a semiconductor device adopting a LOC (Lead On Chip) package system.
【０００２】[0002]
【従来の技術】ボンディングパッドを半導体基板（チッ
プ）の中央部に直線状に配置し、これらのボンディング
パッドとリードフレームのインナーリードとのワイヤボ
ンディングを半導体基板面上で行うＬＯＣパッケージ方
式がある。2. Description of the Related Art There is a LOC package system in which bonding pads are linearly arranged in the center of a semiconductor substrate (chip) and wire bonding between these bonding pads and inner leads of a lead frame is performed on the surface of the semiconductor substrate.
【０００３】ＬＯＣパッケージ方式について、例えば、
日経マグロウヒル社発行『日経マイクロデバイス』１９
９１年２月号の第８９頁〜第９７頁に記載されている。Regarding the LOC package system, for example,
Published by Nikkei McGraw-Hill Inc. "Nikkei Microdevice" 19
It is described on pages 89 to 97 of the February 1991 issue.
【０００４】[0004]
【発明が解決しようとする課題】ＬＯＣパッケージ方式
を採る従来の半導体装置において、リードフレームＬＦ
には、図４に例示されるように、ボンディングパッド列
をはさんで、回路の電源電圧又は接地電位を伝達するた
めのいわゆる電源バスバーＢＢＣ及び接地バスバーＢＢ
Ｓが設けられる。これらのバスバー（バスバーリード）
は、ボンディングワイヤＢＷを介して、半導体基板ＳＵ
Ｂに設けられた電源電圧又は接地電位供給用の複数のボ
ンディングパッドと結合される。これにより、半導体装
置の電源電圧又は接地電位供給点が分散され、電源イン
ピーダンスが低減される。In the conventional semiconductor device adopting the LOC package system, the lead frame LF is used.
As illustrated in FIG. 4, the so-called power supply bus bar BBC and ground bus bar BB for transmitting the power supply voltage or ground potential of the circuit across the bonding pad row.
S is provided. These busbars (busbar leads)
Is the semiconductor substrate SU via the bonding wire BW.
It is coupled to a plurality of bonding pads for supplying a power supply voltage or a ground potential provided at B. As a result, the power supply voltage or the ground potential supply point of the semiconductor device is dispersed, and the power supply impedance is reduced.
【０００５】ところが、半導体装置の大規模化が進み電
源電圧又は接地電位供給点の数が増大するにしたがっ
て、上記ＬＯＣパッケージ方式には次のような問題点が
生じることが本願発明者等によって明らかとなった。す
なわち、電源電圧又は接地電位供給点は、前述のよう
に、ボンディングワイヤＢＷを介して電源バスバーＢＢ
Ｃ又は接地バスバーＢＢＳに結合され、各ボンディング
ワイヤＢＷには、わずかながらも寄生インダクタンスが
結合される。これらの寄生インダクタンスは、回路の電
源電圧又は接地電位にパルス性の電源ノイズを発生させ
る原因となり、これによって半導体装置の動作が不安定
なものとなる。However, as the size of the semiconductor device has increased and the number of power supply voltage or ground potential supply points has increased, the LOC package system has the following problems. Became. That is, the power supply voltage or ground potential supply point is connected to the power supply bus bar BB via the bonding wire BW as described above.
C or ground bus bar BBS, and a slight parasitic inductance is coupled to each bonding wire BW. These parasitic inductances cause pulsed power supply noise in the power supply voltage or ground potential of the circuit, which makes the operation of the semiconductor device unstable.
【０００６】この発明の目的は、半導体装置のパッド結
合部における寄生インダクタンスを低減することにあ
る。この発明の他の目的は、ＬＯＣパッケージ方式を採
る半導体装置の電源ノイズを抑制し、その動作を安定化
することにある。An object of the present invention is to reduce the parasitic inductance in the pad coupling portion of the semiconductor device. Another object of the present invention is to suppress power supply noise of a semiconductor device adopting the LOC package system and stabilize its operation.
【０００７】[0007]
【課題を解決するための手段】ＬＯＣパッケージ方式を
採る半導体装置において、電源電圧又は接地電位供給用
のパッドと電源バスバー又は接地バスバーとの間を、例
えばＣＣＢ（Ｃｏｎｔｒｏｌｅｄ Ｃｏｌｌａｐｓｅ
Ｂｏｎｄｉｎｇ）技術を用いてバンプ結合し、その他の
パッドと対応するインナーリードとの間を、従来通りボ
ンディングワイヤを介して結合する。In a semiconductor device adopting a LOC package system, a pad for supplying a power supply voltage or a ground potential and a power supply bus bar or a ground bus bar is, for example, CCB (Controlled Collapse).
Bonding is used to perform bump bonding, and other pads and corresponding inner leads are bonded to each other via bonding wires as is conventional.
【０００８】[0008]
【作用】上記手段によれば、電源電圧又は接地電位供給
用のパッドと電源バスバー又は接地電位バスバーとの結
合部における寄生インダクタンスを低減できるため、Ｌ
ＯＣパッケージ方式を採る半導体装置におけるパルス性
の電源ノイズを抑制し、その動作を安定化することがで
きる。According to the above means, the parasitic inductance in the coupling portion between the power supply voltage or ground potential supply pad and the power supply bus bar or the ground potential bus bar can be reduced.
It is possible to suppress pulsed power supply noise in a semiconductor device adopting the OC package system and stabilize its operation.
【０００９】[0009]
【実施例】図１には、この発明が適用された半導体装置
の第１の実施例の基板接続図が示されている。また、図
２には、図１の半導体装置の一実施例のＡ−Ｂ断面構造
図が示されている。これらの図をもとに、この実施例の
半導体装置における半導体基板及びリードフレーム間の
結合方法とその特徴について説明する。なお、以下の基
板接続図において、リードフレームＬＦは、半導体基板
の外縁周辺で切断された状態で示され、インナーリード
の部分だけが図示されている。また、以下の説明におい
て、半導体基板及びリードフレーム等の上下左右関係
は、これらの基板接続図の位置関係をもって示されてい
る。半導体装置の回路構成及び動作ならびにモールド等
を含むパッケージ構造については、この発明と直接関係
がないためにその説明を割愛する。1 is a substrate connection diagram of a first embodiment of a semiconductor device to which the present invention is applied. Further, FIG. 2 shows an AB cross-sectional structural view of one embodiment of the semiconductor device of FIG. Based on these figures, a method of coupling the semiconductor substrate and the lead frame in the semiconductor device of this embodiment and the features thereof will be described. In the following substrate connection diagram, the lead frame LF is shown in a state of being cut around the outer edge of the semiconductor substrate, and only the inner lead portion is shown. Further, in the following description, the vertical and horizontal relations of the semiconductor substrate, the lead frame and the like are shown by the positional relations of these substrate connection diagrams. The circuit configuration and operation of the semiconductor device, and the package structure including the mold and the like are not directly related to the present invention, and therefore the description thereof is omitted.
【００１０】図１において、この実施例の半導体装置
は、単結晶シリコンからなる半導体基板ＳＵＢをその基
本構成とする。この実施例において、半導体装置はＬＯ
Ｃパッケージ方式を採り、半導体基板ＳＵＢの中央部に
は、垂直方向に整列して複数のボンディングパッドＰＡ
Ｄ（第２のパッド）が配置される。また、ボンディング
パッド列の近接する外側には、図１に点線で示されるよ
うに、複数のバンプパッド（第１のパッド）ＢＰ１及び
ＢＰ２等が配置され、さらにその外側には、図示されな
い集積回路群が配置される。なお、ＢＰ１及びＢＰ２に
代表されるバンプパッドは、回路の電源電圧又は接地電
位を伝達するための電源電圧又は接地電位供給点となる
ものであり、半導体基板ＳＵＢの中央部に配置されるボ
ンディングパッドＰＡＤは、通常の入力又は出力信号を
伝達するための信号入出力点となるものである。バンプ
パッド及びボンディングパッドは、半導体基板ＳＵＢに
用意される最上層の金属配線層によって形成される。In FIG. 1, the semiconductor device of this embodiment has a semiconductor substrate SUB made of single crystal silicon as its basic structure. In this embodiment, the semiconductor device is LO
A C package method is adopted, and a plurality of bonding pads PA are vertically aligned in the central portion of the semiconductor substrate SUB.
D (second pad) is arranged. Further, a plurality of bump pads (first pads) BP1 and BP2, etc. are arranged on the outer side of the bonding pad row in the vicinity thereof, as indicated by a dotted line in FIG. 1, and further on the outer side thereof, an integrated circuit not shown is shown. A group is arranged. The bump pads typified by BP1 and BP2 are the power supply voltage or ground potential supply points for transmitting the power supply voltage or ground potential of the circuit, and are the bonding pads arranged at the center of the semiconductor substrate SUB. The PAD serves as a signal input / output point for transmitting a normal input or output signal. The bump pad and the bonding pad are formed by the uppermost metal wiring layer prepared on the semiconductor substrate SUB.
【００１１】半導体装置のパッケージ工程において、半
導体基板ＳＵＢは、所定の接着フィルムＡＦを介してリ
ードフレームＬＦと接合され、その表面上には、リード
フレームＬＦのインナーリードがボンディングパッド列
に近接する位置まで延長される。これらのインナーリー
ドの大半は、対応するボンディングパッドＰＡＤに近接
する位置で切断状態とされ、ボンディングワイヤＢＷを
介して対応するボンディングパッドＰＡＤに結合され
る。これらのボンディングパッド及びインナーリード間
の結合は、従来のワイヤボンディング法によって行われ
る。In the packaging process of the semiconductor device, the semiconductor substrate SUB is joined to the lead frame LF via a predetermined adhesive film AF, and the inner lead of the lead frame LF is located on the surface thereof in a position close to the bonding pad row. Be extended to. Most of these inner leads are cut in a position close to the corresponding bonding pad PAD, and are bonded to the corresponding bonding pad PAD via the bonding wire BW. The bonding between the bonding pad and the inner lead is performed by a conventional wire bonding method.
【００１２】一方、リードフレームＬＦの左右の最上段
及び最下段に設けられる一対のインナーリードは、それ
ぞれバンプパッドＢＰ１及びＢＰ２等を覆うべく上下に
延長され、電源バスバーＢＢＣあるいは接地バスバーＢ
ＢＳとなる。これらのバスバーは、図２に例示されるよ
うに、ＣＣＢ技術を用いて、ハンダバンプＢ１又はＢ２
等を介して対応するバンプパッドＢＰ１及びＢＰ２等に
結合される。各バスバーのバンプパッドとの結合部を除
く他の部分は、ポリ・イミド系の接着フィルムＡＦを介
して半導体基板ＳＵＢに接合される。半導体基板ＳＵＢ
の表面には、ＰＩＱすなわちポリ・イミド・イソインド
ロキナゾリンジオンからなるα線保護膜ＡＧが設けら
れ、その下層には、さらにナイトライドＳｉＮならびに
酸化シリコンＳｉＯ2 からなるパッシベーション膜ＰＧ
が設けられる。On the other hand, a pair of inner leads provided on the left and right uppermost and lowermost stages of the lead frame LF are extended vertically to cover the bump pads BP1 and BP2, respectively, and the power source bus bar BBC or the ground bus bar B is provided.
Become a BS. These busbars are solder bumps B1 or B2 using CCB technology, as illustrated in FIG.
And the like to the corresponding bump pads BP1 and BP2. The other portions of the busbars other than the bonding portions with the bump pads are bonded to the semiconductor substrate SUB via the poly-imide adhesive film AF. Semiconductor substrate SUB
An α-ray protective film AG made of PIQ, that is, poly-imide-isoindoloquinazolinedione, is provided on the surface of, and a passivation film PG made of nitride SiN and silicon oxide SiO 2 is further provided under the α-ray protective film AG.
Is provided.
【００１３】前述のように、ＢＰ１及びＢＰ２等に代表
される複数のバンプパッドは、回路の電源電圧又は接地
電位供給点となるものであって、半導体基板ＳＵＢに形
成された集積回路群に対して回路の電源電圧又は接地電
位を供給する。この実施例の半導体装置において、これ
らのバンプパッドは、上記のように比較的小さなハンダ
バンプを介して電源バスバーＢＢＣ又は接地バスバーＢ
ＢＳに結合され、その結合部には、従来のワイヤボンデ
ィングで問題となるような寄生インダクタンスは存在し
ない。その結果、この実施例の半導体装置では、寄生イ
ンダクタンスを原因とするパルス性の電源ノイズが抑制
され、これによって半導体装置の動作が安定化されるも
のとなる。As described above, the plurality of bump pads typified by BP1 and BP2, etc. serve as power supply voltage or ground potential supply points of the circuit, and are different from the integrated circuit group formed on the semiconductor substrate SUB. Supply the power supply voltage or ground potential of the circuit. In the semiconductor device of this embodiment, these bump pads are connected to the power supply bus bar BBC or the ground bus bar B via the relatively small solder bumps as described above.
It is coupled to the BS and there is no parasitic inductance at that junction that would be a problem with conventional wire bonding. As a result, in the semiconductor device of this embodiment, pulsed power supply noise due to parasitic inductance is suppressed, and the operation of the semiconductor device is stabilized.
【００１４】図３には、この発明が適用された半導体装
置の第２の実施例の基板接続図が示されている。以下、
前記第１の実施例と異なる部分について説明を追加す
る。FIG. 3 is a board connection diagram of a second embodiment of a semiconductor device to which the present invention is applied. Less than,
A description will be added to the portions different from the first embodiment.
【００１５】図３において、点線で示されるＢＰ３等の
バンプパッドは、図４に示される従来例と同様に、ボン
ディングパッドＰＡＤとともに半導体基板ＳＵＢの中央
部に整列して配置される。このため、電源バスバーＢＢ
Ｃ及び接地バスバーＢＢＳには、バンプパッドＢＰ３等
と結合すべく複数の引き出し部が設けられる。これによ
り、前記第１の実施例と同様な効果を得つつ、パッドの
所要レイアウト面積を縮小し、半導体装置のチップ面積
を縮小することができる。In FIG. 3, the bump pads such as BP3 indicated by the dotted line are aligned with the bonding pad PAD in the central portion of the semiconductor substrate SUB, as in the conventional example shown in FIG. Therefore, the power bus bar BB
C and the ground bus bar BBS are provided with a plurality of lead portions for coupling with the bump pads BP3 and the like. As a result, the required layout area of the pad and the chip area of the semiconductor device can be reduced while obtaining the same effect as that of the first embodiment.
【００１６】以上の本実施例に示されるように、この発
明をＬＯＣパッケージ方式を採る半導体装置に適用する
ことで、次のような作用効果が得られる。すなわち、 （１）ＬＯＣパッケージ方式を採る半導体装置におい
て、電源電圧又は接地電位供給用のパッドと電源バスバ
ー又は接地バスバーとの間を、例えばＣＣＢ技術を用い
てバンプ結合し、その他のパッドと対応するインナーリ
ードとの間を、従来通りボンディングワイヤを介して結
合することで、電源電圧又は接地電位供給用のパッドと
電源バスバー又は接地電位バスバーとの結合部における
寄生インダクタンスを低減できるという効果が得られ
る。 （２）上記（１）項により、ＬＯＣパッケージ方式を採
る半導体装置のバルス性の電源ノイズを抑制し、その動
作を安定化できるという効果が得られる。 （３）上記（１）項及び（２）項において、電源バスバ
ー及び接地バスバーに、電源電圧又は接地電位供給用の
パッドとの結合部となる複数の引き出し部を設けること
で、パッドの所要レイアウト面積を縮小し、半導体装置
のチップ面積を縮小することができるという効果が得ら
れる。By applying the present invention to a semiconductor device adopting the LOC package system as shown in the above embodiment, the following operational effects can be obtained. That is, (1) In a semiconductor device adopting the LOC package method, a pad for supplying a power supply voltage or a ground potential and a power supply bus bar or a ground bus bar are bump-bonded by using, for example, CCB technology to correspond to other pads. By coupling the inner lead with the bonding wire as in the conventional case, it is possible to reduce the parasitic inductance in the coupling portion between the pad for supplying the power supply voltage or the ground potential and the power supply bus bar or the ground potential bus bar. .. (2) According to the above item (1), it is possible to suppress the pulsating power source noise of the semiconductor device adopting the LOC package method and stabilize the operation. (3) In the above items (1) and (2), the power supply busbar and the ground busbar are provided with a plurality of lead-out portions that are to be connected to the pads for supplying the power supply voltage or the ground potential. The effect that the area can be reduced and the chip area of the semiconductor device can be reduced is obtained.
【００１７】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、この発明は、上記実
施例に限定されるものではなく、その要旨を逸脱しない
範囲で種々変更可能であることは言うまでもない。例え
ば、図１及び図３において、ハンダバンプを介して結合
されるインナーリードは、電源バスバー及び接地バスバ
ーに限定されない。また、これらの実施例において、ボ
ンディングパッドＰＡＤならびにバンプパッドＢＰ１及
びＢＢ２等はすべて同一の大きさで形成されているが、
バンプパッドＢＰ１及びＢＰ２等は、必要とされるハン
ダバンプの大きさにあわせて小さくすることができる。
半導体基板ＳＵＢ及びリードフレームＬＦならびに各パ
ッドの具体的な形状及び構造は、種々の実施形態を採り
うる。図２において、接着フィルムＡＦの材質や半導体
基板ＳＵＢの保護膜等の種別及び材質は、この実施例に
よる制約を受けない。Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIGS. 1 and 3, the inner leads coupled via the solder bumps are not limited to the power bus bar and the ground bus bar. Further, in these embodiments, the bonding pad PAD and the bump pads BP1 and BB2 are all formed in the same size.
The bump pads BP1, BP2, etc. can be made smaller according to the size of the solder bump required.
The semiconductor substrate SUB, the lead frame LF, and the specific shapes and structures of the pads can adopt various embodiments. In FIG. 2, the type and material of the adhesive film AF, the protective film of the semiconductor substrate SUB and the like are not restricted by this embodiment.
【００１８】以上の説明では、主として本発明者によっ
てなされた発明をその背景となった利用分野であるＬＯ
Ｃパッケージ方式を採る半導体装置に適用した場合につ
いて説明したが、それに限定されるものではなく、リー
ドフレーム及びパッド間の結合が半導体基板面上で行わ
れる各種の半導体装置に広く適用できる。In the above description, the LO, which is the field of application of the invention mainly made by the present inventor, was the background.
The case where the present invention is applied to the semiconductor device adopting the C package method has been described, but the present invention is not limited to this and can be widely applied to various semiconductor devices in which the bonding between the lead frame and the pad is performed on the semiconductor substrate surface.
【００１９】[0019]
【発明の効果】ＬＯＣパッケージ方式を採る半導体装置
において、電源電圧又は接地電位供給用のパッドと電源
バスバー又は接地バスバーとの間を、例えばＣＣＢ技術
を用いてバンプ結合し、その他のパッドと対応するイン
ナーリードとの間を、従来通りボンディングワイヤを介
して結合することで、電源電圧又は接地電位供給用のパ
ッドと電源バスバー又は接地電位バスバーとの結合部に
おける寄生インダクタンスを低減できるため、ＬＯＣパ
ッケージ方式を採る半導体装置におけるバルス性の電源
ノイズを抑制し、その動作を安定化することができる。In the semiconductor device adopting the LOC package system, the pad for supplying the power supply voltage or the ground potential and the power supply bus bar or the ground bus bar are bump-bonded by using, for example, the CCB technique to correspond to other pads. By coupling the inner lead with a bonding wire as in the conventional case, it is possible to reduce the parasitic inductance in the coupling portion between the pad for supplying the power supply voltage or the ground potential and the power supply bus bar or the ground potential bus bar. It is possible to suppress the pulsating power supply noise in the semiconductor device adopting the above-mentioned method and stabilize its operation.
【図１】この発明が適用された半導体装置の第１の実施
例を示す基板接続図である。FIG. 1 is a substrate connection diagram showing a first embodiment of a semiconductor device to which the present invention is applied.
【図２】図１の半導体装置の一実施例を示すＡ−Ｂ断面
構造図である。FIG. 2 is a cross-sectional structural view taken along the line AB, showing an embodiment of the semiconductor device of FIG.
【図３】この発明が適用された半導体装置の第２の実施
例を示す基板接続図である。FIG. 3 is a substrate connection diagram showing a second embodiment of a semiconductor device to which the present invention is applied.
【図４】従来の半導体装置の一例を示す基板接続図であ
る。FIG. 4 is a substrate connection diagram showing an example of a conventional semiconductor device.
ＳＵＢ・・・半導体基板、ＬＦ・・・リードフレーム、
ＢＢＣ・・・電源バスバー、ＢＢＳ・・・接地バスバ
ー、ＢＰ１〜ＢＰ３・・バンプパッド、ＰＡＤ・・・ボ
ンディングパッド、ＢＷ・・・ボンディングワイヤ。Ｂ
１〜Ｂ２・・・ハンダバンプ、ＡＦ・・・接着フィル
ム、ＡＧ・・・α線保護膜、ＰＧ・・・パッシベーショ
ン膜。SUB: semiconductor substrate, LF: lead frame,
BBC ... Power supply bus bar, BBS ... Ground bus bar, BP1 to BP3 ... Bump pad, PAD ... Bonding pad, BW ... Bonding wire. B
1-B2 ... Solder bump, AF ... Adhesive film, AG ... Alpha ray protective film, PG ... Passivation film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山口 泰紀 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 菅 進一 千葉県茂原市早野3681番地 日立デバイス エンジニアリング株式会社内 (72)発明者 野副 敦史 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuki Yamaguchi 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Shinichi Suga 3681 Hayano, Mobara City, Chiba Hitachi Device Engineering Co., Ltd. ( 72) Inventor Atsushi Nozoe 2326 Imai, Ome City, Tokyo Metropolitan Government Device Development Center, Hitachi, Ltd.
Claims (4)
リードに結合される第１のパッドと、ボンディングワイ
ヤを介して対応するインナーリードに結合される第２の
パッドとを具備することを特徴とする半導体装置。1. A semiconductor device comprising: a first pad coupled to a corresponding inner lead via a solder bump; and a second pad coupled to a corresponding inner lead via a bonding wire. apparatus.
式を採るものであって、上記第１のパッドが結合される
インナーリードは、電源バスバー及び／又は接地バスバ
ーであることを特徴とする請求項１の半導体装置。2. The semiconductor device adopts a LOC package system, and the inner lead to which the first pad is coupled is a power supply bus bar and / or a ground bus bar. Semiconductor device.
上記第１のパッドとの結合部を除く他の部分において、
所定の接着フィルムを介して上記半導体基板と接合され
るものであることを特徴とする請求項２の半導体装置。3. The power supply bus bar and the ground bus bar,
In other parts except the connection part with the first pad,
The semiconductor device according to claim 2, wherein the semiconductor device is bonded to the semiconductor substrate via a predetermined adhesive film.
は、上記第１のパッドとの結合部となる引き出し部が設
けられるものであることを特徴とする請求項２又は請求
項３の半導体装置。4. The semiconductor device according to claim 2, wherein the power supply bus bar and the ground bus bar are provided with a lead-out portion which is a connecting portion with the first pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30405091A JPH05114622A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30405091A JPH05114622A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05114622A true JPH05114622A (en) | 1993-05-07 |
Family
ID=17928443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30405091A Pending JPH05114622A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05114622A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990000382A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | Lead frame, chip scale package using same and manufacturing method thereof |
| EP0867938A3 (en) * | 1997-03-28 | 1999-03-10 | Oki Electric Industry Co., Ltd. | Semiconductor device comprising electrode pads and leads |
| KR100366383B1 (en) * | 1999-04-19 | 2002-12-31 | 캐논 가부시끼가이샤 | Semiconductor integrated circuit and printed wiring substrate provided with the same |
-
1991
- 1991-10-23 JP JP30405091A patent/JPH05114622A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0867938A3 (en) * | 1997-03-28 | 1999-03-10 | Oki Electric Industry Co., Ltd. | Semiconductor device comprising electrode pads and leads |
| US6137166A (en) * | 1997-03-28 | 2000-10-24 | Oki Electric Industry Co., Ltd. | Semiconductor device |
| KR19990000382A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | Lead frame, chip scale package using same and manufacturing method thereof |
| KR100366383B1 (en) * | 1999-04-19 | 2002-12-31 | 캐논 가부시끼가이샤 | Semiconductor integrated circuit and printed wiring substrate provided with the same |
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