JPH05108587A - Parallel arithmetic unit - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize an electronic / device-like structure that speeds up data transmission between processors and makes the transmission line structure flexible in order to improve the processing capability and versatility of the parallel computing device. is there. [Structure] The synchronization control unit 4 is a processor element (PE)
For 5, the processing start timing control is performed. The processing start timing may be obtained from the internal processing state of the parallel arithmetic device or may be external synchronization. The connection control unit 7 determines the P determined according to the algorithm to be processed.
The internal connection status of the bus switch network 6 is controlled so as to realize the connection form of the E group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel arithmetic unit, and more particularly to a structure of a fast and flexible interprocessor linkage.

[0002]

2. Description of the Related Art In a method for realizing high-speed processing by configuring a parallel operation mechanism using a plurality of processors, it is important to improve the data transmission speed and efficiency between the processors, and The flexibility of the structure of the data transmission path between them is important for ensuring the versatility of the arithmetic unit. There is a strong demand for improved data transmission speed and flexibility between processors. Realization of high processing performance depends on the electrical characteristics and structural constraints of the data transmission path between the processors.

For example, Japanese Patent Application Laid-Open No. 3-174646 is related to the above, which employs a method of connecting a plurality of processors by a hardwired transmission network of a serial transmission system.

[0004]

Generally, a parallel arithmetic processing unit can improve the superficial processing capacity by increasing the number of connected processors, but the overall processing capacity is the data transmission capacity between the processors. Is often a bottleneck and does not improve.

Originally, in order to improve the data transmission speed,
The parallel data bus may be adopted and the transmission path length may be shortened. Further, in order to improve the degree of freedom of connection between the processors, the processors may be connected in a mesh. However, it was difficult to satisfy all of these conditions at the same time due to the restrictions on the implementation.

An object of the present invention is to realize an electronic / device-like structure for speeding up data transmission between processors and making a transmission line structure flexible in order to improve the processing capability and versatility of a parallel arithmetic device. is there.

[0007]

The features of the present invention for achieving the above object are as follows. (1) A linkage bus switch network is used as a chassis unit to minimize the data transmission path length between processors. Configured on the backboard.

(2) In order to minimize the transmission delay of the linkage bus switch network, the transmission switching network is connected from the entrance to the exit.
It was built on a single integrated circuit for all inputs and outputs, and the total line length was shortened and the delay due to the connection between elements was minimized.

(3) In order to prevent the number of connection pins of the integrated circuit for the transmission switching network from becoming excessive in (3) and (2), the bus line is bit-sliced and divided, and each processor element corresponding to this division is divided. The wiring of the integrated circuit for the transmission switching network is divided and the wiring is made in multiple layers on the backboard.

(4) In order to minimize the total line length of the linkage bus switch network, a plurality of integrated circuits for the transmission switching network are arranged in the center of the backboard.

[0011]

According to the present invention, the path length of a memory bus used as a data transmission line between processor elements can be mounted in the shortest, the number of logic gates through which the data transmission line passes can be minimized, and the integrated circuit element can be integrated. Can be realized. as a result,
It is possible to prevent lowering of processability due to the data transfer neck of the linkage part, and to realize high processability of the parallel arithmetic device as a whole, and to reduce the cost of the entire device because ordinary parts widely used can be used. ..

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, a parallel or pipeline processing or a combination of both of them having a structure most suitable for the processing target (hereinafter, referred to as "parallel / pipeline processing") (Referred to as)) is related to the structure of the device. In the device according to the present invention, in order to realize high-speed operation, not only the processing capability as a parallel operation device is increased, but also the parallel operation is arbitrarily performed depending on the target.
The feature is that the processing structure of the pipeline can be changed.
In order to improve the processing capability and versatility of such a parallel processing device, it is indispensable to realize an electronic / device-like structure that speeds up data transmission between processors and makes the transmission line structure flexible. The present invention relates to realization of an electronic / device structure of a parallel arithmetic device.

An embodiment of the present invention will be described below with reference to FIG. A processor element (hereinafter referred to as PE) 5 is a processor in charge of parallel / pipeline processing, and includes a plurality of processors. The management processor 1 controls and controls the entire operation of the parallel arithmetic device, and may be a commercially available microprocessor board. The memory 2 is used for storing a processing program of the management processor 1 and data, and a work area. External interface 3
Is for data communication when the parallel computing device is used in connection with an external host computer, and the external interface signal line 9 is an industry standard such as Ethernet. The synchronization control unit 4 controls the timing of the processing start via the PE synchronization control signal line 14 for the plurality of PEs 5 that perform parallel / pipeline processing. The processing start timing may be obtained from the internal processing state of the parallel arithmetic device or may be external synchronization. The bus switch network 6 arbitrarily realizes the connection form of the plurality of PEs 5 and realizes a desired parallel / pipeline processing structure. The connection control unit 7 determines the PE determined according to the algorithm to be processed.
The internal connection status of the bus switch network 6 is controlled via the bus switch network connection control signal line 10 so as to realize the group connection form. The management processor bus 8 is the management processor 1
PE based on the progress of processing or an external command
A data path for controlling the group, the connection control unit 7, and other devices connected to the bus 8, which is an industry standard bus such as the VME bus. The PE-to-PE interface buses 11 and 12 are P
E is a memory bus for directly reading and writing the memory of the other side by the memory bus.

FIG. 2 shows a processor element (PE) 5
Is the internal structure of. The processor 14 to which the processor element (PE) synchronization control signal line 13 is connected is preferably a processor suitable for high-speed calculation, and may be, for example, a general-purpose DSP (digital signal processor). The management processor bus interface 15 is for exchanging information with the management processor 1 and is well known such as an industry standard VME bus or Ethernet. Management processor 1
Via the management processor bus interface 15
It is possible to obtain the processing result and the internal state of the processing unit 14 in addition to loading the processing program to the processing unit 14, changing the setting of the processing parameter, and controlling the change of the processing content. The arithmetic processor memory bus 20 is a bus for the processing unit 14 to access the high speed memory. Interface bus between PEs (without replacement buffer memory) 11
Is a bus for direct memory access to the alternate buffer memory of another connected PE, and is composed of a data bus and an address bus. In FIG. 2, the bus 11
However, it is possible to connect other PEs that can be connected via the alternate buffer memory by the number of buses. The PE-to-PE interface bus (with replacement buffer memory) 12 is for realizing data transmission between PEs by allowing another PE to access the replacement buffer memory in its own PE. The reason why there are two buses 12 is similar to the case of the bus 11.

The alternation buffer memory (1) 16 and the alternation buffer memory (2) 17 are connected to each other through the memory bus changeover switch 18 and the PE-to-PE interface bus between the processing unit 14 in its own PE and the processing units of other PEs. 11) (without replacement buffer memory). The internal connection state of the memory bus changeover switch 18 is switched between forward connection and reverse connection depending on the state of the memory bus changeover switch control signal line 19. The data bus and the address bus are to be switched.

FIG. 3 shows the logical structure of the bus switch network. The function of the bus switch network can be freely set for all or some of the PE groups in the parallel arithmetic unit by program control of the memory bus connection. Is to realize.
The bus switch network of FIG. 3 has an input bus group 21 and an output bus group 2
A switching connection between the two is realized, and the input bus group 21
Is connected to the interface bus (with replacement buffer memory) 12 of each PE, and the output bus group 22 is connected to the interface bus (without replacement buffer memory) 11 of each PE. The logical structure of the bus switch network is to connect the bus switch elements 23 as shown in FIG. Figure 3
Shows an example in which the number of PEs to be connected is 16, but the bus switch elements 23 form a group and are composed of rows 0 to 15 corresponding to each PE and five columns from the 0th column to the 4th column. To be done. Each bus switch element performs connection exchange between a plurality of bus inputs and a plurality of bus outputs based on an external control signal. That is, the bus switch element 23 in the fourth column is connected to one of two outputs in response to an external control signal for one input, and the bus switch element 23 in the third column is connected to four inputs for two inputs in accordance with an external control signal. The output is connected without duplication. The second row bus switch element 23 is 1
Two 2-input 2-output bus switch elements are arranged for each row, and each of them is exchange-connected by the external control signal without duplication. First row bus switch element 2
Reference numeral 3 is a 4-input 2-output bus switch element. Connection PE
When the number is 16, two inputs are connected at the same time out of the four inputs, so these two inputs are exchange-connected to the two outputs by the external control signal without duplication. The bus switch element 23 in the 0th column is a 2-input 1-output bus switch element. However, when the number of connected PEs is 16, only one input is connected at the same time out of the two inputs, so the output is output as it is. To do.

With the bus switch network having the configuration shown in FIG.
Any input PE bus can be any output PE without overlapping
Can be interchangeably connected to the bus.

FIG. 4 shows the structure of an integrated circuit device for a bus switch network. The control unit 26 controls the bus switch element state of each matrix based on an external signal from the control interface signal line 28. A bus switch network 27, an input bus group 29, and an output bus group 3 which are connected to the control unit 26 via a bus switch element state control signal line 31.
0 is the same as the structure of FIG. 3, but the input bus group 29 and the output bus group 30 are provided in order to avoid the pin number constraint of the integrated circuit element.
Each is integrated with a bit slice. For example, if the address bus is 24 bits and the data bus is 32 bits, by bit-slicing the address bus with 3 bits and the data bus with 4 bits, all bus switch networks can be realized with 8 integrated circuit elements. What is important here is to collectively integrate all the bus switch networks from the input bus group 29 to the output bus group 30 to minimize the propagation delay. The control unit 26 controls the control interface signal line 2
A bus switch element state control signal 38, a timing signal 39, and a bus switch network integrated circuit element switching command 40 are received from the connection control unit 7 via 8, and a bus switch network integrated circuit element switching completion signal 35 is connected and controlled. Send to part 7. The bus switch element state control signal 38 transmits the state values of all the bus switch elements constituting the bus switch network serially or in parallel. In this device, serial transmission is preferable because the number of signal lines is likely to be restricted. In that case, the timing signal 39 is used as a bit synchronization signal. When all the bus switch element state control signals 38 have been received by the control unit 26, the bus switch network integrated circuit element switching completion signal 35 is transmitted to the connection control unit 7 as a reception completion signal. The bus switch network integrated circuit element switching command 40 is a timing command signal for switching the bus switch network state to the bus switch element state received by the bus switch element state control signal 38, and the internal state of the bus switch network integrated circuit element is When the switching is completed, the bus switch network integrated circuit element switching completion signal 35 is transmitted to the connection control unit 7.

FIG. 5 shows the configuration of a bus switch network 6 including a connection control unit 7 and a plurality of bit slice type integrated circuit elements 25 for the bus switch network. The input bus group 29 and the output bus group 30 shown in FIG. 5 are obtained by integrating the input bus and the output bus of the plurality of bit-sliced integrated circuit elements 25 for the bus switch network, and are the same as those of the processor element (PE) shown in FIG. One pair of each of the input bus 11 and the output bus 12 can be connected to all PEs. In the example of PE in FIG. 2, two input buses 11 and two output buses 12 are provided.
Since two sets are provided, two sets of the input bus group 29, the output bus group 30, and the bus switch network integrated circuit element 25 group in FIG. 5 are required. The bus switch network connection data instructed by the management processor 1 is the management processor interface bus 3
2 via the management processor interface unit 33
The bus switch element state control signal 38 and the timing signal 39 are applied to the integrated circuit device 25 for the bus switch network.
Broadcast to the group. After the broad cast, all internal connection states of the integrated circuit device 25 for the bus switch network are changed by the command 40 for switching the integrated circuit device for the bus switch network. When the change is completed, each bus switch network integrated circuit element outputs a bus switch network integrated circuit element switching completion signal 35. Is confirmed by AND gate processing, the bus switch network integrated circuit all-device switching completion signal 36, and when switching fails, the switching failure bus switch network integrated circuit device identification number 37 is given to the management processor interface unit 3
3 to the management processor 1.

FIG. 6 is a structural view showing the mounting of the PE group and the bus switch network 6, in which a plurality of processor section printed boards 43 each having a PE mounted therein are inserted into a unit chassis 41. A bus connector which can be inserted into the backboard unit 42 is attached to each processor printed board 43, and the management processor interface bus connector 44 is used for data communication with the management processor 1. The management processor interface bus may be a general purpose processor bus such as the VME bus. The input / output bus connector (No. 1) 45 mounts a pair of PE-to-PE interface buses 11 (without replacement buffer memory) and a pair of PE-to-PE interface buses 12 (with replacement buffer memory) in each PE. Address bus 2
In the case of 4 bits and 32 bits of data bus, the total number of signal lines is 106. Input / output bus connector (2) 46 is P
Another pair of PE-to-PE interface buses 11 (without replacement buffer memory) and a PE-to-PE interface bus 12 (with replacement buffer memory) 12 are mounted in E. The backboard unit 42 mounts a bus switch network between PEs in addition to a general-purpose processor bus such as a VME bus. Figure 7
Shows an example of the structure of the backboard.
A general-purpose processor bus such as the ME bus and a printed board connector are mounted. Input / output bus connector (No. 1) 45 and input / output bus connector (No. 2) in the middle and lower stages
46 is placed. Input / output bus connectors (No. 1) in the middle and lower stages of the processor printed circuit board 43 equipped with PE
45 and the input / output bus connector (No. 2) 46 are arranged on both sides except the central portion of the unit chassis 41.

As shown in FIG. 7, the required number of integrated circuit devices 25 for the bus switch network are mounted in the center of the backboard section 42 in the configuration of FIG. If it cannot be mounted on one side of the backboard, it may be mounted on both sides of the backboard. What is important here is that the processor printed boards 43 on which PEs are mounted are arranged on both sides of the unit chassis 41 excluding the central part, and the integrated circuit elements 25 for the bus switch network are centrally arranged in the central part of the backboard. This is to minimize the length of the signal lines mounted in the bus switch network between them and minimize the data transmission delay time. The central part and the lower part of the backboard in which the integrated circuit elements 25 for the bus switch network are centrally arranged are mounted with a general-purpose processor bus such as a VME bus and a printed board connector, a printed board for the management processor 1 and a printed board for the external interface 3. etc,
A printed board other than PE is placed.

FIG. 8 shows a back board printed board having a multi-layered structure (for example, connection connection layer 50 corresponding to integrated circuit device (1) for bus switch network, connection connection layer 51 corresponding to integrated circuit device (2) for bus switch network, The integrated circuit element (n) corresponding to the integrated circuit element (n) for the bus switch network is formed), and the middle and lower input / output bus connectors (part 1) corresponding to the plurality of integrated circuit elements 25 for the bus switch network are provided. Four
5, an example in which the connection portion with the input / output bus connector (No. 2) 46 is formed by forming a multilayered structure in a plurality of layers, and the restriction due to excessive linear density within one layer is avoided. On the printed board, the input / output bus connector arrangement area 53 and the bus switch network integrated circuit element (for example, bus switch network integrated circuit element (1) 47, bus switch network integrated circuit element (2) 4).
8, integrated circuit device (n) 49 for bus switch network, etc.).

[0023]

According to the present invention, versatile data linkage between processor elements can be realized by a high-speed memory access system. As a result, it is possible to prevent a decrease in processability due to a data transfer neck of the linkage unit, and it is possible to realize high processability as the entire parallel arithmetic device. In this method, MO
It is possible to apply S and ordinary printed board technology, and low-cost hardware realization by air cooling is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 shows a processor element (P according to an embodiment of the present invention).
Configuration example of E).

FIG. 3 is a logical structure diagram of a bus switch network according to an embodiment of the present invention.

FIG. 4 is a configuration of an integrated circuit device for a bus switch network according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a bus switch network using an integrated circuit device for a bus switch network according to an embodiment of the present invention.

FIG. 6 is a structural diagram of an embodiment of the present invention.

FIG. 7 is an example of a backboard structure according to an embodiment of the present invention.

FIG. 8 is a backboard multilayer structure of one embodiment of the present invention.

[Explanation of symbols]

1 ... Management processor, 2 ... Memory, 3 ... External interface, 4 ... Synchronous control unit, 5 ... Processor element (PE), 6 ... Bus switch network, 7 ... Connection control unit, 8 ...
Management processor bus, 9 ... External interface signal line, 10 ... Bus switch network connection control signal line, 11 ... Processor element (PE) interface bus (without replacement buffer memory), 12 ... Processor element (PE) interface bus ( Alternate buffer memory), 13 ... Processor element (PE) synchronization control signal line, 14 ... Processing unit, 15 ... Management processor bus interface, 16 ... Alternate buffer memory (1), 17 ...
Alternate buffer memory (2), 18 ... Memory bus changeover switch, 19 ... Memory bus changeover switch control signal line, 20 ... Arithmetic processor memory bus, 21 ... Input bus group, 22 ... Output bus group, 23 ... Bus switch element, 24
... connection path between bus switch elements, 25 ... integrated circuit element for bus switch network, 26 ... control unit, 27 ... bus switch network,
28 ... Control interface signal line, 29 ... Input bus group, 30 ... Output bus group, 31 ... Bus switch element state control signal line, 32 ... Management processor interface bus, 33 ... Management processor interface section, 34 ...
Switching state determination unit, 35 ... Bus switch network integrated circuit element switching completion signal, 36 ... Bus switch network integrated circuit element switching completion signal, 37 ... Switching failure Bus switch network integrated circuit element identification number, 38 ... Bus switch Element state control signal, 39 ... Timing signal, 40 ... Bus switch network integrated circuit element switching command, 41 ... Unit chassis, 42 ... Backboard section, 43 ... Processor section printed board, 44 ... Management processor interface bus connector, 45 ... I / O bus connector (1),
46 ... Input / output bus connector (No. 2), 47 ... Bus switch network integrated circuit element (1), 48 ... Bus switch network integrated circuit element (2), 49 ... Bus switch network integrated circuit element (n), 50 ... Bus switch network integrated circuit element (1) corresponding connection connection layer, 51 ... Bus switch network integrated circuit element (2) corresponding connection connection layer, 52 ... Bus switch network integrated circuit element (n) corresponding connection connection layer , 53 ... Input / output bus connector arrangement area.

Claims (5)

[Claims] 1. A processor group comprising a plurality of processors connected to each other, a management processor managing the processing of the processor group, and a memory bus connecting the processors via a bus switch network, A parallel arithmetic device, wherein the processor group section is configured by using a plurality of uniform printed boards, mounted in a unit chassis, and a bus switch network is realized by a backboard section. 2. The bus switch network according to claim 1, wherein the bus switch connection switch section and the printed circuit board connection connection section are integrated, and the bus exchange connection switch section from an input stage to an output stage is integrated. Parallel computing device characterized by. 3. The bus exchange connection switch according to claim 1, wherein the bus exchange connection switch unit and the printed circuit board connection connection unit that compose the bus switch network are divided into groups each having a specific number of bits and divided. Parallel operation, characterized in that parts are integrated by bit slices corresponding to the groups, and the printed board connection wiring parts are formed by stacking printed boards by dividing layers by bit slices corresponding to the groups. apparatus. 4. A parallel arithmetic unit according to claim 1, wherein an exchange switch network integrated circuit which constitutes the bus switch network is arranged on a backboard. 5. The control unit printed board other than the processor group is arranged in the central portion of the unit chassis, the processor group printed boards are evenly arranged on the left and right sides of the unit, and the exchange switch network is arranged in the central portion of the backboard. A parallel arithmetic device having an integrated circuit arranged therein.