JPH0510739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a servo device for a rotating body equipped with a phase error detection counter and a speed error detection counter.

Configuration of conventional example and its problems Figure 1 shows a typical block diagram of the servo system of a home video tape recorder during playback.
Reference numeral 1 denotes a cylinder motor that drives a rotating cylinder to which a head for recording and reproducing video signals is attached. A position detector 3 that generates a single position detection signal is connected.

The output signal of the frequency generator 2 is amplified and waveform-shaped by an FG signal amplifier 4, and its output is supplied to a frequency divider 5 and a controller 6.
The output of the position detector 3 is amplified and waveform-shaped by a PG signal amplifier 7, and the output is supplied to a frequency divider 8, which is half of the frequency divider 5, as a reset signal.

Furthermore, the output signal of the clock generator 9 is transmitted to the frequency divider 1.
0 to a cylinder phase counter 11, a cylinder speed counter 12, a capstan phase counter 32 (described later), and a capstan speed counter 28 (described later) as clock signals.

The number of bits of the cylinder phase system counter 11 is
It has a 16-bit configuration, and preset data is supplied from a 16-bit cylinder phase system ROM (read-only memory) 13, and its output is supplied to a decoder 14 and a 10-bit latch 15. The output of the latch 15 is supplied as a preset signal to the cylinder phase system counter 11, the second output is supplied to the delay circuit 16, and the output data of the latch 15 is sent to a 10-bit DA converter (digital-to-analog converter). 17 is supplied.

Note that the latch 15 is connected to the cylinder phase system.
LSB of 16-bit output data of ROM13
(lowest bit) is supplied.

Further, the output of the frequency divider 8 is supplied to the latch 15 as a load signal, and the output of the frequency divider 8 is supplied to the latch 15 as a load signal.
The first output of the 8-bit latch 18 is supplied as a load signal, and the second output is supplied as a preset signal to the cylinder speed counter 12.

The cylinder speed system counter 12 has a 12-bit configuration, and the cylinder speed system counter 12 has a 12-bit configuration.
Preset data is supplied from the ROM 19, the lower 8 bits of the output data including the LSB are supplied to the latch 18, and the output data of the latch 18 is supplied to the 8-bit D-A converter 20. .

Furthermore, the D-A converter 17 and the D-A converter 17 and the D-A converter 17 and
The outputs of the A converter 20 are combined by a combining circuit 21, and the output signal of the combining circuit 21 is supplied to a cylinder motor drive circuit 22.

On the other hand, a frequency generator 24 is connected to a capstan motor 23 for running the magnetic tape, and the output signal of the frequency generator 24 is amplified and waveform-shaped by an FG signal amplifier 25 and then sent to a controller 26. The first output of the controller 26 is supplied as a load signal to an 8-bit latch 27, and the second output is supplied as a preset signal to a 10-bit capstan speed counter 28.

Also, a control head 29 plays back control signals recorded on the magnetic tape at regular intervals.
The output signal is amplified and waveform-shaped by a control signal amplifier 30, and then supplied to a 10-bit latch 31 as a load signal.

Clock signals are supplied from the frequency divider 10 to the capstan speed counter 28 and the 15-bit capstan phase counter 32, respectively.

The capstan phase system counter 32 is supplied with a preset signal from the delay circuit 16, and of its output data, the lower 10 bits including the LSB are supplied to the latch 31, and the output data of the latch 31 is 10 bits. is supplied to the D-A converter 33.

Preset data is supplied to the capstan speed system counter 28 from a 10-bit capstan speed system ROM 34, and among the output data,
The lower 8 bits of data including the LSB are supplied to the latch 27, and the output data of the latch 27 is supplied to an 8-bit DA converter 35.

Furthermore, the D-A converter 33 and the D-A converter 33 and the D-A converter 33 and the D-A converter 33 and
The outputs of the A converter 35 are combined by a combining circuit 36, and the output signal of the combining circuit 36 is supplied to a capstan motor drive circuit 37.

In FIG. 1, it is assumed that a frequency generator 2 connected to a cylinder motor 1 generates an AC signal of 6 cycles per rotation, and a frequency divider 5 is set to 1/3.
It is assumed that the frequency divider 8 performs a frequency division operation of 1/2.

In addition, according to the NTSC specification (a standard for television broadcasting adopted in Japan and the United States), the reference rotation speed of the cylinder motor 1 is 1800 rpm, and the output frequency of the frequency generator 2 is 180 Hz. The output frequency of device 3 is 30Hz.

Therefore, a square wave having a phase dependent on the rotational phase of the cylinder motor 1 and a duty of 50% is obtained from the frequency divider 8, and this signal becomes the rotational phase signal.

Further, a clock signal of a constant frequency is supplied to the cylinder phase system counter 11, and when a predetermined count value is reached, the decoder 14 generates an output pulse, so that the first output of the decoder 14 is The second output becomes a reference phase signal of the capstan phase system after passing through a delay circuit 16 for tracking adjustment.

Furthermore, since the control head 29 obtains a control reproduction signal that depends on the running phase of the magnetic tape, the output signal of the control signal amplifier 30 becomes a running phase signal of the capstan phase system.

On the other hand, the FG signal amplifier 4 obtains a rotational speed signal of the rotating cylinder, and the FG signal amplifier 25 obtains a rotational speed signal of the capstan.

At the leading edge of the output signal of the FG signal amplifier 4, the controller 6 first latches the count value of the cylinder speed counter 12.
8, and then a preset signal for the cylinder speed counter 12.

In addition, the capstan speed controller 26
The operation of is also the same as that of the controller 6.

Therefore, the cylinder phase system latch 15 holds the measurement result of the phase difference between the rotational phase signal of the cylinder system and the reference phase signal, and the cylinder speed system latch 18 holds the measurement result of the period of the rotational speed signal. Similarly, the latch 31 of the capstan phase system holds the measurement result of the phase difference of the capstan system, and the latch 27 of the capstan speed system holds the measurement result of the period of the rotational speed signal of the capstan.

A detailed explanation of these operations is given in Japanese Patent Publication No. 53-19745 or US Pat. No. 3,836,756.

The output of the latch 15 (measured output of the cylinder phase counter 11) is converted into a DC voltage by the DA converter 17, and the latch 18 (measured output of the cylinder speed counter 12) is converted to a DC voltage by the DA converter 17. Therefore, it is converted into a DC voltage, and these DC voltages are combined by a combining circuit 21 to create an error output signal for the cylinder system, and the error output signal is used to generate a cylinder motor drive circuit 22.
The cylinder motor 1 is driven via.

Further, the output of the latch 31 (measured output of the capstan phase system counter 32) is converted into a DC voltage by the DA converter 33, and the output of the latch 27 (measured output of the capstan speed system counter 28) is converted to a DC voltage by the DA converter 33. 35 into a DC voltage, these DC voltages are combined by a combining circuit 36 to create a capstan system error output signal, and the error output signal is output via a capstan motor drive circuit 37. The capstan motor 23 is driven.

By the way, in FIG. 1, the cylinder phase system counter 11, the cylinder speed system counter 12, and the capstan speed system counter 28 each have individual
Preset data is supplied from the ROM, but these preset data are mainly prepared for double speed playback.

For example, in the NTSC specification of VHS (one of the standards for video tape recorders), the relative speed between the rotating head and the magnetic tape during recording or normal (+1x speed) playback is approximately 5.8 m/sec, but in 2-hour mode the relative speed is +9 m/sec. When the magnetic tape is run at double speed (if the controller 26 divides the output signal of the FG signal amplifier 25 into 1/9, the capstan motor 23 rotates at 9 times the rotational speed, so the magnetic tape Since the scanning direction of the rotating head on the magnetic tape is equal to the normal running direction of the magnetic tape, the relative speed of the rotating head and the magnetic tape becomes slower, and the horizontal synchronization speed of the reproduced The signal frequency decreased by about 4.8%, and on the contrary -
When a magnetic tape is run at 9x speed, the frequency of the reproduced horizontal sync signal increases by about 5.4 percent.

If the frequency of the horizontal synchronization signal changes significantly, the television receiver will be unable to follow it and the synchronization will be disrupted, so it is necessary to correct the relative speed so that it does not change.

Taking +9x speed as an example, in order to correct the relative speed, it is sufficient to prepare preset data such that the count frequency of the cylinder phase system counter 11 is 4.8% higher than during normal playback, and also, Cylinder speed counter 1
The preset data supplied to the capstan speed system counter 2 and the capstan speed system counter 28 are also respectively set so that the speed error output becomes zero during synchronous rotation.

In this way, cylinder phase system ROM13, cylinder speed system ROM19, capstan speed system
The ROM 34 is prepared with a number of data depending on the type of double speed mode required, but according to the NTSC specifications, there are three types of recording and playback time modes: 2 hour mode, 4 hour mode, and 6 hour mode. ,each
The amount of data (number of addresses) required for ROM is considerable.

For example, in each time mode, ±15 times speed, ±9
Double speed, ±5x speed, ±3x speed, ±2x speed, ±1x speed, 0
If double speed (stop) is required, different preset data must be prepared for all except for +1x speed, and the number of addresses for each ROM will be 37, which means that the system as shown in Figure 1 must be prepared. When converting into an LSI (large-scale integrated circuit), not only the area of the ROM part on the chip and the area of the address decoder part attached to it become quite large, but also the inspection of ROM data requires a lot of work. The problem was that it took time.

OBJECTS OF THE INVENTION An object of the present invention is to simplify the structure of a memory means having a plurality of preset data for switching rotational speeds more than ever before.

Structure of the Invention The servo device of the present invention includes an M-bit phase error detection counter that measures a phase difference between a rotational phase signal of a rotating body and a reference phase signal, and an N-bit phase error detection counter that measures a repetition period of a rotational speed signal of the rotating body. control means for generating an error output signal by synthesizing the output of a speed error detection counter of a bit, the output of the phase error detection counter, and the output of the speed error detection counter, and controlling the rotational speed and rotational phase of the rotating body to be constant; , a plurality of Y for switching the rotational speed of the rotating body
a memory means for supplying preset data of bits (Y<M) to at least the phase error detection counter; and a memory means for dividing one count period of the phase error detection counter into a first count mode and a second count mode; In the first counting mode, the phase error detection counter is caused to perform a counting operation based on preset data from the memory means, and in the second counting mode, it is caused to perform a counting operation based on unique preset data prepared separately. The present invention is characterized by comprising a count mode switching means for causing the phase error detection counter to perform a counting operation, or in order to further enhance the effects of the present invention, the switching of the rotational speed of the rotating body is controlled from the memory means. Preset data of a plurality of Z bits (Z<N) is also supplied to the speed error detection counter, and one count period of the speed error detection counter is divided into a first count mode and a second count mode. , said first
In the second counting mode, the speed error detection counter is caused to perform a counting operation based on preset data from the memory means, and in the second counting mode, the speed error detection counter is caused to perform a counting operation based on unique preset data prepared separately. The second one causes the error detection counter to perform counting operation.
The present invention is characterized by comprising a count mode switching means.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of a servo system according to an embodiment of the present invention. Blocks that are the same as those in FIG. 1 are designated by the same numbers, and their explanations will be omitted.

The system shown in FIG. 2 is different from that shown in FIG. 1 in that the cylinder phase counter 11, cylinder speed counter 12, and capstan speed counter 28 of the conventional system are replaced by a cylinder phase count block 40 and a cylinder speed count block, respectively. 41, the capstan speed system count block 42 has been changed, and the three systems of memory that used to supply individual preset data to each counter, namely the cylinder phase system ROM 13,
Cylinder speed meter ROM19, capstan speed system
ROM34 is integrated as the only memory (ROM)
38, and is configured such that preset data is supplied from the memory 38 to three systems of counting blocks via a common data bus 39.

The number of bits of the data bus 39 is equal to the number of bits of the data bus 39.
At the exit of 8, the number is 15 bits, but between the cylinder phase system count block 40 and the cylinder speed system count block 41, it is 11 bits.
9 between the cylinder speed system count block 41 and the capstan speed system count block 42.
It's becoming bit.

By the way, FIG. 3 shows a concrete internal configuration diagram of the cylinder phase system counting block 40, and the first clock signal is supplied from the frequency divider 10 of FIG. 2 to the clock signal input terminal 43. ,
A main preset signal is supplied to the preset signal input terminal 44 from the decoder 14 shown in FIG.

Further, the data input terminals D ₁ to _{D 15} of the cylinder phase system counter 11 are connected to the respective output terminals of 15 single AND-OR gates, one input terminal of which is supplied with preset data from the data bus 39. An output data bus 45 is connected to the output terminals Q ₁ to _{Q 16} of the cylinder phase system counter 11, and in order to detect that the output of the cylinder phase system counter 11 has become [00...000]. of
The input terminal of NOR gate 46 is connected.

One input terminal of a NOR gate 47 is connected to the output terminal of the NOR gate 46.
The other input terminal and output terminal of the gate 47 and the one input terminal and output terminal of the NOR gate 48 are cross-coupled to each other, and the
The other input terminal of NOR gate 48 is connected to the preset signal input terminal 44.

Further, the output terminal of the NOR gate 48 is connected to the D terminal of a D flip-flop 49, and the output terminal of the D flip-flop 49 and the
Each output terminal of the NOR gate 48 has an EX−
The input terminal of the OR gate 50 is connected, and the EX
- The output terminal of the OR gate 50 is connected to the D terminal of the D flip-flop 51, the output terminal of the D flip-flop 51 is connected to the preset input terminal of the cylinder phase system counter 11, and the clock terminal of the D flip-flop 49 is connected to the output terminal of the D flip-flop 51. The clock terminal of the D flip-flop 51 is connected to the clock signal input terminal 43 via an inverter 52.

Further, the OR side input terminals of the 15 single AND-OR gates and the output signal line 53 of the NOR gate 48 are connected to a PLA (programmable logic) for creating the second preset data of the cylinder phase system counter 11. Further, the output signal line 53 is connected to the input terminal of an inverter 54, and the output terminal of the inverter 54 is connected to the other AND input of the 15 single AND-OR gates. The terminals are connected so that the data input terminal _D16 of the most significant bit of the cylinder phase system counter 11 is always supplied with a logic level "0".

It is assumed that the portions marked with circles in the mesh of the PLA are connected, and the other portions are not connected and a logic level "0" is always applied.

Next, FIG. 4 is a signal waveform diagram for explaining the operation of the count block shown in FIG. 3. FIG. is the signal waveform supplied to the signal input terminal 44, and c is the signal waveform supplied to the signal input terminal 44;
d is the output signal waveform of the NOR gate 48, e is the output signal waveform of the D flip-flop 49, and f is the output signal waveform of the D flip-flop 49.

Briefly explaining the operation of the count block shown in FIG. 3 based on the signal wave diagram shown in FIG. ₄ , when the decoder 14 shown in FIG. The level shifts from "0" to "1", and accordingly, the output state of the RS flip-flop constituted by the NOR gate 47 and the NOR gate 48 is inverted, and the output logic level of the NOR gate 48 becomes "0". As a result, EX-OR gate 50
The output logic level of also shifts to "1".

When the trailing edge of the clock signal arrives at time _t2 , the D flip-flop 51 is triggered and its output logic level shifts to "1", which causes the cylinder phase system counter 11 to respond to the preamp supplied from the data bus 39. Since it is preset based on the set data, the output logic level of the decoder 14 returns to "0".

When the leading edge of the clock signal arrives at time _t3 , the D flip-flop 49 is triggered and its output logic level goes to "0", and as a result, the output logic level of the EX-OR gate 50 also goes to "0". Transition.

Furthermore, when the trailing edge of the clock signal arrives at time _t4 , the D flip-flop 51 is triggered and its output logic level transitions to "0", and this state remains until the NOR gate 46 generates an output. .

The cylinder phase system counter 11 counts down from the first preset value until time _t11 .
When the output becomes [00...000], the output logic level of the NOR gate 46 shifts to "1", thereby inverting the output state of the RS flip-flop, and the output logic level of the NOR gate 46 shifts to "1".
The output logic level of the EX-OR gate 50 shifts to "1", and as a result, the output logic level of the EX-OR gate 50 also shifts to "1".

At time _t12 , when the trailing edge of the clock signal arrives, the D flip-flop 5
1 is triggered and its output logic level transitions to "1", resulting in a second preset signal being supplied to the cylinder phase system counter 11, this time on the output signal line 53 of the NOR gate 48. Presetting is performed using the data from the formed PLA, and the output logic level of the NOR gate 46 returns to "0" again.

At time _t13 , when the leading edge of the clock signal arrives, the D flip-flop 4
9 is triggered and its output logic level shifts to "1", and then the output logic level of the EX-OR gate 50 also returns to "0", and at time _t14 ,
When the trailing edge of the clock signal arrives, the D flip-flop 51 is triggered and its output logic level returns to "0".

At time _t21 , when the output of the cylinder phase system counter 11 becomes [00...000], the
The output logic level of the NOR gate 46 shifts to "1", but since the output logic level of the NOR gate 47 has already shifted to "0", the output state of the RS flip-flop does not invert, and therefore the D Presetting to the cylinder phase system counter 11 by the flip-flop 51 is not performed at this point, and the output of the cylinder phase system counter 11 becomes [11...111] at time _t22 .
At the time when the output voltage changes to "0", the output logic level of the NOR gate 46 returns to "0".

Note that since the decoder 14 does not generate an output until the most significant bit of the cylinder phase system counter 11 becomes "1", its output logic level becomes "1" between time _t1 and time _t21 . Never.

Now, at time _t31 , when the output of the cylinder phase system counter 11 reaches a preset count value, the decoder 14 generates an output, and thereafter repeats the same operation as after time _t1 in FIG. .

In this way, when the cylinder phase system count block 40 shown in FIG. After counting down by a number of clocks equal to the value, a second preset is performed based on data from the PLA.

Regarding the cylinder speed system count block 41 and the capstan speed system count block 42 shown in FIG. 2, the number of bits of each counter is 12 and 10, respectively, which is different from the cylinder phase system, but their basic configuration is shown in FIG. Since this is the same as the cylinder phase system count block in , a detailed explanation will be omitted.

Now, we will explain the outline of the operation when the VTR is in the playback state in the system shown in Figure 2.For convenience of explanation, we will use specific numerical values. It is assumed that the frequency of the subcarrier signal is the same as 3579.545 kHz, and a signal of 894.886 kHz, which is divided into quarters by the frequency divider 10, is supplied as a clock signal to the cylinder phase system count block 40,
The 223.722kHz signal divided by 1/16 is used as a clock signal for the cylinder speed system count block 41.
It is assumed that the

The ratio between the count period of the cylinder phase system counter and the count period of the cylinder speed system counter during steady rotation is determined by the cylinder FG signal and the cylinder PG signal.
It is equal to the frequency ratio of the signals, which is 6 in the system configuration shown in Figure 2, and since the frequency ratio of both clock signals is 4, the count amount per count period of the cylinder phase system counter and cylinder speed system counter is 24 times. There will be a difference.

Here, the maximum preset value of the cylinder phase system counter is Npa, the minimum preset value is Npb, the count value at the time when the decoder 14 generates an output signal is Nf, the maximum preset value of the cylinder speed system counter is Nsa, and the minimum preset value is Npb. If the value is Nsb, both the cylinder phase counter and cylinder speed counter start counting down from the preset value, and during steady rotation, the cylinder phase counter passes [00...000] and reaches Nf. Considering that the cylinder speed system counter is preset by itself when the leading edge of the cylinder FG signal arrives near [00...000], the following equation holds true.

(Npa+2 ¹⁶ −Nf)/(Npb+2 ¹⁶ −Nf) = Nsa/Nsb (1) Here, ΔNp=Npa−Npb (2) ΔNs=Nsa−Nsb (3) Then, equations (1) to (3) The following equation is immediately obtained.

ΔNs/ΔNp = Nsb/(Npb+2 ¹⁶ −Nf) (4) By the way, the right side of equation (4) is equal to the ratio 24 of the count amount per count period of the cylinder phase system counter and cylinder speed system counter, so the following equation holds true. do.

ΔNs=ΔNp/2 ⁴・1.5 (5) Based on the above calculation results, the first preset data ΔNs for the cylinder speed system counter is 4 bits to the right of the preset data ΔNp for the cylinder phase system counter. The second preset data can be obtained by shifting and further dividing by 1.5, and the second preset data is the PLA of each count block.
It can be seen that it is sufficient to supply Npb or Nsb.

In addition, in the example explained here, the ratio of the frequency of the cylinder FG signal and the frequency of the cylinder PG signal is 6.
Therefore, in the cylinder speed system count block, it is necessary to divide the preset data supplied from the data bus 39 by 1.5 after the 4-bit right shift, but this is the second time after the first preset. The period until the presetting is performed can be easily realized by configuring the clock signal to be alternately supplied to the first and second bits of the cylinder speed counter.

FIG. 5 shows a specific circuit configuration diagram of a cylinder speed system count block configured for such a purpose, and while the output logic level of the NOR gate 48 is "0", that is, From time _t1 to time _t11 in FIG. 4, a clock signal is alternately supplied to the first and second bits of the cylinder speed counter 12 in accordance with the output logic level of the T flip-flop 55. From the time when the output of the cylinder speed system counter becomes [00...001] or after the output logic level of the NOR gate 48 becomes "1", a clock signal is supplied only to the 1st bit.

Now, during VTR playback, the capstan motor 23 rotates in synchronization with the cylinder motor 1, so the capstan speed system count block 42 is also transferred from the memory 38 via the data bus 39, as shown in FIG. Preset data can be supplied to the cylinder speed system, but since the concept is the same as that of the cylinder speed system count block 41 already explained, the explanation will be omitted.

As described above, in the servo device of the present invention, the cylinder phase system counter 11, the cylinder speed system counter 12, and the capstan speed system included in the cylinder phase system count block 40, the cylinder speed system count block 41, or the capstan speed system count block 42 are One count period of the system counter 28 (although not shown in the embodiment of FIG. 2, the capstan speed system counter 28 is included inside the capstan speed system counter block 42) is a first counting mode represented by time t ₁ to time t ₁₁ in the figure;
divided into a second counting mode represented by time t ₁₁ to time t ₃₁ in FIG. In the second counting mode, the NOR gates 46, 47, 48, D flip-flops 49, 51, and EX-OR gates shown in FIG. 50,
A count mode switching circuit constituted by the inverter 52 operates.

Therefore, it is only possible to supply preset data from the only memory 38 prepared for the cylinder phase system count block 40 to the cylinder speed system count block 41 and the capstan speed system count block 42 via the data bus 39. Moreover, the bit size of the memory 38 itself is also different from that of the cylinder phase system ROM 1 in the conventional example.
3 (in the embodiment shown in FIG. 2, it is smaller by 1 bit, but the difference between the maximum preset value and the minimum preset value of the cylinder phase system counter 11 is 1/4 of the total count amount). (If it is less than 1/8, it can be reduced by 2 bits, and if it is less than 1/8, it can be reduced by 3 bits.) Therefore, compared to conventional devices, the proportion of memory (ROM) in the entire system is reduced. This not only reduces the number of elements that make up the system and reduces overall power consumption, but also significantly reduces the time it takes to inspect ROM data.

Effects of the Invention As is clear from the above description, the servo device of the present invention has an M-bit phase error detection counter ( In the embodiment, a 16-bit cylinder phase system counter 11)
, an N-bit speed error detection counter (in the embodiment, a 12-bit cylinder speed system counter 12) that measures the repetition period of the rotational speed signal of the rotating body, and an output of the phase error detection counter and the speed error detection counter. Control means (in the embodiment, latches 15 and 18, DA converters 17 and 20, synthesis circuit 21, Furthermore, the cylinder motor drive circuit 22 constitutes a control means. A memory means (a 15-bit memory 38 in the embodiment) supplies the detection counter, and one count period of the phase error detection counter is divided into a first count mode and a second count mode, and the first count In the second counting mode, the phase error detection counter is caused to perform a counting operation based on preset data from the memory means, and in the second counting mode, the phase error detection counter is caused to perform a counting operation based on unique preset data prepared separately. Since the counting mode switching means for causing the counter to perform a counting operation is provided, the bit size of the memory 38 can be made smaller than before.Furthermore, in the embodiment, in order to further enhance the effects of the present invention, the memory means Preset data of a plurality of Z bits (Z<N) for switching the rotational speed of the rotating body is also supplied to the speed error detection counter, and one count period of the speed error detection counter is set as a first count. In the first counting mode, the speed error detection counter is caused to perform a counting operation based on preset data from the memory means, and in the second counting mode, A second count mode switching means (a counter included in the cylinder speed system count block 41 or the capstan speed system count block 42) causes the speed error detection counter to perform a counting operation based on fixed preset data prepared separately. Since it is equipped with a mode switching circuit (mode switching circuit), the necessary preset data can be supplied to each counter from a single memory means, which has a great effect on streamlining the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional servo device, FIG. 2 is a block diagram of a servo device according to an embodiment of the present invention, FIG. 3 is a circuit configuration diagram of the main parts, and FIG. 4 is a signal waveform diagram thereof. FIG. 5 is a circuit configuration diagram of the main part. 11...Cylinder phase system counter, 12...Cylinder speed system counter, 38...Memory.

Claims (1)

[Scope of Claims] 1. An M-bit phase error detection counter that measures the phase difference between the rotational phase signal of the rotating body and a reference phase signal, and a speed error detection counter that measures the repetition period of the rotational speed signal of the rotating body. a control means for synthesizing the output of the phase error detection counter and the output of the speed error detection counter to generate an error output signal and controlling the rotational speed and rotational phase of the rotating body to be constant; memory means for supplying preset data of a plurality of Y bits (Y<M) for speed switching to the phase error detection counter; In the first counting mode, the phase error detection counter is caused to perform a counting operation based on preset data from the memory means, and in the second counting mode, the counting mode is divided into two counting modes. A servo device comprising count mode switching means for causing the phase error detection counter to perform a counting operation based on unique preset data. 2. An M-bit phase error detection counter that measures the phase difference between the rotational phase signal of the rotating body and the reference phase signal; an N-bit speed error detection counter that measures the repetition period of the rotational speed signal of the rotating body; a control means for synthesizing the output of the phase error detection counter and the output of the speed error detection counter to generate an error output signal, and controlling the rotational speed and rotational phase of the rotating body to be constant; and switching the rotational speed of the rotating body. memory means for supplying a plurality of Y-bit (Y<M) preset data to the phase error detection counter and a plurality of Z-bit (Z<N) preset data to the speed error detection counter; and one count period of the phase error detection counter and the speed error detection counter is divided into a first count mode and a second count mode, respectively, and in the first count mode, each preset from the memory means is divided into a first count mode and a second count mode. The phase error detection counter and the speed error detection counter are caused to perform a counting operation based on the data, and in the second counting mode, the phase error detection counter and the speed error detection counter are caused to perform a counting operation based on unique preset data prepared separately. A servo device comprising count mode switching means for causing an error detection counter to perform a counting operation.