JPH05100853A - Data processor with debug support function - Google Patents

Abstract

PURPOSE:To make correspondence between an instruction and operand access clear at the time of debug work to facilitate program debugging by outputting the identifier of an instruction corresponding to data access when mode designation is effective. CONSTITUTION:An instruction decoding (D) stage 4 including a decoder 5 executing the instruction received from an instruction fetch(IF) stage 2 generates an instruction code and an address calculation information code, calculates and outputs the program counter (PC) values of the respective instructions. The general-purpose register group 9 of 32 bits, a control register group 10b and a computing element 11 are contained in an instruction execution (E) stage 8, and an instruction execution result is written into an operand. When the bit is set, the PC value of the instruction corresponding to operand access is outputted after an operand access cycle. Thus, correspondence between the instruction and operand access can be made clear.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a debug support function and performing pipeline processing.

[0002]

2. Description of the Related Art Normally, execution of each instruction is completed through several cycles of sequential operations such as instruction reading, instruction decoding, operand address calculation, operand data reading, operation execution, and result storage. In order to achieve high-speed processing, some data processing devices have been divided into these operations and performed in a streamlined manner.
There is a pipeline processing mechanism in which execution of a plurality of instructions is performed simultaneously at the same time, and ideally, the execution result of one instruction is obtained for each cycle (execution time of one sequential operation).

Some data processing apparatuses have a debugging function to improve program development efficiency.

FIG. 5 shows functional blocks of an example of a conventional data processing device. 2 in the CPU 1a is an instruction fetch stage for fetching an instruction and inputs it to the instruction queue 3 (hereinafter referred to as an IF stage), and 4 is an instruction decode stage including a decoder 5 for decoding an instruction received from the IF stage (hereinafter, referred to as an IF decode stage). D stage)
Then, the instruction code and the address calculation information code are generated, and the program counter (hereinafter referred to as PC) value of each instruction is calculated and output. 6 is an operand address calculation stage (hereinafter, referred to as A stage) that performs operand address calculation by the address calculation information code generated in the D stage and fetches an effective address, and 7 is data required for instruction execution Operand fetch stage (hereinafter referred to as F stage) that fetches from the effective address of the operand calculated in the stage,
Reference numeral 8 denotes an instruction execution stage (hereinafter referred to as E stage) for executing a designated instruction, in which a 32-bit general-purpose register group 9, a control register group 10a, and an arithmetic unit 11 are provided.
Etc. are included, and the instruction execution result is written to the operand. Reference numeral 12 is a bus interface unit for controlling communication with an external memory, which is an external memory 1 generated from the IF stage 2.
3, an instruction fetch request to A3, a read request for data required for effective address calculation to the external memory 13 from the A stage 6, an operand data read request to the external memory 13 from the F stage 7, and an external memory 13 from the E stage 8. Arbitrates operand access (read or write) requests.

Reference numeral 23 is a clock signal (hereinafter referred to as CLK), 24 is a bus start signal (hereinafter referred to as BS) which is valid at "L" and indicates the start of a bus cycle, and 22 designates an address of the external memory 13. An address bus (hereinafter referred to as AD), 21 is a data bus (hereinafter referred to as D) for transferring data between the external memory 13 and the CPU 1a, 2
Reference numeral 5 indicates “H” for reading, “L” for writing, and a read / write signal (hereinafter R / W) indicating the direction of data transfer.
, 26 is a data transfer complete signal (hereinafter D), which is valid at “L” and indicates the completion of data transfer.
C).

FIG. 6 shows a control register 10a of FIG.
A detailed description of the debug environment control register (hereinafter referred to as the DBC register) that controls the debug environment.
The A bit 31 indicates whether a debug event is detected in the trace mode, the EA bit 32 detects whether a debug event is detected by executing an instruction, the RA bit 33 indicates whether a debug event is detected by reading from an operand, WA Bit 34 indicates whether a debug event was detected by writing to the operand.

Instructions A, B, and C are stored at addresses 0 to 2 of the external memory 13, respectively, and the instruction processing at each stage when these instructions are sequentially read by the CPU 1a and pipelined. 7 and the bus operation in each cycle will be described with reference to FIG.

The bus cycle starts when the CPU 1a asserts BS24, and the external memory 13 causes the DC cycle.
When 26 is input, the process ends. AD22 and R / W25 are also output at the same time when BS is asserted. First of FIG.
In the cycle, the CPU 1a asserts BS24, outputs the transfer direction R / W = "H", issues an address signal designating address 0 of the external memory 13 from AD22, reads the instruction A at address 0 through D21, and outputs IF Store in instruction queue 3 of stage 2. The bus cycle ends with the input of DC26. In the second cycle, the CPU 1a
Assert S24, the instruction A is sent to the D stage 4, and is decoded by the decoder 5. Command A PC
The value is calculated. In the second cycle, at the same time when BS24 is asserted, the CPU 1a outputs the transfer direction R / W = "H", outputs an address signal designating the first address of the external memory 13 from the AD22, and outputs the instruction B from the first address through the D21.
Store in the instruction queue 3 of the F stage 2. In the third cycle, the fetching of the instruction C in the IF stage 2, the decoding of the instruction B in the D stage 4, the address calculation of the operand of the instruction A in the A stage 6, and the three processes are simultaneously performed. In this way, basically, an instruction flows through each stage and is processed every cycle.

However, in the fifth cycle, two memory access requests, a write request for the instruction A to the external memory 13 in the E stage 8 and an operand read request for the instruction B from the external memory 13 in the F stage 7, are simultaneously performed. Since this occurs, arbitration is performed in the bus interface unit 12, where the writing of the instruction A to the memory in the E stage 8 is given priority, and the processing of the instruction B in the F stage 7 is delayed until this processing ends. The write operation to the external memory 13 in the fifth cycle starts by asserting BS24, then outputs R / W = "L", and outputs the address from the AD22. After that, the data is output from D21, and the bus cycle is ended by the input of DC26.

In the sixth cycle, since the operand of the instruction B is read from the external memory 13 in the F stage 7, the processing of the instruction C is delayed while waiting for the F stage 7 to be vacant in the A stage 6. It As described above, even while the processing of the previous instruction is being performed in the next stage, the processing is delayed until the processing is completed.

As described above, in the conventional data processing device for pipeline processing, there is a time lag between the fetching of an instruction and the complete processing, and a plurality of instructions are processed at the same time. Although it is possible to determine whether or not a debug event has occurred by referring to the control register, when an operand access is performed, it is not possible to instantaneously obtain information such as which instruction performed the access. could not.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and an object thereof is to clarify the correspondence between instruction and operand access at the time of debugging work to facilitate program debugging.

[0013]

In a data processing device according to the present invention, for example, in a register or the like for controlling a debug environment, a bit (a mode designating means of a mode designating means) for designating a mode for clarifying a correspondence between an instruction and an operand access is provided. One example), and an instruction identifying means for outputting a PC value (an example of an identifier) of an instruction corresponding to operand access.

[0014]

According to the present invention, when the above-mentioned bit (mode designating means) in the register for controlling the debug environment is set, the instruction identifying means can access the operand access during or before or after the operand access bus cycle. The PC value of the corresponding instruction is output.

[0015]

【Example】

Example 1. As one embodiment of the present invention, a register for controlling a debug environment is provided and a PC value of a corresponding instruction is output after a bus cycle of an operand access in order to clarify the correspondence between the instruction and the operand in the register. A pipeline data processing device having a bit that specifies whether or not to do so will be described with reference to FIGS.

FIG. 1 shows a functional block of an example of a data processing device of the present invention. 2 in the CPU 1b is an instruction fetch stage (hereinafter referred to as an IF stage) that fetches an instruction and inputs it to the instruction queue 3. 4 is a decoder 5 that decodes the instruction received from the IF stage.
In the instruction decoding stage (hereinafter referred to as D stage) including, the instruction code and the address calculation information code are generated, and the program counter (hereinafter referred to as PC) value of each instruction is calculated and output. 6 is an operand address calculation stage (hereinafter referred to as A stage) that performs operand address calculation by the address calculation information code generated in the D stage and fetches an effective address, and 7 is the data necessary for instruction execution Fetch from the effective address of the operand calculated in the stage,
An operand fetch stage (hereinafter referred to as F stage) 8 is an instruction execution stage (hereinafter referred to as E stage) that executes a designated instruction, and includes a 32-bit general-purpose register group 9 and a control register group 10b. The arithmetic unit 11 and the like are included, and the instruction execution result is written in the operand. Reference numeral 12 denotes a bus interface unit for controlling communication with an external memory, which includes an instruction fetch request from the IF stage 2 to the external memory 13 and a data read request from the A stage 6 to read external data required for effective address calculation. Operand data read request to external memory 13 from stage 7, E
It arbitrates an operand access (read or write) request to the external memory 13 that occurs from the stage 8.

Reference numeral 23 is a clock signal (hereinafter referred to as CLK), 24 is a bus start signal (hereinafter referred to as BS) indicating the start of a bus cycle, and 22 is an address bus (hereinafter referred to as AD) for designating an address of the external memory 13. , 21 is a data bus (hereinafter referred to as D) for transferring data between the external memory 13 and the CPU 1b, 25 is a read / write signal (hereinafter referred to as R / W) indicating the direction of data transfer, 26
Is a data transfer complete signal (hereinafter referred to as DC) indicating the completion of data transfer.

FIG. 2 shows the control register 10b of FIG.
It is a detailed representation of a debug environment control register (hereinafter referred to as a DBC register) for controlling the debug environment of the data processor of the present invention. Whether or not the PC value of the corresponding instruction is output after the operand access by the A bit 35. Is specified, the SA bit 31 indicates whether a debug event is detected in the trace mode, the EA bit 32 indicates whether a debug event is detected by instruction execution, and the RA bit 33 detects a debug event by reading from the operand. The WA bit 34 indicates whether or not a debug event is detected by writing to the operand.

Instructions A, B, and C are stored at addresses 0 to 2 of the external memory 13, respectively, and instruction processing at each stage when these instructions are sequentially read by the CPU 1b and pipelined. And the bus operation in each cycle will be described with reference to FIG.

The bus cycle is started by the CPU 1b asserting BS24, and the external memory 13 causes the DC cycle.
When 26 is input, the process ends. AD22 and R / W25 are also output at the same time when BS is asserted. First of FIG.
In the cycle, the CPU 1b asserts BS24, outputs the transfer direction R / W = "H", issues an address signal designating address 0 of the external memory 13 from AD22, reads the instruction A at address 0 through D21, and outputs IF Store in instruction queue 3 of stage 2. The bus cycle ends with the input of DC26. In the second cycle, CPU 1b
Assert S24, the instruction A is sent to the D stage 4, and is decoded by the decoder 5. Command A PC
The value is calculated. In the second cycle, at the same time when BS24 is asserted, the CPU 1b outputs the transfer direction R / W = “H”, issues an address signal designating the first address of the external memory 13 from the AD22, and outputs the instruction B from the first address through the D21.
Store in the instruction queue 3 of the F stage 2. In the third cycle, the fetching of the instruction C in the IF stage 2, the decoding of the instruction B in the D stage 4, the address calculation of the operand of the instruction A in the A stage 6, and the three processes are simultaneously performed. In this way, when there is no operand access, an instruction basically flows through each stage and is processed every cycle, as in the conventional data processing device.

In the fourth cycle, operand access is performed to fetch the operand of instruction A.
In such a case, in the cycle immediately after the operand access, that is, in the fifth cycle, the PC value 0 of the instruction A that caused the operand access is output to the signal line AD22. At this time, since R / W25 remains H and BS24 is not asserted, the address of the instruction A is only output to the signal line AD22 in the fifth cycle, and the memory 13 is not accessed for reading or writing. .. As described above, the address of the instruction A output to the signal line AD22 is detected by the debug means (not shown). The sixth cycle is the write cycle of the instruction A, and the PC value 0 of the instruction A is AD in the seventh cycle after the write is completed.
22 is output. At this time, R / W25 remains L and B
S24 is not asserted. The eighth cycle is the operand prefetch cycle of the instruction B, and the PC value of the instruction B is 1 in the ninth cycle after the operand prefetch.
Is output to AD22.

Example 2. In the first embodiment, a bit for clarifying the correspondence between the operand access and the instruction is provided in the debug control register, and when the above bit is set, the PC value is output after the operand access cycle. However, even if the PC value of the corresponding instruction is output during the operand access cycle,
The same effect can be obtained. The state of the bus operation in each cycle when the instructions A, B, and C are sequentially read into the data processing device and pipeline processing will be described with reference to FIG.

The bus cycle is started by the CPU 1b asserting BS24, and the external memory 13 causes the DC cycle.
When 26 is input, the process ends. AD22 and R / W25 are also output at the same time when BS is asserted. First of FIG.
In the cycle, the CPU 1b asserts BS24, outputs the transfer direction R / W = "H", issues an address signal designating address 0 of the external memory 13 from AD22, reads the instruction A at address 0 through D21, and outputs IF Store in instruction queue 3 of stage 2. The bus cycle ends with the input of DC26. In the second cycle, CPU 1b
Assert S24, the instruction A is sent to the D stage 4, and is decoded by the decoder 5. Command A PC
The value is calculated. In the second cycle, at the same time when BS24 is asserted, the CPU 1b outputs the transfer direction R / W = “H”, issues an address signal designating the first address of the external memory 13 from the AD22, and outputs the instruction B from the first address through the D21.
Store in the instruction queue 3 of the F stage 2. In the third cycle, the fetching of the instruction C in the IF stage 2, the decoding of the instruction B in the D stage 4, the address calculation of the operand of the instruction A in the A stage 6, and the three processes are simultaneously performed. In this way, when there is no operand access, basically every cycle, like the conventional data processing device,
Instructions flow through each stage and are processed.

In the fourth cycle, an operand access request is issued to fetch the operand of instruction A. In the fourth cycle, the CPU 1b asserts BS24, outputs R / W = "H" at the same time to instruct to read the data from the external memory 13, and in the first half of the cycle, the PC of the instruction A that caused the operand access is issued. The value 0 is output to AD22. In the latter half of the cycle, an address signal designating the operand of the instruction A in the external memory 13 is issued from the AD 22 and the data is read through the D 21. The bus cycle ends with the input of DC26. The fifth cycle is a write cycle of the instruction A, and the CPU 1b asserts BS24, outputs R / W = "L" at the same time to instruct to write the data in the external memory 13, and causes an operand access in the first half of the cycle. The PC value 0 of the instruction A is output to the AD 22. In the latter half of the cycle, an address signal designating the operand of the instruction A in the external memory 13 is issued from the AD 22 and the data is written through the D 21. The bus cycle ends with the input of DC26. The sixth cycle is the instruction B operand prefetch cycle, which is the CPU
1b asserts BS24, outputs R / W = "H" at the same time to instruct to read data from the external memory 13, and transfers the PC value 1 of the instruction B that caused the operand access to the AD22 in the first half of the cycle. Output. In the latter half of the cycle, the address signal designating the operand of the instruction B of the external memory 13 is issued from the AD 22 and the data is read through the D 21. The bus cycle ends with the input of DC26. The seventh cycle is the write cycle of instruction A, and CP
U1b asserts BS24 and at the same time R / W = "L"
Is output to instruct to write the data in the external memory 13, and the PC value 1 of the instruction B that caused the operand access in the first half of the cycle is output to the AD 22. In the latter half of the cycle, an address signal designating the operand of the instruction B in the external memory 13 is issued from the AD 22 and the data is written through the D 21. The bus cycle ends with the input of DC26.

Example 3. In the first embodiment, the debug control register has a bit for clarifying the correspondence between the operand access and the instruction, and when this bit is set, the PC value is output after the operand access cycle. However, the same effect can be obtained by outputting the PC value before the operand access cycle.

Example 4. In the above embodiment, one bit for clarifying the correspondence between the operand access and the instruction in the debug control register has been described as an example of the mode designating means, but this bit does not have to be 1 bit,
There may be multiple bits. For example, with 2 bits,
The modes may be divided as follows. 00 = No debug support function 01 = Debug support function execution described in the first embodiment 10 = Debug support function execution described in the second embodiment 11 = Debug support function execution described in the third embodiment

Example 5. Further, the mode designating means is not limited to using the bits in the debug control register, and other dedicated registers inside or outside the processor or the CPU or a storage area such as a flip-flop may be used. Further, the mode setting to the bit and the storage area may be performed by any method such as by programmed software or by hardware such as a DIP switch.

Example 6. In the above embodiment, operand access is taken as an example, but data other than operands may be accessed. In the above embodiment, the case where the PC value of the corresponding instruction is output has been described.
It does not matter even if the instruction identifier other than the C value is output. For example, the relative address of the instruction or the code itself may be output as the identifier.

[0029]

As described above, according to the present invention, it is possible to clarify the correspondence between the instruction and the operand access in the data processing device for performing the pipeline processing, and thus it is possible to facilitate the program debugging. ..

[Brief description of drawings]

FIG. 1 is a functional block diagram of an example of a data processing device of the present invention.

FIG. 2 is a diagram showing registers that control a debug environment of an example of a data processing device of the present invention.

FIG. 3 shows an example of a data processing device according to the present invention, which has an instruction A,
FIG. 6 is a diagram showing a flow of instruction processing in each stage in each cycle and a bus operation state of each signal in the first embodiment when B and C are sequentially read and pipeline-processed in each stage. ..

FIG. 4 shows an example of a data processing apparatus according to the present invention, which has an instruction A,
FIG. 9 is a diagram showing a flow of instruction processing in each stage in each cycle and a bus operation state of each signal in the second embodiment when B and C are sequentially read and subjected to pipeline processing in each stage. ..

FIG. 5 is a functional block diagram of a conventional data processing device.

FIG. 6 is a diagram showing registers that control a debug environment of a conventional data processing device.

FIG. 7 is a diagram showing a state where pipeline processing is performed in each stage when instructions A, B, and C are read in a conventional data processing device.

[Explanation of symbols]

 1b CPU of the present invention 2 instruction fetch stage 3 instruction queue 4 decode stage 5 decoder 6 operand address calculation stage 7 operand fetch stage 8 instruction execution stage 9 general-purpose register group 10b control register group 11 arithmetic unit 12 bus interface unit 13 external Memory 21 Data bus 22 Address bus 23 Clock signal 24 Bus start signal 25 Read / write signal 26 Data transfer complete signal 31 SA bit 32 EA bit 33 RA bit 34 WA bit 35 A bit

Claims (1)

[Claims] 1. Debugging comprising mode designating means for designating whether correspondence between an instruction and data access is explicitly indicated, and instruction identifying means for outputting an identifier of an instruction corresponding to data access when the mode designation is valid. Data processing device with support function.