JPH0498873A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable an element to be enhanced in capacitance without increasing it in area by a method wherein a first conductive layer is formed on a semiconductor base, a second conductive layer is formed on the first conductive layer, and the semiconductor base and the second conductive layer are connected together. CONSTITUTION:The prescribed point of a P-type well 2 is etched deep to form a trench groove 3. The etching concerned is carried through a dry etching method large in anisotropy. Then, a field SiO2 film 10 is selectively formed through a LOCOS method. A state where a nitride film used as a mask has been removed is shown in a figure. In succession, a transfer gate region is covered with a photoresist 31, and N-type impurity ions 32 are implanted into the exposed surface of silicon including the groove 3. Then, a photoresist 31 is removed, and a thin SiO film 4 is made to grow as thick as 580Angstrom through a thermal oxidation method. Concurrently, the implanted ions 32 are diffused throughout the silicon concerned to form an N<+>-type diffusion region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is applicable to semiconductor devices, such as dynamic RAM [R
andos Access Memory).

Conventional technology Conventionally, semiconductor integrated circuit devices, such as dynamic RAM
A memory cell having the structure shown in FIG. 7 is known.

That is, a trench-like groove 3 of a predetermined depth is provided in the P-type well 2, and a pear-shaped polycone layer 8 is deposited on the groove 3 with an insulating film 4 interposed therebetween. Note that below well 2 there is a
Although there is a - type silicon substrate, it is not shown. A capacitor is formed on the entire surface of the outer side of the groove 3 (the side in contact with the well 2) using the diffused N-type diffusion region 5 as one electrode. Also, on the side of groove 3 (right side in the figure)
An N° type source region 6 and an N° type drain region 7 are diffused in a predetermined pattern on the surface of the P type well 2, and a word line is formed between them with a gate oxide film 14 interposed therebetween. A gate electrode 9 of polysilicon is provided,
A horizontal N-channel MOS transistor (transfer gate) 30 is configured. The source region 6 of this transistor is connected to the above-mentioned diffusion region 5. In addition,
In the symbols shown in the figure, 10 is a field oxide film, 11
and 15 is a Sin layer, 12 is a contact hole, 13
is an aluminum wiring (bit line).

This device uses a trench groove 3 to form a capacitor between a diffusion region 5 and a polysilicon layer 8 on its wall surface, and has a structure in which charge is accumulated. It can be made larger than a planar shape, and the cell area can also be made smaller.

Further, a device having the structure shown in FIG. 8 is also known.

In this device as well, in the trench groove 3, the surface oxide film 15 of the first polysilicon layer 8 is filled with a second polysilicon layer 16 connected to the source region 6, and both polysilicon layers 8- Since a capacitor is formed between 16 and 16, the capacitance can be made relatively large as in FIG. Note that 17 in the figure is a SiO□ film.

However, both the devices shown in FIGS. 7 and 8 are still insufficient as memory cells in terms of large capacity and reliability. Dynamic RAM increases the capacity of memory cells.
By increasing the discharge time and the refresh cycle, the memory retention time can be increased and the reliability of the memory can be increased accordingly. However, in the case of the above-mentioned memory cell, for example, a capacitance of about 40 fF is possible for 1 megabit, but it is impossible to form a larger capacitance within a limited area.

OBJECTS OF THE INVENTION An object of the present invention is to provide a high-capacity, high-convertibility semiconductor device in which the capacitance can be increased without increasing the area of the element portion.

26 Structure of the Invention That is, in the present invention, a first conductive layer is formed on a semiconductor substrate with an insulating film interposed therebetween, and a second conductive layer is formed on the first conductive layer with an insulating film interposed therebetween. The present invention relates to a semiconductor device configured such that a plurality of capacitors are connected in parallel between the semiconductor base and the first conductive layer by connecting the semiconductor base and the second conductive layer. .

E, Example The present invention will be explained in detail below.

1 to 4 show a first embodiment of the present invention.

As shown in FIGS. 1 and 2, the memory cell of the dynamic RAM according to this example (for example, a 1 megafocus dynamic RAM) is formed by forming a P-type well 2 on a P-type silicon substrate 1 (not shown). A trench-like groove 3 having a predetermined depth is formed within this well 2 . A first N-type polysilicon layer 8 is deposited in this groove via a thin insulating film (silicon oxide film) 4, and is used as an electrode of a capacitor facing the N-type diffusion region 5. . This polysilicon layer 8 is connected at a predetermined location 34 to an earth line 22 (see FIG. 2) indicated by a phantom line. The N-type diffusion region (including the source region 6) 5 is formed by diffusion (formed by thermal diffusion) over a predetermined region on the outer peripheral surface of the groove 3, and is used as a storage electrode for storing charge of the capacitor. ing.

Then, a second polysilicon layer 20 is filled on the polysilicon layer 8 with a thin insulating film 15 interposed therebetween, and the first polysilicon layer 8 is sandwiched between it and the substrate. One end 20a of the polysilicon layer is ohmically connected to the above-described diffusion region 5. polysilicon layer 20
The surface of the film is a thin SiOz film 21, and the surface of the film is a thin SiOz film 21. hO:)
S i O2 film 11 T: Covered.

Since the other configurations are the same as those in FIG. 7, common parts are given common reference numerals and explanations are omitted.

As described above, the memory cell according to this embodiment has a first capacitor C1 formed of the diffusion region 5, the insulating film 3, and the polysilicon layer 8 between the source region 6 of the transfer gate 30 and the ground level. , the second capacitor Ct formed of the polysilicon layer 20, the insulating film 15, and the polysilicon layer 8 are connected in parallel as shown in FIG. Therefore, compared to the conventional examples shown in FIGS. 7 and 8, the structure has the following features.

(1), ) Not only is the capacitor CI formed over the entire wall surface of the wrench groove 3, but also the capacitor C2 is formed over an equivalent area, and both capacitors CI
and C2 are connected in parallel between the source region and the ground, so the overall capacitance becomes a composite capacitance of (c+ +C2), making it possible to nearly double the capacitance (larger capacitance).

As a result, since the capacitance per unit area of the cell can be increased, when the cell size is the same, the discharge time of the accumulated charges in the capacitor becomes longer, and the memory retention time can be lengthened to improve reliability.

(2), and when the capacitance is the same, the planar size of the capacitor part (furthermore, the depth of the trench)
can be made smaller, element design becomes easier, and layout area can be reduced.

(3), ) In addition to the already mentioned advantages of using wrench grooves, from the above, it is possible to create a larger capacity in a smaller cell area than in the conventional example, so -
It has a layer-friendly structure.

Next, an example of a method for manufacturing the above structure will be explained with reference to FIG.

First, as shown in FIG. 4A, a predetermined portion of the P-type well 2 is deeply etched to form a trench groove 3 to a depth of, for example, 32,000 mm.
Form into a person. This etching is a highly anisotropic dry etching (the etching gas is CB r F3 +NZ
).

Next, as shown in the 4th day diagram, the well-known LOGO3 (Loca
In the drawing in which the field SiOz film 10 is selectively formed by the oxidation of 5 silicon method, the nitride film used as a mask is shown removed.

Next, as shown in FIG. 4C, the transfer gate region is covered with a photoresist 31 and an N-type impurity (for example, As) is added.
ions 32 are implanted to implant N-type impurities 32 into the exposed silicon surface including the groove 3. The amount of ions implanted at this time is, for example, 5E15 ions/cj.

Next, after removing the photoresist 31, as shown in FIG.
i O! Grow film 4 to a thickness of 580 nm.

At the same time, the ions 32 implanted in FIG. 4C are diffused into the silicon to form an N-type diffusion region 5.

Next, as shown in FIG. 4E, after etching the 5iOz film 4 into a predetermined pattern to partially expose the silicon surface, a first polysilicon layer 8 is deposited over the entire surface by CVD (C
chemical vapor deposition
) deposited to a thickness of 2,500 people. At this time, by simultaneously supplying an impurity gas (for example, AsHs), the polysilicon layer 8 can be made into an N-type and have a low resistance.

Next, as shown in FIG. 4F, the polysilicon layer 8 is patterned to leave it in approximately the same shape as the SiO□ film 4. Then, as shown in FIG. This patterning is desirably carried out so that the polysilicon layer 8 remains at least in the same area as the SiO□ film 4 or in an area smaller than it.

In the former case, the polysilicon layer 8 can be deposited after the step shown in FIG. 40, and the polysilicon layer 8, the Sin layer, and the film 4 can be etched in sequence using a common etching mask.

After cleaning the silicon surface, as shown in FIG. 4G, the entire surface is thermally oxidized at 900° C. for 30 minutes to grow a gate oxide film 14 with a thickness of 190λ and an SiO□ film 15 with a thickness of 190 μm.

Next, as shown in FIG. 4H, a predetermined portion of the SiO□ film 15 is removed by etching to expose the diffusion region 5, the surface is cleaned, and a second polysilicon layer 20 is formed by CVD.
is deposited to a thickness of 4,200 people.

Next, as shown in FIG. 41, the polysilicon layer 20 is patterned by etching to selectively leave the polysilicon layer 20 from inside the groove 3 to a part of the diffusion region 5, and at the same time, a polysilicon gate 9 is formed. In addition, Sin, film 15
The part on the field SiO□ film 10 is made of the same Si.
n, shown included in the film 10 (the same applies to other figures).

Next, as shown in FIG. 4J, an ion beam 33 of N-type impurities (for example, As) is implanted in the transfer gate region (the implantation amount is 3.5E15/d).

At this time, ions 33 are selectively implanted into the self-alignment line in the silicon using the gate 9 as a mask, thereby obtaining the amount of impurity implanted into the source and drain regions. Further, by implanting N-type impurities into polysilicon layers 9 and 20, the resistance of both polysilicon layers is reduced.

Fourth, as shown in the figure, the surface is coated with a thin (for example, 1,000 thick) Sin by thermal oxidation at 430°C for 1 minute.

A film 21 is grown. At this time, the implanted ions 33 are thermally diffused to form the source region 6 (which is integrated with the diffusion region 5) and the drain region 7 of the transfer gate 30, respectively.

Then, as shown in FIG. 1, a 5ift film 11 is formed on the entire surface.
is deposited by CVD, patterned to open each contact hole 12 (furthermore 34), and then aluminum is deposited by a sputtering method and patterned to form each wiring 13 (furthermore 22) and the like.

The above-mentioned manufacturing method may be modified in various ways, and various methods such as etching methods and impurity implantation methods (solid phase diffusion is also possible) can be employed within the range of known techniques.

FIG. 5 shows a second embodiment of the invention.

In this example, unlike the example of the memory cell shown in FIG.
A film 4, a polysilicon layer 8.5iOz film 15, a polysilicon layer 20, and SiO□ films 21 and 11 are sequentially formed by a similar process. The second polysilicon layer 20 is connected to the diffusion region 5 at one end, so that a capacitor formed by the diffusion region, the insulating film 4 and the polysilicon layer 8 is formed between the substrate (or the diffusion region 5) and the ground. The polysilicon layer 20, the insulating film 15, and the capacitor formed by the polysilicon layer 8 are connected in parallel.

Therefore, in this example as well, a large capacitance capacitor can be constructed in a small area on a semiconductor substrate.

Then, by connecting the diffusion region 5 to other circuit elements through the wiring 13, the above-mentioned capacitor can be incorporated into a predetermined circuit. Note that this capacitor can also be connected to the source region of a transfer gate as shown in FIG.

The embodiments described above can be further modified based on the technical idea of the present invention.

For example, the above-mentioned polysilicon layers 8 and 20 may not only overlap as described above, but also partially overlap (however, it is desirable that the overlapping portion be two or more of the lower layers). Alternatively, the material may be a semiconductor or conductive material other than polysilicon. Furthermore, the formation method and material of the above-mentioned insulating films 4 and 15 may be changed. For example, the dielectric constant can be increased by forming not only a Sin film but also a laminated film with nitride or nitride oxide. I can do it.

In addition, in the above example, the conductive layers forming the capacitor were provided one layer each on the top and bottom (20 and 8), but more layers (for example, 4 layers) could be stacked to connect three or more types of capacitors in parallel. good.

An example is shown in FIG. 6, where the third and fourth polysilicon layers 40, 41
When the polysilicon layer 40 is connected to the polysilicon layer 20 and the polysilicon layer 8, respectively, a capacitor formed by the polysilicon layer 40, the insulating film 42, and the polysilicon layer 41 is formed as shown in FIG. Another one will be connected in parallel.

In addition, the shape, arrangement, etc. of the above-mentioned grooves can be modified, and various dry etching methods and the like can be employed for forming the grooves. The method of taking out the wiring part of the capacitor ground electrode is not limited to the above-mentioned method, but it can also be taken out after being buried in a groove, for example.

Further, the gate electrode is not made of polysilicon (or may be made of metal such as aluminum or silicide, which is a compound of metal and Si). Other layers and films can also be changed in various ways.

Note that the conductivity type of each semiconductor region described above may be reversed,
Of course, the shape, arrangement, structure, manufacturing method, etc. of each region can also be changed.

9. Effects of the Invention As described above, the present invention forms a semiconductor substrate by forming first and second conductive layers on a semiconductor substrate via an insulating film and connecting the second conductive layer to the semiconductor substrate. - Since a plurality of capacitors are connected in parallel between the first conductive layers, the capacitance per unit area can be increased, and the retention time of the accumulated charges in the capacitors can be extended, and reliability can be improved. Further, when the capacitances are made the same, the size of the capacitor portion can be reduced, which facilitates device design and reduces the layout area.

[Brief explanation of the drawing]

1 to 6 show embodiments of the present invention. FIG. 1 is a cross-sectional view of a memory cell of a dynamic RAM according to the first embodiment (I-1 in FIG. 2, which will be described later). ), Figure 2 is a plan view of the memory cell in Figure 1 (however, each insulating film is omitted), Figure 3 is an equivalent circuit diagram of the memory cell, Figure 4A , Figure 4B, Figure 4C, Figure 40, Figure 4E,
Figure 4F, Figure 4G, Figure 4H, Figure 41, Figure 4J,
4th figure is each cross-sectional view sequentially showing the main steps of the manufacturing method of the dynamic RAM of FIG. 1, and FIGS. 5 and 6 are respective sectional views of semiconductor devices according to other embodiments. FIGS. 7 and 8 are cross-sectional views of memory cells of two examples of conventional dynamic RAM. In the symbols shown in the drawings, 2...P-type well 3...Groove 4.15.21...Insulating film 5.・・・・・・
...N-type diffusion region 6...Source region 7...Drain region 8...Polysilicon layer (first layer) )9...
・・・・・・Polysilicon gate 20・・・・・・・
...Polysilicon layer (second layer). Agent Patent Attorney Hiroshi Osaka]

Claims (1)

[Claims] 1. A first conductive layer is formed on a semiconductor substrate via an insulating film, a second conductive layer is formed on the first conductive layer via an insulating film, and the semiconductor substrate and the second conductive layer are formed on the semiconductor substrate with an insulating film interposed therebetween. A semiconductor device configured such that a plurality of capacitors are connected in parallel between the semiconductor substrate and the first conductive layer by connecting the layers.