JPH0484354A - Data transferring system for synchronous circuit - Google Patents

Abstract

PURPOSE:To allow a synchronous circuit to operate with a high-frequency clock so as to improve the processing capacity of a pipeline processor by making smaller a skew which is a margin necessary for allowing the synchronous circuit to operate normally. CONSTITUTION:A sampling clock generating means 10 is constituted of a data variation detecting means 11 and phase controlling means 12 and when data inputted from a data input terminal 1 vary, the generating means 11 informs the controlling means 12 of the data variation. The controlling means 12 controls the phase of a reference clock by using a signal indicating the data variation from the generating means 11 as a reference signal and generates a sampling clock. When the sampling clock rises, the data are held by a data holding means 20. Therefore, the frequency of the clock is raised while increases in pipeline losses and hardware caused by skews are suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer system in a synchronous circuit that operates in synchronization with a clock.

(Prior Art) In a synchronous circuit, data is held in a register using a clock that controls the operation of the circuit. A logic circuit is provided between the registers to process the data held, and the data output from the register is processed by this logic circuit, and after 120 passes, the processed result is transferred to the next stage. The data is stored in the register. Here, it is assumed that the register holds input data at the rising edge of the clock. Since the circuit has a finite operating speed, in order to operate normally as a synchronous circuit, it is necessary to stabilize the input data before and after the rising edge of the clock. Setup time is a parameter that specifies how long the data needs to be stabilized before the clock rises, and the setup time is the parameter that specifies how long the data needs to be stabilized before the clock rises. The data hold time is a parameter that defines how long data needs to be kept stable. Third
The figure shows the relationship between clock rise, set-up time, and data hold time. As is clear from FIG. 3, the set-up time and data hold time are determined by the time relationship between the timing at which the input data fluctuates and the rising edge of the tarock. However, due to the physical size of the circuit, it is not possible to define constant set-up times and data hold times for all registers.

This is mainly due to variations in signal propagation delay time. Skew is defined as a margin that absorbs this variation. The synchronous circuit is designed to satisfy the following condition.

Maximum delay time Child set-up time + skew <Operating clock period...(1) Minimum delay time> Data hold time + Skew...(2) This skew is a margin for absorbing variations in signal propagation delay time. It is. In general, synchronous circuits are designed to equalize the propagation delay time, that is, to make the wiring lengths in the circuit the same, in order to reduce the skew, but essentially it is impossible to reduce the skew beyond a certain level. Can not. This is because the propagation delay is caused by external factors 21, for example.

This is because it has components that depend on temperature and other factors.

(Problem to be Solved by the Invention) The sum of the aforementioned setup time and data hold time can be reduced by using a device that operates at high speed. On the other hand, skew depends on the physical arrangement of registers and has a nearly constant value regardless of the clock, so if you increase the clock frequency to improve circuit performance, the relative skew will increase. can no longer be ignored. This means that when the tarokk frequency is low enough, that is, when the skew is negligible with respect to the clock period, the time that could be used almost entirely for propagation delay is gradually reduced by increasing the tarokk frequency. A problem arises in that the device becomes unusable and the operating efficiency is significantly reduced. Furthermore, in order to satisfy equation (2), it is necessary to delay the signal on the minimum delay path. For this purpose, a logic circuit is inserted just to delay the signal, but this leads to an increase in the amount of hardware. The problem of decreased operating efficiency of synchronous circuits is 1. This is noticeable in pipeline operating circuits. Here, assuming that the skew is sufficiently large relative to the sum of the set-up time and the data hold time, equation (1) can be simplified to equation (3). The logic circuit is designed to satisfy the condition of equation (3).

Open at maximum delay + skew clock cycle...(3) Pipeline parallel processing does not wait for one process to complete, but starts the next process, thereby reducing the time it takes for one process to complete. Although the time remains the same, this method increases processing power by executing multiple processes consecutively within one piece of hardware. In order to improve the performance of this pipeline parallel processing, it is possible to divide the processing into smaller sections and increase the number of internally executed processes in parallel, that is, to increase the degree of processing parallelism. For this purpose, it is necessary to increase the clock frequency. This is a way of dividing a certain amount of time into smaller pieces. However, by increasing the clock frequency, the skew can no longer be ignored, and when the clock frequency is low, the
When the number of pipeline stages is increased, the logic circuit that should have entered N8 cannot be accommodated.

This causes a problem in that the number of stages in the pipeline increases and the time from the start to the end of processing becomes longer. This problem is called pipeline loss because it is caused by making the pipeline smaller. The present invention is a data transfer method for suppressing the pipeline loss and increase in hardware due to this skew and increasing the clock frequency.

(Measures Pi for Solving the Problems) A data transfer method in a synchronous circuit of the present invention is a data transfer method in a synchronous circuit that operates in synchronization with a clock, and detects fluctuations in input data to means for outputting an instruction signal indicating the fluctuation; and means for controlling the phase of a reference clock with the instruction signal and applying a delay of a data hold time to the reference clock whose phase has been controlled and outputting the resultant as a sampling clock. , and means for sampling the input data using the sampling clock and holding the sampled data.

(effect) Next, the operation of the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the constituent elements of the present invention.

Reference numeral 10 denotes a sampling clock generating means, which is composed of a data fluctuation detecting means 11 and a phase controlling means 12. 2
0 is data holding means. Further, 1 is a data input terminal, and 2 is a reference tally clock input terminal.

Here, it is assumed that data is held in the register, that is, the data holding means 20, at the rising edge of the tarok. There is no difference even if the data is held in the register at the falling edge of the clock.When the data input via the data input terminal 1 fluctuates, the data fluctuation detection means 11 notifies the phase control means 12 that the data has fluctuated. The 0 phase control means 12 controls the phase of the reference clock applied via the reference clock input terminal 2, using the signal indicating data fluctuation from the data fluctuation detection means 11 as a reference signal,
Generate sampling clock.

This sampling clock is given a delay equivalent to the data hold time, and by aligning the phase of the reference signal and the sampling clock, equation (3) can be satisfied and the longest time can be allocated to the propagation delay. It is possible to generate a timing clock that rises at an appropriate timing in order to hold such data as possible.

The means for aligning the phase of the sampling clock with the reference signal is phase control (Phase Locked Loop).
).

(Example) Next, an example of the present invention will be described with reference to the drawings. In FIG. 2, reference numeral 10 denotes a sampling clock generating means, which is composed of a data fluctuation detecting means 31, a phase difference voltage converting means 32, and a voltage frequency converting means 33.

Further, 20 is a data holding means, 1 is a data input terminal, and 2 is a reference clock input terminal. 30 is a delay element. The delay element 30 is composed of N stages of gates. When the data input via the data input terminal 1 fluctuates, the data fluctuation detection means 31 outputs a reference signal and activates the phase difference voltage conversion means 32.

The activated phase difference voltage conversion means 32 starts time integration, finishes the integration at the rising edge of the sampling clock output from the voltage frequency conversion means 33, and outputs a voltage proportional to the phase difference between the reference signal and the sampling clock. do. When the sampling clock rises first, the voltage frequency conversion means 33 controls the oscillation frequency by the voltage output from the phase difference voltage conversion means 32, and temporarily changes the frequency to generate the sampling signal from the reference clock. Align the clock phase with the reference signal. A delay element 30 is inserted between the voltage frequency conversion means 33 that outputs the sampling clock and the data holding means 20 to provide a delay corresponding to the data hold time, and by aligning the phases of the reference signal and the sampling clock, (3) Satisfy the formula and pass it on! ! Generate a tarok that rises at the optimal timing to hold data so that the longest delay time can be used.

(Effects of the Invention) As explained above, according to the present invention, the synchronous circuit can be operated with a high frequency clock by reducing the skew, which is the margin required for the synchronous circuit to operate normally. becomes possible. by this,
The processing capacity of a pipeline processing device composed of synchronous circuits can be increased.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the constituent elements of the present invention, FIG. 2 is a diagram showing an embodiment of the data transfer method in the synchronous circuit of the present invention,
FIG. 3 is a diagram showing the time relationship between set-up time, data hold time, and rising edge of the clock. 1...Data input terminal, 2...Reference tally clock input terminal, 10...Sampling clock generator H, IB
. 31... Data fluctuation detection means, 12... Phase control means, 20... Data holding means, 30... Delay element,
32... Phase difference voltage conversion means, 33... Voltage frequency conversion means.

Claims (1)

[Claims] A data transfer method in a synchronous circuit that operates in synchronization with a clock includes means for detecting fluctuations in input data and outputting an instruction signal indicating the fluctuations in the input data, and controlling the phase of a reference clock using the instruction signal. It has means for giving a time delay of a data hold time to the reference clock whose phase is controlled and outputting it as a sampling clock, and means for sampling the input data with the sampling clock and holding the sampled data. A data transfer method in a synchronous circuit characterized by the following.