JPH1185307A - Integral delay circuit and clock generation circuit using the same - Google Patents

Abstract

(57) [Problem] To generate a clock having a certain delay amount with respect to an input clock, so that the delay amount can always be kept constant regardless of the environmental temperature and the voltage value. SOLUTION: A dummy buffer circuit 3 equivalent to a buffer circuit 2 for generating an unspecified delay amount connected to an output side of an integration delay circuit 1 is connected to a preceding stage of the integration delay circuit 1, and here the buffer circuit 2 is connected. A compensation pulse having the same pulse width as the delay amount is generated. The integration voltage is increased in advance by performing integration in the preceding clock cycle by an amount corresponding to the delay amount of the buffer circuit 2 based on the compensation pulse, so that the integration voltage reaches a predetermined threshold value This can be made earlier by the delay time of the buffer circuit 2, so that variations in the total delay amount of the integration delay circuit 1 and the buffer circuit 2 can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integration delay circuit and a clock generation circuit using the same, and more particularly to a technique for generating a clock having a fixed delay with respect to an input clock.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit (LSI) such as a microprocessor or a semiconductor memory has been required to operate at a high frequency in order to increase processing speed. Accordingly, synchronization between each LSI chip or each LSI
The frequency of a clock for synchronizing circuits in a chip has been increasing.

[0005] As the operating frequency is extremely high, it is sometimes required to generate a clock having a fixed delay amount with respect to the input clock. For example,
For very high-speed DRAM interfaces, when the microprocessor receives information from the DRAM via the bus, the timing to read from the DRAM is set to be a fixed time shorter than the timing of the input clock so that the microprocessor can receive the information at the right timing. There is a demand to delay.

Conventionally, for example, an integration delay circuit has been used to delay an input clock. In this case, it is required that the delay amount of the clock is always constant regardless of disturbance or the like. Therefore, for example, a "power supply voltage compensation type integration delay circuit" is used as a device capable of adjusting a delay amount by having a mechanism for performing self-correction for fluctuations in the power supply voltage. As shown in FIG. 5A, the power supply voltage compensation type integration delay circuit 50 mainly includes a variable current source 51.
, Capacitor 52, inverter 53, switch 5
And 4.

According to the power supply voltage compensation type integration delay circuit 50, the switch 54 is turned on by the supply of the input clock, and the voltage is gradually accumulated in the capacitor 52 by the integration operation as shown in FIG. The input to the inverter 53 gradually increases. Thereafter, by outputting a clock when the integrated voltage exceeds the logical threshold value of the inverter 53, the clock can be delayed by the time from the start of integration until the threshold value is reached.

However, the logical threshold value of the inverter 53 is
Since the power supply voltage is generally set to about １ ／ of the power supply voltage, if the power supply voltage changes, the logical threshold value also changes, and accordingly, the delay amount also changes. Therefore, by changing the current in proportion to the power supply voltage by the variable current source 51, even if the logic threshold of the inverter 53 changes due to the fluctuation of the power supply voltage, the integration speed (rise curve of the integration voltage) changes correspondingly. As a result, a certain amount of delay can be maintained. It is also possible to change the current of the variable current source 51 according to an external instruction.

[0007]

However, in an actual circuit, as shown in FIG. 6, a buffer circuit 54 or a gate (not shown) is provided as a buffer circuit for an internal circuit (not shown) after the power supply voltage compensating integration delay circuit 50, as shown in FIG. Is provided. Therefore, the clock signal generated by the power supply voltage compensation type integration delay circuit 50 and having a fixed delay amount with respect to the input clock is input to the buffer circuit 54 and a gate (not shown), Used for processing in the circuit.

However, the buffer circuit 54 and the gate (not shown) have a characteristic that the delay is caused by itself and the amount of the delay changes depending on a supplied voltage and an environmental temperature. Therefore, the power supply voltage compensation type integration delay circuit 50
Therefore, even if the delay amount is kept constant, the overall delay amount becomes unstable due to the buffer circuit 54 and the gate (not shown) in the subsequent stage. In other words, in the design, the integration delay circuit 5
Even if a fixed delay amount is specified by 0 or the buffer circuit 54, there is a problem that the specified delay amount cannot be obtained on a circuit that actually operates.

The present invention has been made to solve such a problem. When a clock having a certain amount of delay with respect to an input clock is generated, the amount of delay is independent of the environmental temperature and the voltage value. The goal is to be able to keep constant at all times.

[0010]

SUMMARY OF THE INVENTION An integration delay circuit according to the present invention is an integration delay circuit for obtaining a predetermined delay amount by performing integration until a predetermined threshold is reached. Is characterized in that it has a sequence structure in which integration is performed in advance at least one clock before the cycle of performing the integration by the amount of delay of the buffer circuit connected to the subsequent stage.

Another feature of the present invention is an integration delay circuit for obtaining a predetermined delay amount by performing integration until a predetermined threshold is reached. Before inputting an integration pulse that is a trigger to perform, a compensation pulse having the same pulse width as the delay amount of the buffer circuit connected in the subsequent stage is input in advance, and the integration is divided into a plurality of phases according to these pulses. It is characterized by performing.

Here, the compensation pulse may be generated by a second buffer circuit connected before the integration delay circuit. Further, the compensation pulse may be input at a clock cycle earlier than the clock cycle at which the integration pulse is input. Further, the compensation pulse may be input in a clock cycle immediately before a clock cycle in which the integration pulse is input.

Another feature of the present invention is that a plurality of integration delay circuits configured as described above are provided, and a compensation phase for performing integration based on the compensation pulse in each of the integration delay circuits; And an output phase in which an output clock is obtained by performing integration based on.

Further, the clock generation circuit of the present invention performs integration until a predetermined threshold value is reached, thereby providing a constant delay amount to the input clock regardless of the value of the power supply voltage. A delay circuit, a first buffer circuit connected to a stage subsequent to the power supply voltage compensation type integration delay circuit, and a delay circuit connected to a stage preceding the power supply voltage compensation type integration delay circuit and the same delay amount as the first buffer circuit A second buffer circuit for generating a compensation pulse having a pulse width, wherein the power supply voltage compensation type integration delay circuit performs at least one clock before a clock cycle for performing integration until the predetermined threshold is reached. It is characterized in that the integration is performed in advance by the amount of delay of the first buffer circuit based on the compensation pulse.

Here, the second buffer circuit is provided with the first buffer circuit.
May be configured similarly to the buffer circuit of FIG. Further, the integration based on the compensation pulse may be performed in a clock cycle immediately before a clock cycle in which integration is performed until the predetermined threshold is reached.

Another feature of the present invention is that a plurality of sets of the power supply voltage compensation type integration delay circuit and the second buffer circuit are provided, each of which performs integration based on the compensation pulse; An output phase for obtaining an output clock by performing integration until a threshold is reached is alternately switched.

According to the present invention constructed as described above, the second buffer circuit connected to the output side of the integration delay circuit and equivalent to the buffer circuit for generating an unspecified delay amount allows the delay of the buffer circuit to be reduced. A compensation pulse having the same pulse width as the amount is generated. Then, by performing integration based on the compensation pulse, the integration voltage is increased in advance by the delay amount of the buffer circuit. That is, the integration is performed earlier by an amount corresponding to the delay amount generated at the subsequent stage of the integration delay circuit, so that the time required for the integrated voltage to reach the predetermined threshold is shortened by the delay time of the buffer circuit. Variations in the total delay amount of the delay circuit and the subsequent buffer circuit can be suppressed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment of a clock generation circuit to which an integration delay circuit according to the present invention is applied, and FIG. 2 is a diagram illustrating an operation of the integration delay circuit according to the present invention. Hereinafter, the integration delay circuit and the clock generation circuit of the present embodiment will be described with reference to FIGS.

In FIG. 1, a power supply voltage compensation type integration delay circuit 1 has a configuration substantially similar to the configuration shown in FIG. 5, and has a constant delay amount with respect to an input clock irrespective of a change in power supply voltage. Generated clock. At the subsequent stage (output stage) of the power supply voltage compensation type integration delay circuit 1, for example, a buffer circuit 2 is provided as a buffer circuit, and the clock generated by the power supply voltage compensation type integration delay circuit 1 is buffered. After being input to the circuit 2, it is used for subsequent processing (not shown).

As described in the description of the conventional example, the buffer circuit 2 has a characteristic that it has its own delay and the amount of delay changes depending on the environmental temperature and the supply voltage value. 1 and the total delay amount of the buffer circuit 2 must always be constant. Therefore, in the present embodiment, a dummy buffer circuit 3 for delay compensation (hereinafter, referred to as a dummy buffer circuit) is provided at a stage (input stage) before the power supply voltage compensation type integration delay circuit 1.

The dummy buffer circuit 3 is configured as the same as the buffer circuit 2 as much as possible. Preferably, the buffer circuit 2 and the dummy buffer circuit 3 are formed on the same silicon substrate, and furthermore, are formed with very similar shapes, properties, standards and the like. This is because the dummy buffer circuit 3 has substantially the same delay characteristics as the delay characteristics of the buffer circuit 2.

The power supply voltage compensation type integration delay circuit 1 includes:
Two clocks are input. One is FIG.
The input clock is as shown in FIG.
The input clock is a clock output through the dummy buffer circuit 3. Power supply voltage compensation type integration delay circuit 1
Generates an integration pulse as shown in FIG. 2B using these two clocks, and performs the integration operation over two cycles of the input clock as shown in FIG. 2C.
It is divided into two sessions. FIG. 2 (b) is the same as FIG.
This corresponds to the operation when the middle buffer delay = “large”.

The two integration operations include an output phase as an integration period for outputting a clock signal having a fixed delay amount from the input clock from the buffer circuit 2, and an output phase before the output phase. Two operations are a compensation phase, which is an integration period for performing integration in advance for the delay time of the buffer circuit 2 predicted by the dummy buffer circuit 3 during the clock cycle.

In order to realize such an integration operation divided into two phases, it is necessary to define at least the following three timings with respect to the integration pulse shown in FIG. That is, there are three rising timings A for starting the compensation phase, falling timings B for ending the compensation phase, and rising timings C for starting the output phase. The integration operation in the output phase ends when the integrated value reaches a logical threshold value of an inverter (not shown in FIG. 1) provided at an output stage in the power supply voltage compensation type integration delay circuit 1.

According to the clock generation circuit of this embodiment configured as described above, in the compensation phase, the delay time of the dummy buffer circuit 3 provided before the power supply voltage compensation type integration delay circuit 1 (this is the integration pulse From the rising timing A to the falling timing B, which is the same as the delay time of the buffer circuit 2 provided at the subsequent stage of the power supply voltage compensation type integration delay circuit 1). Performs integration in advance.

Thus, when the power supply voltage compensation type integration delay circuit 1 enters the output phase and performs integration in the next clock cycle, integration is continuously performed from the integration value obtained in the earlier compensation phase. Therefore, the logic threshold value is reached earlier by the integration time (the delay time of the dummy buffer circuit 3) in the compensation phase. That is, the integration time in the output phase is shortened by the delay time of the buffer circuit 2. Therefore, the output timing of the clock further delayed by the clock output from the power supply voltage compensation type integration delay circuit 1 passing through the buffer circuit 2 is:
It is always at the desired timing and is stable.

That is, as shown in FIG. 2C, when the buffer delay amount is 0 (when there is no buffer circuit 2), when the buffer delay amount is "small" (when the buffer circuit 2
In any case, when the buffer delay amount is “large” (when there are two buffer circuits 2), the integration is previously performed in the compensation phase by the delay time of the buffer circuit 2 in each case. Is performed, the total delay amount in the output phase can always be the same, and the output timing from the buffer circuit 2 can always be the desired timing D.

The delay amount of the buffer circuit 2 varies depending on the environmental temperature and the supply voltage value.
Have the same delay characteristics as the buffer circuit 2. Therefore, the amount of delay of the dummy buffer circuit 3 changes in the same manner as the buffer circuit 2 depending on the environmental temperature and the supply voltage value. And
As shown in FIG. 2, the compensation phase is performed just one clock before the output phase, and one clock cycle is as short as about 10 ns. Thus, the delay amount of the buffer circuit 2 can be accurately predicted.

The compensation phase is most preferably performed between the output phase to be performed and the previous output phase, but the present invention is not limited to this. In other words, if the output phase using the buffer circuit 2 and the compensation phase in which the delay amount of the buffer circuit 2 is predicted by the dummy buffer circuit 3 are within a time period in which it is not expected that a large environmental change occurs, the output phase The process of the compensation phase may be performed several clocks before.

In the examples of FIGS. 1 and 2, the compensation phase and the output phase are performed every other clock.
An output clock having a fixed delay amount cannot be obtained for each clock. In order to obtain the same for each clock, two sets of similar circuits may be prepared, and the compensation phase and the output phase may be alternately performed in each circuit. FIG.
Is a diagram showing a circuit configuration example for realizing this,
FIG. 4 is a timing chart showing the operation.

In FIG. 3, reference numerals 10 and 20 denote integrators having the same configuration, and the internal configuration of one integrator 10 is shown as a representative. The currents from the variable current source 11 are both input to these two integrators 10 and 20.
The compensation phase and the output phase are alternately repeated. That is, when the integrator 10 is in the compensation phase, the integrator 20 is in the output phase, and when the integrator 10 is in the output phase, the integrator 20 is in the compensation phase.

The variable current source 11 realizes a first variable element for making the current have a fixed relation (for example, a proportional relation) with respect to a power supply voltage (not shown) and a delay amount set from the outside. And a second variable element for performing 1
Reference numeral 2 denotes a capacitor that stores the integrated voltage d5, and reference numeral 13 denotes an inverter that inverts the output d6 at a predetermined logical threshold. Reference numeral 14 denotes a compensation switch that is turned on when the compensation phase is executed, 15 denotes an output switch that is turned on when the output phase is executed, and 16 denotes a reset switch for resetting the integrated voltage d5 to zero. .

With the above configuration, the variable current source 11
The voltage gradually accumulates in the capacitor 12 by the integration operation using the current from the inverter 13 and the input to the inverter 13 gradually increases. Thereafter, when the integrated voltage d5 exceeds the logical threshold of the inverter 13, the inverter 13
Is inverted to "L" level. The output signal d6 of the inverter 13 is supplied to one input terminal of the negative logic OR circuit 17, and the other input terminal is connected to the integrator 2
An output signal d6 'from an inverter (not shown) within 0 is supplied.

The negative logic OR circuit 17 is a synthesizing circuit that outputs an "L" level pulse when one of the signals d6 and d6 'output from the two integrators 10 and 20 is at an "L" level. is there. In the subsequent stage of the negative logic OR circuit 17,
A buffer circuit 18 (corresponding to the buffer circuit 2 in FIG. 1) is connected, and after being delayed by a predetermined time by this, is output as a clock d10 having a predetermined delay amount with respect to the input clock.

Reference numerals 30 and 40 denote controllers having the same configuration, and correspond to the two integrators 10 and 20, respectively.
Control for switching between the compensation phase and the output phase is performed. For example, the controller 30 controls the integrator 10, and its internal configuration is shown as a representative. The input clock d0 is supplied to these two controllers 30 and 40 by dividing the frequency of the input clock d0 by に よ り by the 分 frequency divider 50. The dummy buffer circuit 31 is configured as similar to the buffer circuit 18 as possible. (Corresponding to the dummy buffer circuit 3 in FIG. 1).

The output terminals of the 1/2 frequency divider 50 include a terminal Q and a terminal Q bar. The output signal d1 from the terminal Q is supplied to the dummy buffer circuit 31
And the positive logic AND circuit 32. Positive logic AND
The circuit 32 outputs the output signal d2 from the dummy buffer circuit 31 and the output signal d from the terminal Q of the 1/2 frequency divider 50.
When the two input signals d1 and d2 are both at the "H" level, a "H" level signal d3 is supplied to the compensation switch 14, and the switch is turned on.

From the terminal Q bar of the 1/2 frequency divider 50, a signal d4 obtained by inverting the output signal d1 from the terminal Q is output.
Is supplied to one input terminal of the positive logic AND circuit 33 and the flip-flop 34 for stopping integration. The flip-flop 34 includes the inverter 1
3 is also supplied, and when these two input signals d4 and d6 are both at the "H" level, "H" is output.
The level signal d8 is output to the other input terminal of the positive logic AND circuit 33. When these two input signals d4 and d8 are both at the "H" level, the positive logic AND circuit 33 supplies the "H" level signal d9 to the output switch 15 and turns on the switch.

The output signal d6 from the inverter 13
Is also supplied to the reset pulse timer 35. The reset pulse timer 35 measures a predetermined delay time after the output signal d6 from the inverter 13 is inverted to “L” level, turns on the reset switch 16 by the signal d7 at the end of the output phase, and sets the integrated voltage. Is initialized to zero. The operation of the clock generation circuit thus configured will be described below with reference to the timing chart of FIG.

First, the input clock d shown at the top of FIG.
As 0 is divided by に よ り by the １ ／ frequency divider 50, a signal d1 is output from the terminal Q, and a signal d4 obtained by inverting the signal d1 is output from the terminal Q bar. The signal d1 output from the terminal Q is supplied to the dummy buffer circuit 31
, The signal is delayed by a certain amount, resulting in a signal d2. At this time, the positive logic AND circuit 32 outputs “H” only while both the signal d1 and the signal d2 are at “H” level.
The signal d3 which becomes a level is output.

The output signal d3 of "H" level from the positive logic AND circuit 32 causes the compensating switch 14 to operate.
Is turned ON, and the integration of the compensation phase is executed. This allows the capacitor 12 during this compensation phase to be performed.
, The integrated voltage d5 (supplied to the input terminal of the inverter 13) gradually increases. Thereafter, when the signal d3 goes to the “L” level, the integration stops. The first cycle of the input clock d0 ends after executing the compensation phase in this way.

In the next cycle, the output phase is executed. That is, in synchronization with the rise of the signal d4 output from the terminal Q bar of the 1/2 frequency divider 50, the positive logic AND
The output signal d9 of the circuit 33 becomes “H” level (the signal d
4 rises, the output signal d8 of the flip-flop 34 is at "H" level, and the positive logic AND circuit 3
3 are both at "H" level), whereby the output switch 15 is turned on.

When the output switch 15 is turned on,
The integration operation in the output phase is started, and the integrated voltage d5 accumulated in the compensation phase in the previous clock cycle further gradually increases. Thereafter, when the integrated voltage d5 exceeds the logical threshold value of the inverter 13, the output signal d6 of the inverter 13 is inverted from "H" level to "L" level. The signal d <b> 6 at the “L” level is supplied to the flip-flop 34 and the reset pulse timer 35.

When an "L" level signal d6 is input from the inverter 13 to the integration stop flip-flop 34, the output signal d8 of the flip-flop 34 becomes "L".
And the output signal d9 of the positive logic AND circuit 33 becomes “L” level in response to this.
5 becomes OFF. When the signal d6 at "L" level is input to the reset pulse timer 35, the signal d7 attains "L" level after a certain period of time, and accordingly, the reset switch 16 is turned on to set the integrated voltage. d
5 is reset to zero. At this time, the inverter 13
Returns to the "H" level.

After executing the output phase and returning to the initial state, the compensation phase is executed again in the next clock cycle. Hereinafter, in the same manner, the compensation phase and the output phase are repeatedly executed. The clock pulse d6, which is the output signal of the inverter 13 generated in this manner, is supplied to the negative logic OR circuit 17 and the buffer circuit 18
(Composed of three inverters).

Thus, the signal d10 that rises after the delay time of the buffer circuit 18 (same as the delay time in the compensation phase) after the integration in the output phase is completed.
Is obtained as an output clock. That is, it is possible to obtain the output clock d10 in which the total delay amount obtained by adding the delay time in the compensation phase and the delay time in the output phase to the input clock d0 is always constant.

Here, if one of the integrators 10 in FIG. 3 operates as shown in FIG. 4, the other integrator 20 operates in the reverse cycle. That is, the integrator 1
When 0 is the compensation phase, the integrator 20 operates in the output phase, and when the integrator 10 is in the output phase, the integrator 20 operates.
Operates in the compensation phase. Thus, in a cycle in which a pulse of the output clock d10 is not obtained by one of the integrators 10, a pulse is obtained by the other integrator 20.

With the above configuration, the integration operation of the output phase is performed by the two integrators 1 over all clock periods.
0 or 20 is always performed, and the clock pulse obtained by this operation is applied to the negative logic OR circuit 17.
Then, the data is sequentially output for each clock via the buffer circuit 18. Therefore, an output clock having a fixed delay amount can be obtained for each clock.

In the example shown in FIG. 3, two sets of integrators and controllers having the same configuration are provided so that two phases are repeatedly executed, but the present invention is not limited to this. For example, in order to realize that the delay amount of the output clock with respect to the input clock is set to zero, the integration time cannot be made zero, so one clock delay must be regarded as zero delay. Since this is output at a timing exceeding one clock, it cannot be realized without at least four phases in order to secure a long integration time. Therefore, when a zero delay is required, at least four integrators and controllers having the same configuration are provided and four phases (for example, three compensation phases and one
Two output phases).

In addition, the configuration of each part shown in the above embodiment is only an example of the embodiment for carrying out the present invention, and the technical scope of the present invention is limited by these. It must not be interpreted. The present invention can be embodied in various forms without departing from the spirit or main features thereof. Therefore, the above embodiments are merely examples in all respects, and should not be construed as limiting.

[0050]

According to the present invention, as described above, a sequence structure in which integration is performed in advance by a delay amount of a buffer circuit connected in a subsequent stage before a cycle of performing integration until a predetermined threshold is reached is achieved. As a result, the time required for the integrated voltage to reach the predetermined threshold value can be shortened by the delay time of the subsequent buffer circuit. This makes it possible to suppress the variation in the total delay amount of the integration delay circuit and the buffer circuit in the subsequent stage, and to provide a delay amount with respect to the input clock in the clock generation circuit in which the buffer circuit is connected downstream of the integration delay circuit. When generating a clock having the following, an output clock with a constant delay amount can be obtained regardless of the environmental temperature or the voltage value.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a clock generation circuit to which an integration delay circuit according to the present invention is applied.

FIG. 2 is a diagram for explaining an operation of the integration delay circuit according to the present invention.

FIG. 3 is a diagram showing another embodiment of the clock generation circuit according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the clock generation circuit shown in FIG. 3;

FIG. 5 is a diagram showing a configuration example of a conventional power supply voltage compensation type integration delay circuit and its operation.

FIG. 6 is a diagram illustrating a configuration example of a conventional clock generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply voltage compensation type integration delay circuit 2 Buffer circuit 3 Delay compensation dummy buffer circuit 10, 20 Integrator 11 Variable current source 12 Capacitor 13 Inverter 14 Compensation switch 15 Output switch 16 Reset switch 17 Negative logic OR circuit 18 Buffer Circuits 30, 40 Controller 31 Dummy buffer circuit for delay compensation 32, 33 Positive logic AND circuit 34 Flip-flop 35 Reset pulse timer 50 1/2 divider d0 Input clock d5 Integration voltage d10 Output clock

Claims (10)

[Claims] An integration delay circuit for obtaining a predetermined delay amount by performing integration until a predetermined threshold is reached, wherein at least one clock before a cycle of performing integration until the predetermined threshold is reached, An integration delay circuit having a sequence structure in which integration is performed in advance by a delay amount of a buffer circuit connected to a subsequent stage. 2. An integration delay circuit for obtaining a predetermined delay amount by performing integration until a predetermined threshold value is reached, wherein an integration pulse serving as a trigger for performing integration until the predetermined threshold value is reached is provided. Before inputting, a compensation pulse having the same pulse width as the delay amount of the buffer circuit connected in the subsequent stage is input in advance, and integration is performed in a plurality of phases according to these pulses. Integral delay circuit. 3. The integration delay circuit according to claim 2, wherein the compensation pulse is generated by a second buffer circuit connected before the integration delay circuit. 4. The integration delay circuit according to claim 2, wherein the compensation pulse is input at a clock cycle earlier than a clock cycle at which the integration pulse is input. 5. The integration delay circuit according to claim 4, wherein the compensation pulse is input in a clock cycle immediately before a clock cycle in which the integration pulse is input. 6. A compensation phase in which a plurality of integration delay circuits according to claim 1 are provided, wherein integration based on said compensation pulse is performed in each of the integration delay circuits, and a compensation phase based on said integration pulse is provided. An integration delay circuit which alternately switches between an integration phase and an output phase for obtaining an output clock. 7. A power-supply-voltage-compensation-type integration delay circuit that performs integration until a predetermined threshold value is reached, thereby providing a constant amount of delay to an input clock irrespective of the value of the power-supply voltage. A first buffer circuit connected downstream of the integrated delay circuit; and a compensation pulse connected upstream of the power supply voltage-compensated integrated delay circuit and having the same pulse width as the delay amount of the first buffer circuit. A power supply voltage compensation type integration delay circuit, based on the compensation pulse, at least one clock before a clock cycle for performing integration until the predetermined threshold is reached. A clock generation circuit for performing integration in advance by an amount corresponding to the delay amount of the buffer circuit. 8. The clock generation circuit according to claim 7, wherein said second buffer circuit is configured similarly to said first buffer circuit. 9. The clock generation circuit according to claim 7, wherein the integration based on the compensation pulse is performed in a clock cycle immediately before a clock cycle for performing integration until the predetermined threshold is reached. 10. A plurality of sets of the power supply voltage compensation type integration delay circuit and the second buffer circuit, each of which performs integration based on the compensation pulse, and performs integration until the predetermined threshold is reached. 10. The clock generation circuit according to claim 7, wherein an output phase for obtaining an output clock is alternately switched.