JPH0473685A - Display controller - Google Patents

Abstract

PURPOSE:To preferentially display a specified event by outputting the address of a display element in accordance with the setting of display element information related to the event and transferring the display data which is read out from a display data storing means based on the address to a display device. CONSTITUTION:In the case that the data is read out from a video memory 41 so that it may be transferred to a liquid crystal display device FLCD 26, and the data transfer demand is generated from a synchronization control circuit 39 to a memory controller 40. The address of an address counter 38 or on the side of an FIFO is selected by an address selector 35 as the address with reference to the video memory 41, and also a control signal for the data transfer is generated by the memory controller 40, and then, the data on an applicable address is transferred from a memory cell to a shift resistor so as to be outputted to a driver 42 by the control signal of a serial port. Thus, rewriting a part related to the event is preferentially performed by setting the position, etc., related to the partial rewriting by a CPU on the host side of a display device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, a display that is updated by applying an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a display control device for a display device including a display element that can maintain a state.

[Prior Art] Display devices are generally used in information processing systems as information display means that performs the function of visually expressing information, and CRT display devices are widely known as such display devices. .

In display control in a CRT display device, a writing operation by a system CPU to a video memory as a display data buffer on the CRT side and an operation for reading display data from the video memory and displaying one display by a CRT controller on the CRT side are independent of each other. is executed.

In the case of CRT display control as described above, the writing of display data to a video memory for changing display information and the operation of reading and displaying display data from the video memory are independent, so the information processing The program on the system side does not need to consider display timing or the like at all, and has the advantage that desired display data can be written at any timing.

However, on the other hand, since CRTs require a certain length in the thickness direction of the display screen, their overall volume is large (which makes it difficult to miniaturize the entire display device. The degree of freedom in using an information processing system using the display as a display device, that is, the degree of freedom in terms of installation location, portability, etc., is impaired.

A liquid crystal display (hereinafter referred to as LCD) can be used to compensate for this point. That is, according to the LCD, the entire display device can be made smaller (particularly thinner). Some of these more advanced LCDs include the above-mentioned ferroelectric liquid crystal (hereinafter referred to as FLC).
There is a display device (hereinafter referred to as FLCD: FLC display) that uses a liquid crystal cell (called Quid Crystal), and one of its features is that the liquid crystal cell maintains its display state against the application of an electric field. be. In other words, in %FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the applied force direction of the electric field, and the electric field is applied. Even when removed, each orientation state is maintained. Due to this strong bistability of FLC molecules, FLCD has memory properties.

Details of such FLC8 and FLCD are described in, for example, Japanese Patent Application No. 1983-76357.

As a result, when driving an FLCD, unlike a CRT or other liquid crystal display, there is a time margin in the cycle of continuous refresh drive of the display screen, and there is also a time margin in the cycle of continuous refresh drive of the display screen. , it becomes possible to perform partial rewriting drive that updates the display state of only the changed portion on the display screen.

[Problems to be Solved by the Invention] Therefore, if appropriate and timely partial rewrite driving can be performed in FLCDs, the advantages of FLCDs will be further increased.

In addition, such F is used as a display device of an information processing system.
The ability to use LCDs interchangeably with CRTs increases the flexibility and value of the system.

From the above viewpoint, it is possible to consider a display control mode in which predetermined partial rewriting is given priority over other partial rewriting of display information. An example of such a display is a display of cursor movement, and the display state of this display must be changed in real time (intuitively) in accordance with the operation of a mouse or the like by the operator.

If such a display is defined as an event, a configuration for performing partial rewriting for the event according to the priority order among multiple events is proposed, for example, in Japanese Patent Application Laid-Open No. 2-934 by the applicant.
It is disclosed in No. 91. However, in display control with this configuration, when a partial rewrite related to an event is performed, the information processing system side provides information for identifying this process to the display device side. Therefore, a control program for an information processing system using such a display device is significantly different from a control program for an information processing system using the above-mentioned CRT as a display device.

As a result, it becomes difficult to configure an information processing system that is compatible with FLCD and CRT.

On the other hand, when an FLCD is used as a display device of an information processing system while being compatible with a CRT, an essential problem arises in its configuration. That is, the CPU on the system side only transfers display data related to display updating and its address to the display device side. Therefore, there arises the problem of how to distinguish the partial rewriting related to the above-mentioned event from other partial rewriting, and as a result of this discrimination, how to prioritize the partial rewriting related to the event.

The present invention has been made in view of the above-mentioned problems, and it is possible to easily and reliably capture a specific event and display it in priority to other partial rewriting displays, and it also provides an information processing system. An object of the present invention is to provide an FLCD display control device that is compatible with a CRT without significantly changing the side software.

[Means for Solving the Problems] To this end, the present invention provides a display control device for a display device that is capable of updating the display state of only the display elements related to a change in display, in which a display control device corresponding to each of the display elements is provided. display data storage means for storing display data; address output means for outputting the address of the display element related to the event according to settings of display element information related to the event; and based on the address output from the address output means. The display device is characterized by comprising data transfer means for transferring display data read from the display data storage means to the display device.

[Operation] According to the above configuration, partial rewriting related to an event can be performed by
For example, the host side CPU of the display device can perform partial rewriting preferentially by setting the position for partial rewriting.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

(System Configuration) FIG. 1 is a block configuration diagram of the entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, 11 is a C that controls the entire information processing system.
Po, 12 is a system bus consisting of an address bus, a control bus, and a data bus; 13 is a main memory used for storing programs and as a work area;
4 is a DMA controller (DirectM) that transfers data between the memory and the I10 device without going through the CPU II.
El! 1ory Access Controller
, hereinafter referred to as DMA (:), 15 is Ethernet (XE
LAN interface between the LAN (local area network) 16 such as ROX (by ROX), 17 is the R
110 device for connecting I10 devices consisting of OM, SRAM, R3232C specification interface, etc., 18 is a hard disk device, 19 is a floppy disk device, 20
is hard disk device 18 or floppy disk device 1
9, 21 is a high-resolution printer such as a laser beam printer or an inkjet printer, 22 is a printer interface for printer 2], 23 is a keyboard for inputting characters such as letters, numbers, etc., 24 is a mouse which is a pointing device, 25 is a keyboard 23 and a mouse 2
4, 26 is an FLCD (FLC display) that can be constructed using a display device disclosed in Japanese Patent Application Laid-Open No. 63-243993 by the present applicant, and 27 is an FL (:D interface) for FLCD 26. be.

(Display control device) Figure 2 shows an FLC as an embodiment of the display control device of the present invention.
2 is a block diagram showing an example of the configuration of a D interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. Address data from the CPU II is supplied from the address bus driver 31 to one input section of the memory controller 40 and the address selector 35, and is selectively supplied to the FIFO memory 36 or 37 by switching the first switch S1. and memorized. That is, these memories 36 and 37 (hereinafter referred to as FIFO(^) and FIFO(), respectively)
Bl) is a FIFO (First In First Out) memory that reads data in the order in which it is written, and the address data written in these memories 36 and 37 can be selectively read out by switching the second switch S2. It will be done.

Address data read from these memories 36 or 37, address data from an address counter 38, which will be described later, and a partial rewrite request circuit 100, which will also be described later.
The address data from the address selector 35 is selectively applied to the other input section of the address selector 35 by switching the selector 50. The address counter 38 generates address data for refreshing the entire screen line-sequentially, and the timing of generation of the address data is controlled by the synchronization control circuit 39. This synchronous control circuit 39 includes the switches Sl, S2 and the selector 5.
0 switching control signal Sl (A/B), S2 (
A/B), a select control signal 5LCT, and a data transfer request signal to a memory controller 40, which will be described later, are also generated.

Furthermore, the partial rewrite request circuit 100 and the synchronization control circuit 39 exchange a request signal REQ requesting partial rewriting and an acknowledge signal ACK when an event occurs (in this example, when the cursor is moved).

The control signal from cputt is given from the control bus driver 32 to the memory controller 40, which generates control signals for the sampling counter 34, address selector 35, and video memory 41, which will be described later. The sampling counter 34 performs a counting operation based on the sidewalk signal from the memory controller 40, and the synchronous control circuit 39
A control signal C is generated. In addition, the address selector 35
, selects one of the two address data given to the input section of the address selector 35 and supplies it to the video memory 41 based on a control signal from the memory controller 40 .

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads display data via the data bus driver 33.

The display data written in the video memory 41 is supplied to the image data synthesis circuit 20[1 via the driver receiver 42, where appropriate image synthesis is performed, and then the FLC
It is transferred to D26 and displayed.

Further, the driver receiver 42 provides the synchronization signal from the FLCD 26 to the synchronization control circuit 39. FLCD2
6 incorporates a temperature sensor 26a that detects the temperature of the FLC.

Further, setting data, which will be described later, from the CPU II is provided to the synchronization control circuit 39 via the data bus driver 43. Further, the output signal of the temperature sensor 26a is transferred to the CPU II via the data bus driver 44.

Note that 47 is engaged with the data bus on the system bus 12 and requests the partial rewrite request circuit 100 to send the video memory 41
48 is a bus driver for setting the position information of image data such as a cursor (hereinafter referred to as compositing data) to be synthesized with internal data; It is a receiver for

The FLCD interface main body within the broken line indicated by the reference numeral 300 and the circuit section indicated by the reference numeral 400 including the partial rewrite request circuit 100 and the image data synthesis circuit 200 may be configured as one unit, but they may be configured separately. circuit section 400
can be attached to the FLCD interface main body 300. In other words, the circuit unit 400 may be an external circuit to the FLCD interface main body 300, and in this case, it is suitable to be installed when the FLCD interface main body 300 is applied to, for example, a system compatible with the so-called hard cursor function described above. . In other words,
When displaying or moving synthetic data such as a cursor in systems that support the hard cursor function, CPU 1
Even if the system does not access the video memory 41, such an event can be detected and partial rewriting can be activated accurately and quickly, thereby realizing image composition.

FIG. 3 shows a configuration example of a partial rewrite request circuit 100 compatible with a hard cursor according to this example.

Here, 101 and 102 are position registers (referred to as position registers I and ■, respectively) for storing the old position or new position of the cursor, and alternately latch values in response to settings from the CPU II. That is, when displaying or moving the cursor, one memorizes the old position and the other memorizes the new position. A cursor size register 105 is used to store the size of the cursor to be displayed, and the size is set by the CPU II. C
When displaying or moving the cursor, PUII sets the new position of the cursor in position register I or H and sets its size in the cursor size register 105, but does not set the size unless the size has changed (but good.

107 is a request control circuit, and the position register I or H
When the new position of the cursor is set to , the contents of the position register ■ or I that stores the old position are loaded into the request address counter 109, and the synchronization control circuit 39
A partial rewrite request signal REQ is sent to update the cursor. Then, when an acknowledge signal ACK is supplied from the synchronization control circuit 39, the request address counter 109
The requested address counter 109 sequentially counts up the line address at the old position by the cursor size (number of lines) set in the cursor size register 105 and sends the value to the selector 50 side. Since the FLC has a memory property, the cursor at the old position is immediately erased prior to updating the cursor, as will be described later. Specifically, only the data in the video memory 41 at that position is erased. This is a group of line addresses used for redisplay.

Thereafter, the request control circuit 107 loads the value of the position register storing the new position into the counter 109 and transmits the signal REQ, and in response to the input of the signal ACH, the request control circuit 107 causes the counter 109 to perform the same operations as described above regarding the new position. make the action take place. The line address group output at this time is used to display the cursor at the movement destination.

The cursor is moved (updated) by repeating the above operations every time a new cursor position is set from the CPU II. In order to alternately set new positions in the position registers I or (2) and alternately load the counter 109, for example, a toggle-operated switch may be inserted at an appropriate location.

FIG. 4 shows a configuration example of an image data synthesis circuit 200 compatible with a hard cursor according to this example.

Here, 201 is a position register in which the new position of the cursor updated by CPUIT is set, and 205 is a cursor size register in which the cursor size is also set.

FIG. 5 is an explanatory diagram of data stored in these registers. As shown in FIG. 0, the upper left corner of the display screen is the origin (0
, O), and the relative distance (X, Y) from that point becomes the cursor position and is stored in the position register 201. On the other hand, its width W and height H are determined by the cursor size register 20.
Set to 5.

Note that the contents stored in the position registers 101 and 102 and the cursor size register 105 in the partial rewrite request circuit 100 shown in FIG. 3 may be the same as the position register 201 and the cursor size register 205, respectively.
Since the partial rewrite request circuit 100 in FIG. 3 only needs to output a line address, only data in the sub-scanning direction (Y and H, respectively) is set in the position registers 101, 102 and the cursor size register 105. It's okay. Further, the contents of the cursor size register 205 in FIG. 4 may be changed only when the cursor size is changed, as described above.

In FIG. 4, ID! 3 and AD are respectively FLC
These are the identification signal and address/data signal transmitted from the video memory 41 of the D interface main body 300. To explain these signals using FIG. 6, FLCD
The interface main body 300 outputs a data group of one main scanning line (H direction line in FIG. 5) in response to the horizontal synchronizing signal H3YNC from the FLCD 26. This data group is a data group from the leftmost pixel to the rightmost pixel in one main scanning line ("data 1", "data 2", etc.).
). The line address of the line in question is added to the head of this data group and sent out as an address/data signal AD. On the other hand, in order to identify that the beginning of the signal AD is an address, an identification signal 10 that becomes "0" when the address is output, "l", "data l", "data 2", etc. is output is sent. That is why it is done.

Referring again to FIG. 4, 207 is a sub-scanning comparison circuit. The sub-scanning comparison circuit 207 includes registers 201 and 205.
Based on the value of , it is determined whether the image data sent from the FLCD interface body 300 is included in the line on which the cursor should be displayed, based on the line address at the beginning of the image data group. That is, it is determined whether the line address to be displayed is currently between Y and Y+H (see FIG. 5). If it is determined that there is a match between the two, a match signal is sent to the main scanning counter 209.
Send to.

The main scanning counter 209 counts the number of pixels in the main scanning direction based on this coincidence signal, and calculates the X value set in the position register 201 and the cursor size register 205.
Based on the W value set in , it is determined whether the current pixel is within the range of X-X+W. If it is within that range, the cursor display data is expanded, a corresponding position in the cursor RAM is specified, data at that position is read out, and a synthesis instruction is given to the logic synthesis circuit 213.

In the logic synthesis circuit 213, when the synthesis instruction signal is not given from the main scanning counter 209, the address data signal A/D from the FLCD interface main body 300 is output as is to the FLCD 26, and when there is a synthesis instruction, the cursor RAM 211 is output to this. It performs logical operations on the data read from and outputs the synthesized data.

The following operations are performed by the configurations shown in FIGS. 3 and 4.

That is, the current position (X, Y) of the cursor is stored in one of the position registers 101 and 102 in the partial rewrite request circuit 100 and in the position register 2 in the image data synthesis circuit 200.
01, and the cursor is displayed based on the data held in the registers 201-205. Therefore, even if the line on which the cursor is displayed is accessed during a refresh cycle or partial rewrite cycle, which will be described later,
The cursor is displayed at that position on that line, and the cursor is not erased by the access.

On the other hand, when moving the cursor, ((X, Y) → (X
', Y')), the data at the new position is in registers 101 and 10.
2 (7) is set to the other side and is also set to the register 201. First, from the old position “Y” to “■4”
"The line address for the line is output, and in response, the corresponding line address and data in the video memory 41 are output to the image data synthesis circuit 200. At this time,
Since the contents of the register 201 in the circuit 200 have already been updated, the data is directly transferred to the FL without being synthesized.
Displayed on CD26. Therefore, the cursor display is erased from the line where the cursor was displayed up until then. After this, “ from the new position “Y”
In response to the output of the line address for the H'' line, cursor data is synthesized with the data of the line according to the contents of registers 201 and 205, and the new position (x',
y').

(Example of operation) In the above configuration, when cputi changes the display data in the video memory 41, the address signal of the video memory 41 corresponding to the desired data rewriting is sent to the memory controller 40 via the address bus driver 31. Here, arbitration is performed between the memory access request signal of cput i and the data transfer request signal from the synchronization control circuit 39. When the CPU accessing side obtains the right, the memory controller 40 switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41.

At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, the CPU access address 20 is transferred to the FIFO (
A) 36 or FIFO (B) 37, and is used when transferring display data, which will be described later. In this way, CP
The display data access method seen from the UII is the conventional CR
This is no different from the system using T as an indicator.

It also reads data from the video memory 41 and displays it on the FLCD.
26, a data transfer request is generated from the synchronization control circuit 39 to the memory controller 40, and the address counter 38 or FIFO side address address selector 3 is sent as the address to the video memory 41.
5 and the memory controller 4
By generating a control signal for data transfer from 0, data at the corresponding address is transferred from the memory cell to the shift register, and is output to the driver 42 by the control signal of the serial port.

The synchronization control circuit 39 completely refreshes the screen line by line in units of multiple lines based on the horizontal synchronization signal HSYNC from the FLCD 26.
Timing is generated to alternately generate partial rewrite cycles in which lines accessed by UII are rewritten. Here, the full refresh cycle is to rewrite the display screen sequentially from the top line (first line) downwards, and when it reaches the bottom line, return to the top line again and repeat the rewriting. An access line rewrite cycle is a cycle in which a line accessed by the CPU II is rewritten within a predetermined time period immediately before the cycle.

In this way, basically, in this example, the operation of sequentially refreshing the entire screen of the FLC display 26 and the operation of rewriting the line accessed by the CPU II in order to change the display contents are performed in a time-sharing manner. However, when an instruction to move the cursor is given, the latter operation period is used to quickly update the cursor display.

First, with reference to FIG. 7, the basic operation of this example will be described in which a refresh operation and a line rewriting operation are performed alternately in a time-sharing manner without performing a cursor movement display. Here, an example will be shown in which the refresh cycle is performed in units of 4 lines, and the access line rewrite cycle is performed in units of 3 lines.

In FIG. 7, REE/AC3 is a timing that causes a full refresh cycle and an access line rewriting cycle to occur alternately. In this example, T indicates the rewrite cycle, and T represents the full refresh cycle time and the T-divided access line rewrite cycle time.
Although Ta:T=4=3, an optimal value can be selected depending on the required refresh rate, etc.

That is, by increasing the ratio of T, the refresh rate can be increased, and by increasing the ratio of T, the responsiveness of partial changes can be improved. This aspect will be described later.

To explain the states of FIFO (A) 36 and FIFO (B) 37, when switch Sl is connected to FIFO (A) 36 side (state A/B = 1), CPU
The address of the line accessed by I is FIFO (A) 3
6 and stored. On the other hand switch St
is connected to the FIFO (B) 37 side (A/B= O
), the line address accessed by CPUII is FI
It is stored in FO(B) 37. Moreover, when switch S2 is connected to the FIFO (A) 36 side (A/B=1
), the address stored in FIFO (A) 3B is output, and when switch S2 is connected to the FIFO (B) 37 side (A/B = O), the address stored in FIFO (B) 37 is output. be done.

One refresh of the entire screen is completed, and the FLCD26
outputs the vertical synchronization signal VSYNC, or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the 0th line, and the FLCD 26
Each time the horizontal synchronization signal H3YNC is applied via the synchronization control circuit 39, the count is sequentially increased to "work", "2", and "3". During this time, lines Ll and L are sent from cpuit.
2. When the address of L3 is accessed, switch S1
is connected to FIFO (A) 36), so LL
, L2. The address of L3 is memorized here, and then when switch S2 is connected to FIFO (A) 36, the address of L3 is memorized here.
l, L2. The address of L3 is output from here, and the output lines are Ll, L2 . L3 is selected. Here, the switching signal of the selector 50 is the signal 5 from the synchronous control circuit 39.
FIFO (A), FIFO (
Switched to Bl side.

At this time, switch S1 is set to FIFO (B) 37
Since the access address is connected to the FIFO (B) 37 side, the access address is stored on the FIFO (B) 37 side. In the refresh cycle, the selector 50 is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 7, after the line L3 is output, lines 4", "5", "6", and "7", which are continuations of the previous cycle, are output.The above operation is repeated in the same manner, but The reason for preparing two FIFOs is to sample the address accessed by memory on one side and simultaneously output the sampled address on the other side without any contradiction (and efficiently. In other words, the sampling period of the address is from the start of output of the access line of the other FIFO until the end of the full refresh cycle, and after the end of the full refresh cycle, at the same time as the rewriting cycle of the access line that outputs the address sampled in the previous sampling period begins, F
The IFO address sampling period will begin.

As described above, in the basic operation of this example, refresh cycles and line rewrite cycles are alternately repeated, and the seventh
In the figure, the repetition period is T, with 7 lines as one unit:
In this example, T is determined based on the environmental conditions such as temperature, the type of data to be displayed, or the refresh rate required depending on the difference in the FLCD display device material. The ratio with Tb can be changed. That is, the ratio of T (corresponds to the number of lines M in one refresher cycle, that is, T, = M ×
() Period of IsYNc)) can be increased, the refresh rate can be improved, and a good display state can be obtained, for example, even when the responsiveness of a low-temperature special FLC element is low or when displaying an image. On the contrary,■
, (corresponding to the number of lines N in one partial rewriting cycle, that is, Tl1 = N This makes it possible to cope with cases where the refresh rate does not need to be high, such as at high temperatures or when displaying characters such as text.

Furthermore, in this embodiment, by making it possible to set the number of lines in the repetition cycle, it is possible to more finely change the refresh cycle and the partial rewrite rate, thereby achieving more fine-grained optimization. For example, if you need or want to give priority to the refresh rate, if the number of lines in the repetition period is 40 lines and Ta:Tb = 4:1, then the entire refresh rate will be 32
The access lines can be rewritten for 8 lines. Also, if you can or want to give priority to partial rewriting, if you change the number of lines in the repetition cycle to 10 lines and set Ta:Tb=3:2, perform full refresh for 6 lines and rewrite 4 access lines. be able to.

Furthermore, in this embodiment, within the range of the number of lines for partial rewriting set in this way, the actual number of lines for partial rewriting performed between refresh cycles is determined according to the number of lines accessed by the CPU II and the line access state. Try adjusting P. That is, the CPUI
By dynamically adjusting the 15 time period according to the number of lines accessed by I, for example, unnecessary line rewriting cycles when CPU II does not access it often can be avoided.
Improve refresh rate. This makes it possible to dynamically optimize the relationship between motion followability and refresh rate.

This applies, for example, to the patent application No. 2-10 filed by the applicant.
This can be done according to the rules and structure disclosed in No. 5626.

Next, the operating state when there is an instruction to move and display the cursor will be explained using FIG. However, in this figure, the height H of the cursor is set to "1" for simplicity.

In the device according to this example, the partial rewriting for displaying cursor movement is performed during the line access period, that is, the synchronization control circuit 39 in FIG. 2 responds to the request signal REQ only during the line access period. shall be output, and if there is an instruction to move the cursor during the refresh period, then during the line access period immediately after,
If an instruction is given during the line access period, partial rewriting for the movement display is performed within that period. Note that even if an instruction is given during a line access period, if that period has expired and processing cannot be performed, the processing will be performed during the next line access period.

Now, FIG. 8 shows the process in which the cursor located on the line having the address EXI is moved to the position on the line having the desired address EX2, and then further to the position on the line having the address EX3. There is.

When moving from EXI to EX2, first, in order to erase the cursor on the line having the current address EXI, an access to that line is requested and the request circuit 100 sends the signal R.
EQ is sent to the synchronization control circuit 39. Synchronous control circuit 3
9 waits for the end of the refresh period, returns the signal ACK, switches the selector 50, and selects the address EXI.
be accepted. Accordingly, the address E
The line with XI is accessed and
As mentioned with respect to the figure, only the data in video memory 41 on that line will be displayed, ie the cursor will be removed from that line. EX2 to E
The manner of erasing when moving to X3 is also similar.

Next, in order to display the cursor on the line having the new address EX2, the request circuit 100 requests access to that line and sends out the signal REQ. In the case of this figure, the synchronization control circuit 39 immediately returns the signal ACK and , switches the selector 50 to accept that line address. As a result, the line having the address EX2 is accessed, and as described above, the cursor data is synthesized at the new position and the cursor is displayed. EX2 to E
The manner of erasing when moving to X3 is also similar.

In this figure, partial rewriting by line access (Ll) is performed between erasing the cursor on EXI and displaying it on EXI.
However, depending on the processing speed of the synchronous control circuit 391 and the partial rewrite request circuit 100, the display on the EX2 and the output may be delayed.

In addition, in this example, to simplify the explanation, the line access period is assumed to be three lines, and the cursor height is set to "1," but in reality, as shown in Figure 5, the cursor has a height that spans multiple lines. Therefore, the line access period can be determined taking this into consideration.

(Other Embodiments) It goes without saying that the present invention is not limited to the above-described embodiments, and can employ various configurations and control methods.

For example, on the upper side, refresh periods and line access periods are alternately performed, cursor movement display is performed only during the line access period, and cursor movement display is performed with priority over normal line access. However, the cursor display is displayed even during the refresh period.
Alternatively, the display may be performed only during that period, and the priority of cursor display may be determined as appropriate. Further, instead of having a configuration in which the refresh period and the line access period are performed alternately, only one of them may be performed.

In addition, for example, a partial rewrite request circuit 1 compatible with a hard cursor may be used.
00 can also be configured as shown in FIG.

In FIG. 9, 121 is a difference register, and the 1θth
The old (current) position of the cursor (x,y) as shown in the figure
The absolute value 1y+-yd of the difference between the value y1 in the sub-scanning direction V of , and the value of the new position (xt, ygl in the same direction) is set.1
23 is a movement direction register, which is 0'' when y+>y*
, "1" is set when y+<y*.

125 is a cursor size register similar to the above;
The cursor height H and width W are set.

129 is a comparison control circuit that compares the contents of each register when executing the operation shown in FIG. 11 and outputs a load signal to the line address counter 133. 131 is a current line register in which the address of the line including the current position of the cursor is set. 1
33 is a line address counter, and the comparison control circuit 1
Current line register 13 according to the load signal of 29
1 and sequentially outputs a group of line addresses incremented from that value (line address) and outputs them to the selector 50. 137 is a request control circuit, which sends and receives signals REQ and ACK to and from the synchronization control circuit 39, and only for a period determined by the deviation between the old position (yl) and the new position (y2) and the cursor size (H). , outputs an enable signal to the line address counter 133 to execute the above-mentioned increment and line address output.

FIG. 11 is a flowchart for explaining an example of the operation of the configuration shown in FIG.

When there is a cursor movement instruction from the CPU II and settings are made to the difference register 121 and the movement direction register 123 (and the size register 125 if there is a change in the cursor size) (step Sl), the difference y+-y*l
It is determined whether the movement is less than 8, that is, less than the height of the cursor (step S3).

If the judgment is negative here, the current line register 13
The value of 1 (here, y+, which is the old position) is loaded into the line address counter 133 (step S5), and the signal RE
Send Q. Next, when the signal ACK is returned, the signal REQ is deactivated in step S9゜5ll), and the line address counter 133 is caused to perform a predetermined operation. next,
It is detected whether or not the address output for the line corresponding to the cursor height H has been completed, and if it has not been completed, step S
7 and repeats steps 37 to S13. In this process, as described above, the data in the video memory 41 for lines y to H is output to the image data synthesis circuit 200, while the new position of the cursor is held in the image data synthesis circuit 200. The cursor data is not merged, ie the cursor is erased from its old position.

Next, in step S15, the new position (y2) determined by the old position (y,), the result of the difference (ly+-ygl, and the movement direction) is set in the current line register 131,
In step SIT, the same processing as in steps 35 to Sll is performed for the H line (step 519). This will cause the cursor to be displayed at the new position.

On the other hand, if the deviation between the old and new positions is less than 8, the moving direction is first determined (step 521). Here, move the cursor to the bottom of the screen in the “+” direction, that is, yl<
In the case of y, the same processing as the above steps 87 to Sll is performed (step 523).

Next, it is determined whether this process has been completed for H+ly and -yd lines. This means that if I'+-yal<H, there is a line overlap between the old and new cursors, and the number of duplicate lines can be subtracted from the 2H line without accessing the same position for each H line (access for 2H lines). This is based on the fact that it is sufficient to perform access for the same number of lines (zu-(n-Iy+-yxl)"H"ly+-yal
). This allows line access to be performed with high efficiency, and in the process, it is ensured that the cursor at the old position is erased and the cursor is displayed at the new position. Note that after the end of that line, the same process as step S15 is performed, and y is stored in the current line register 13.
Set to 1 (step 527).

In the case of yl>)'z in step S21, first, y8 is set in the current line register 131 by the same process as step S15 (step 531),
By performing the same processing as steps S5 to Sll and S27 (steps S33 and 535), the cursor at the old position can be erased and displayed at the new position efficiently and reliably.

Incidentally, in the above explanation, the present invention has been explained with reference to an example corresponding to the hard cursor function, but examples of data to be synthesized with data in the video memory (composition data) include other data such as a video window or a message. There are superimpositions, overlays of some form, etc., and the present invention can effectively deal with these as well.

In these cases, for example, referring to the partial rewrite request circuit shown in FIG. 3, only when movement of the combining data occurs, loading of the combining data to the request address counter 109 at the old position and partial rewriting to the synchronization control circuit 39 is performed. When the request signal REQ is sent and the acknowledge signal A (J is supplied from the synchronization control circuit 39), counting permission is given to the request address counter 109, and the request address counter 109 has the same configuration as the cursor size register 105. The size set in the available size register (
While sequentially counting up the line address of the old position by the number of lines), the value is sent to the selector 50 side. Since the FLC has a memory property, the compositing data at the old location is immediately erased prior to updating the compositing data, specifically, the video memory 41 at that location, as described later. This is a group of line addresses that are used to redisplay only the data of .

Thereafter, the request control circuit 107 loads the value of the position register storing the new position into the counter 109 and sends the signal REQ, and in response to the input of the signal ACK, the request control circuit 107 performs the same process as above regarding the new position. An action (abbreviated as action A) is performed.

The line address group output at this time is used to display the synthesis data at the destination. In addition,
If there is no movement, this operation A may be repeated at a constant cycle faster than the refresh rate of the entire screen.

On the other hand, the same configuration and control mode as described above can be adopted for the image data synthesis circuit, and for example, it is sufficient to change the cursor RAM 211 in FIG. 4 to a frame buffer for displaying data for synthesis.

In addition, a circuit section 300 including these circuits 100 and 200
may be configured for multiple types of synthesis data. Further, such a circuit section 300 may be provided for each purpose, or a plurality of circuit sections 300 may be appropriately installed to switch the performance as a display control circuit.

Further, by taking advantage of the memory property of the FLCD element, the synthesis circuit may be configured to be able to handle a plurality of types of events, and also be able to switch between events.

Furthermore, apart from partial rewriting based on the address expanded to FIFO by CPH access (normal partial rewriting), some events (cursor movement display, video w
Insertion display of windows and messages.

Considering the idea of the present invention that partial rewriting is performed by generating an address related to the display position of data related to those events when an event (form overlay, etc.) occurs, the arrangement of the image data synthesis circuit 200 as described above is suitable. The presence or absence of this setting is optional.

In other words, even if display data related to an event is synthesized by an image data synthesis circuit, or if the CPU
Even if the display data related to the event is accessed on the video memory 41, by independently generating display commands and display addresses for those data, it is preferential or forced, unlike normal partial rewriting. This is because the display can be displayed quickly and accurately. for example,
When an operator inputs characters using a keyboard, etc., there is a limit to the character input speed, so partial rewriting should not be performed quickly (however, normal partial rewriting with constraints on execution period or FIFO capacity (as described above) is not recommended. Line access) is sufficient, and it is possible to maintain a constant refresh rate while performing partial rewriting, but such restrictions (for example, F
Sampling using IFO alone may have a detection limit depending on the FIFO capacity and execution period).

FIG. 12 is an example of a display control device according to another embodiment of the present invention based on such a concept.As shown in FIG. 6, this example has almost the same configuration as FIG. No circuit-related configuration is provided, that is, the circuit section 450, which can be attached integrally or separately to the interface main body 300, has only the partial rewrite request circuit 150.

FIG. 13 shows a configuration example of the partial rewrite request circuit 150, where 151 is a leading line register, 153 is a line number register, 157 is a request control circuit similar to the portion 107 in FIG. 3, and 159 is the same portion. This is a request address counter similar to 109.

In this example, immediately after changing the video memory 41, the CPU II sets the first line of data related to the event in the first line register 151, and sets the number of lines of the same data in the line number register 153. In response, the request control circuit 157 loads the value of the first line register into the request address counter 159, and the synchronization control circuit 3
The signal REQ is sent to 9. Then, the request address counter 159 starts counting operation by keeping the input of the signal A (J).
Sends line address groups for the number of lines set in .

That is, with such a configuration, it is possible to give top priority to data related to an event and quickly display all the data.

FIG. 14 shows yet another embodiment of the invention. here,
500 is a circuit unit for issuing a partial rewrite request in response to an event, and indicates an external circuit to the interface main body 300; 510A is an access address buffer coupled to the system bus 12 and storing addresses to be accessed by the CPU II; 510B is a work memory, and 520 is a digital signal processor (DSP). In this example, the accessed address is held and the DS
The rewriting priority is determined by P520, and lines with high priority are converted into appropriate line addresses of the FLCD interface, and this is requested to be output to the FLCD interface main body 300 as exadr. Also, the signal RE
Q. The sending and receiving of ACK is the same as above.

In this way, the partial rewrite request circuit according to the present invention can be integrated into the FLCD.
Used as an external circuit for the interface main body 300,
It can also be used as a tool for improving the performance of the interface main body 300, which can be used alone.

(The following is a blank space) [Effects of the Invention] As is clear from the above description, according to the present invention, partial rewriting in response to an event can be performed by, for example, setting the position, etc. for the host side CPU of the display device to perform partial rewriting. It becomes possible to do this on a priority basis.

As a result, when it is necessary to perform a quick partial rewrite such as display related to an event, the host side C
Restrictions on rewriting line access by PU (for example, FIF
(Detection limits depending on memory capacity and execution time) can be avoided, and this partial rewriting can be reliably executed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the overall configuration of an information processing device incorporating a display control device of the present invention, FIG. 2 is a block diagram of a display control device according to an embodiment of the present invention, and FIG. 4 is a block diagram showing an example of the configuration of the image data synthesis circuit; FIG. 5 is an explanatory diagram for explaining a cursor as an example of data to be synthesized; FIG. 6 is an explanatory diagram of signals output by the FLCD main body according to this example, FIGS. 7 and 8 are timing charts for explaining two examples of the operation of this example device, and FIG. 9 is a partial rewrite request circuit. FIG. 1O and FIG. 11 are explanatory diagrams and flowcharts of operation examples thereof; FIG. 12 is a block diagram of a display control device according to another embodiment of the present invention; FIG. 13 is a block diagram showing an example of the configuration of the partial rewrite request circuit, and FIG. 14 is a block diagram of a display control device according to still another embodiment of the present invention. 11...cpu. 12... System bus, 13... Main memory, 14... DMA controller, 15... LAN interface, 16... LAN, 17... I10 device, 18... Hard disk device, 19. ...Floppy disk device, 20...Disk interface, 21...Printer, 22...Printer interface, 23...Keyboard, 24...Mouse, 25...Interface, 26...FLCD ( FLCD display), 26
a... Temperature sensor, 27... FLCD interface, 31... Address bus driver, 32... Control bus driver, 33, 43.4
4... Data bus driver, 34... Sampling counter, 35... Address selector, 36... FIFO (A) memory, 37... FIFO (B) memory, 38... Address counter, 39 ...Synchronous control circuit, 40...Memory controller, 41...Video memory, 42...Driver receiver, St, S2...Switch, 50...Selector, 100.150...Partial rewriting Request circuit, 101, 10
2.105.121.123.125.131...Register, 107.137...Request control circuit, 109, 133...Address counter, 200...
Image data synthesis circuit, 201.205...Register, 207...Sub-scanning comparison circuit, 209...Main-scanning counter, 211...Cursor RAM. 213...Logic synthesis circuit. Figure 10 Figure 1OA Figure 14

Claims (1)

[Scope of Claims] 1) In a display control device for a display device capable of updating the display state of only display elements related to display changes, display data storing display data corresponding to each of the display elements; storage means; address output means for outputting the address of the display element associated with the event in accordance with the setting of display element information associated with the event; and reading from the display data storage means based on the address output from the address output means. A display control device comprising: data transfer means for transferring display data to the display device. 2) A display control device for a display device capable of updating the display state of only display elements related to display changes, comprising: a display data storage means for storing display data corresponding to each of the display elements; When such display element information is set, an event display requesting means for requesting an update of the display state of the display element related to the event; and, in response to a request by the event display requesting means, access to the display data storage means by the request. access control means for permitting the update of the display state based on priority; address output means for outputting the address of the display element related to the event in response to permission by the access control means; and output from the address output means. A display control device comprising: data transfer means for transferring display data read from the display data storage means to the display device based on an address. 3) The display control device according to claim 1 or 2, wherein the display element information is an address of a predetermined display element to be changed and a value related to the total number of display elements to be changed.