JP3043376B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly, to a display updated by, for example, applying an electric field using a ferroelectric liquid crystal as an operation medium for updating a display. The present invention relates to a display control device for a display device having a display element capable of holding a state.

[Related Art] In general, a display device is used as an information display means for performing a visual expression function of information in an information processing system or the like, and a CRT display device is widely known as such a display device. .

In the display control of the CRT display device, the writing operation of the system side CPU to the video memory as the display data buffer of the CRT side and the reading and display operations of the display data from the video memory by the CRT controller of the CRT side are independent of each other. Executed.

In the case of CRT display control as described above, the operation of writing display data to a video memory for changing display information and the operation of reading and displaying display data from the video memory are independent of each other. The system-side program does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, a CRT, in particular, requires a certain length of the display screen in the thickness direction, and therefore has a large overall volume, making it difficult to reduce the size of the entire display device. This also impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

As a supplement to this point, a liquid crystal display (hereinafter, referred to as LCD) can be used. That is, according to the LCD,
The whole display device can be reduced in size (especially thinner). Among such LCDs, there is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of the above-described ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric Liquid Crystal). The problem is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the molecules of the elongated FLC in the FLCD are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and the electric field is removed. However, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLCD has memory properties. Details of such FLC and FLCD are described, for example, in Japanese Patent Application No. 62-76357.

As a result, when driving an FLCD, unlike a CRT or other liquid crystal display, there is time margin in the cycle of continuous refresh driving of the display screen, and separately from the continuous refresh driving. In addition, it becomes possible to perform partial rewrite driving for updating the display state of only the portion corresponding to the change on the display screen.

[Problems to be Solved by the Invention] Therefore, if an appropriate and timely partial rewriting drive can be performed in the FLCD, the advantage of the FLCD will be further increased.

In addition, such a display device of an information processing system
The ability to use FLCDs compatible with CRTs would increase the flexibility and value of the system.

From the above viewpoint, it is possible to consider a display control mode in which the predetermined partial rewriting is prioritized over the partial rewriting of other display information. A display example of this is a display of cursor movement, and this display needs to change its display state in real time (perceptually) according to the operation of the mouse or the like by the operator.

If such a display is defined as an event, a configuration in which partial rewriting for the event is performed in accordance with the priority order among a plurality of events is described in, for example, Japanese Patent Application Laid-Open No. 2-93 by the present applicant.
No. 491. However, in the display control of this configuration, the information processing system provides the display device with information for identifying this processing at the time of partial rewriting relating to the event. For this reason, the control program of the information processing system using such a display device is described above.
This is significantly different from a control program for an information processing system using a CRT as a display device. As a result, FL
It becomes difficult to configure an information processing system compatible with CD and CRT.

On the other hand, when an FLCD is used as a display device of an information processing system while having compatibility with a CRT, an essential problem arises in its configuration. That is, the CPU on the system side only transfers the display data and the address for the display update to the display device side. Therefore, there arises a problem of how to determine the partial rewriting relating to the event from other partial rewriting, and a problem of how to prioritize the partial rewriting relating to the event as a result of this determination.

The present invention has been made in view of the above problems,
Certain events can be caught easily and reliably, and can be displayed prior to other partial rewriting displays.In addition, compatibility with the CRT can be maintained without significantly changing the software on the information processing system side. It is an object of the present invention to provide an FLCD display control device having the same.

[Means for Solving the Problems] For this reason, according to the present invention, in a display control device of a display device capable of updating a display state of a display element related to display change, an address of the display element related to the change is stored. Address storage means, display data storage means for storing display data corresponding to each of the display elements, and display data read from the display data storage means based on an address output from the address storage means. Data transfer means for transferring to the display device, event detection means for detecting a predetermined event address from addresses transferred to the display control device when displaying on the display device, and the event detection means When detecting, the address stored in the address storage means within a predetermined period based on the detection time point And an address memory control means for outputting the address before the address stored in the address storage means before the detection time.

[Operation] According to the above configuration, when a predetermined event is displayed, when the host CPU of the display device accesses the address of the font data related to the event in the work area in VRAM, for example, this is detected. The address stored in the address storage means after the detection is output with priority and a display based on this address is made.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an FLC display device including a display control device according to an embodiment of the present invention as a display device for various characters, image information, and the like.

In the figure, reference numeral 11 denotes a CPU that executes control of the entire information processing system, 13 denotes a line memory that stores a program executed by the CPU 11 and is used as a work area for this execution, and 14 denotes a main memory that does not pass through the CPU 11. Transfers data between the memory 13 and various devices that make up the system
DMA controller (Direct Memory Access Controller,
DMAC). 15 is LAN (local area network) such as Ethernet (by XEROX) 16
LAN interface between the system and this system, 17 is ROM, SRA
It is an input / output device (hereinafter referred to as I / O) having an M, RS232C system interface and the like. Various external devices can be connected to the I / O 17. Reference numerals 18 and 19 denote a hard disk device and a floppy disk device, respectively, as external storage devices, and reference numeral 20 denotes a disk interface for performing signal connection between the hard disk device 18 and the floppy disk device 19 and the present system. Reference numeral 21 denotes a printer which can be constituted by an ink jet printer, a laser beam printer, or the like capable of recording at a relatively high resolution, and reference numeral 22 denotes a printer interface for performing signal connection between the printer and the present system. 23 is a keyboard for inputting character information such as various characters, control information, etc., 24 is a mouse as a pointing device,
Reference numeral 25 denotes a key interface for performing signal connection between the keyboard 23 and the mouse 24 and the present system. 26
Is a FL as a display control device according to an embodiment of the present invention.
FL whose display is controlled by the CD interface 27
It is a C display device (hereinafter, also referred to as FLCD), and has a display screen using the above-described ferroelectric liquid crystal as its display operation medium.
Reference numeral 12 denotes a system bus including a data bus, a control bus, and an address bus for connecting signals between the above-described devices.

In the information processing system including the various devices described above connected, the user of the system generally performs an operation while corresponding to various information displayed on the display screen of the FLCD 26. That is, the external devices connected to the LAN 16, the I / O 17, the hard disk 18, the floppy disk 19, the keyboard 23,
Characters and image information supplied from the mouse 24, as well as operation information relating to the user's system operation stored in the main memory 13 are displayed on the display screen of the FLCD 26. The user can edit the information while viewing this display. Perform an instruction operation for. Here, each of the above various devices
A display information supply unit is configured for the FLCD 26.

FIG. 2 is a block diagram showing details of the FLCD interface 27.

In the figure, 31 is an address bus driver, 32 is a control bus driver, 33, 43, 44, and 45 are data bus drivers, each of which is connected to each bus of the system bus 12. Absolute address data when the CPU 11 accesses a system-side video RAM (hereinafter, also referred to as a VRAM) for rewriting display contents is transmitted to an access monitor circuit 50 described later with reference to FIG. Given. The absolute address input to the access monitor circuit 50 is converted into a display line address, and the write signal from the access monitor circuit 50 and the FIFO (A) memory 36 or the FIFO (B) memory are switched according to the switching of the first switch S1. It is selectively provided to 37 and stored therein. FIFO
(A) 36 and FIFO (B) 37 are FIFO (First In First Out) memories from which data is read in the order of writing, and the line addresses written into these FIFO (A) 36 and FIFO (B) 37 Data is selectively read according to the switching of the second switch S2. The access monitor circuit 50 determines address data for the CPU 11 to access the memory 41 during a predetermined period, and when a different address is accessed, outputs the data to the sampling counter 34, and the counter 34 counts the data. This count value is given to the synchronization control circuit 39, and can be used to determine a ratio between partial rewriting and refresh driving described later.

The absolute address is also input to the address selector 35 so that the CPU 11 accesses the video memory 41.

The address data read from the FIFO (A) 36 or the FIFO (B) 37 and the video memory 41 similarly.
The address data from the address counter 38, which will be described later, is used to selectively access the address selector 38 according to the switching of the third switch S3.
35 input to one input. Address counter 38
Is to advance the line address of the video memory 41 by "1", and generate address data for refresh driving the entire display screen, and the generation timing of the address data is controlled by the synchronization control circuit 39. .
The synchronization control circuit 39 also generates a switching control signal for the switches S1, S2, and S3 and a data transfer request signal to the memory controller 40 described later. The timing of the signal generation by the synchronization control circuit 39 and the switches S1, S2
The switching timing of S3 and S3 is controlled according to the horizontal synchronization signal (HSYNC) generated by the FLCD 26 every time display driving for one line of the display screen is performed.

The control signal from the CPU 11 is given to the memory controller 40 via the control bus driver 32,
The memory controller 40 controls the address selector 35 and a video memory 41 described later according to the control signal. The memory controller 40 arbitrates a memory access request signal output from the CPU 11 when rewriting data in the video memory 41 and a data transfer request signal output from the synchronization control circuit 39 when displaying data in the video memory 41. In response, the output of the access selector 35 is switched, and one of the two address data supplied to the input section of the address selector 35 is selected and supplied to the video memory 41.

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads out display data via a data bus driver 33. The display data written to the video memory 41 is transmitted to the FLCD via a driver receiver 42.
Read out to 26 and displayed. Also the driver receiver
Reference numeral 42 designates a synchronization signal from the FLCD 26 to the synchronization control circuit 39.

In addition, data for setting the ratio between partial rewriting and refresh driving, which will be described later, and the like are provided to the synchronization control circuit 39 via the data bus driver 43.

The FLC panel of the FLCD 26 is provided with a temperature sensor 26a for detecting the temperature, and an output signal of the temperature sensor 26a is transferred to the CPU 11 via the data bus driver 44.

In the above configuration, when the CPU 11 changes the display, the video memory corresponding to the rewriting of the desired data
41 address signals are given to the memory controller 40,
Here, the memory access request signal of the CPU 11 and the synchronization control circuit 3
Arbitration with the data transfer request signal from 9 is performed. Then, when the CPU access side obtains the right, the memory controller 40 switches the address selector 35 to select the address from the address driver 31 as the address given to the video memory 41, that is, the address currently being accessed by the CPU 11. I do. At the same time, a control signal from the memory controller 40 to the video memory 41 is generated, and reading and writing of data via the data bus driver 33, that is, data rewriting of the video memory 41 is performed. At this time, the address data accessed by the CPU 11 is stored in the FIFO (A) 36 or the FIFO (B) 37 via the access monitor circuit 50 and the switch S1, and is used when transferring display data described later. As described above, the display data access method viewed from the CPU 11 is the same as that of the above-described CRT.

On the other hand, when reading data from the video memory 41 and transferring this data to the FLCD 26 for display, a data transfer request is issued from the synchronization control circuit 39 to the memory controller 40, and the address to the video memory 41 is set according to the switching of the switch S3. The address on the address counter 38 or the FIFO side is selected by the address selector 35 after passing through the address conversion circuit, and the control signal for data transfer is generated by the memory controller 40, so that the memory cell of the video memory 41 The data of the corresponding address line is transferred to the shift register, and is output to the driver 42 according to the control signal of the serial port.

As described above, the synchronization control circuit 39 refreshes the entire screen based on the horizontal synchronization signal HSYNC from the FLCD 26 according to the embodiment of the present invention.
Generates a timing to generate a partial rewrite cycle for rewriting the accessed line. here,
The full refresh cycle refers to a cycle in which lines constituting the display screen are sequentially driven one by one.
In this case, a line to be accessed is determined according to an address sequentially incremented by the address counter 38 as described later. The access line partial rewrite cycle is to rewrite a line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in the present example, basically, the operation of refreshing the entire screen of the FLC display 26 and the operation of rewriting the partial line accessed by the CPU 11 to change the display content are described. The operations are alternately performed in a time-division manner. Further, a repetition period of the operations and a time ratio of the operations within one period can be set.

With reference to FIG. 3, a description will be given of a basic operation of the present example in which a refresh operation and a line rewrite operation are alternately performed in a time-division manner. Here, an example is shown in which a refresh cycle is performed in units of four lines and a rewrite cycle of an access line is performed in units of three lines.

In FIG. 3, REE / ▲ ▼ is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. When “1”, the full refresh cycle is performed, and when “0”, the access line is rewritten. Indicates a rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example, T _a : T _b
= 4: 3, but an optimal value can be selected depending on the required refresh rate and the like. That is, it is possible to increase the refresh rate by increasing the ratio of T _a, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b.

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (the state A / = “1” of the switch S1), the line accessed by the CPU 11 Are sampled and stored in the FIFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / = "0"), the line address accessed by the CPU 11 is stored in the FIFO (B) 37. Switch S2 is FI
When connected to the FO (A) 36 side (state A / = of switch S2)
"1"), the address stored in the FIFO (A) 36 is output, and when the switch S2 is connected to the FIFO (B) 37 side (A /
= “0”), and the address stored in the FIFO (B) 37 is output.

When one refresh of the entire screen is completed and the FLCD 26 outputs the vertical synchronizing signal VSYNC or when the carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle is Return to line 0. As described above, the address counter 38 outputs “1”, “2”, and “2” according to the synchronization signal generated each time the synchronization control circuit 39 counts the horizontal synchronization signal HSYNC.
The counter counts up sequentially to "3".
Is output in accordance with the parameters M and N input to the synchronization control circuit 39 via the data bus driver 43. That is, the parameters M and N determine the ratio between the refresh cycle and the partial rewrite cycle in a certain period, and the synchronization signals are output for the number of lines in the refresh cycle determined by the parameters, and are not output during the partial rewrite. On the other hand, when the address of the line L1, L2, L3 is accessed by the CPU 11, if the switch S1 is connected to the FIFO (A) 36 at this time,
1, L2, L3 addresses are stored here, then switch S
When 2 is connected to the FIFO (A) 36, the addresses of L1, L2 and L3 are output from here, and L1, L2 and L3 are selected as output lines. Here, the switching signal of the switch S3 is given as REE / ▲ ▼ from the synchronization control circuit 39, and REE / ▲
In the line access cycle in which ▼ is “1”, the output is switched from the FIFO (A) and FIFO (B) outputs as the output line address. When REE / ▲ ▼ becomes “1”, the switch S3 is switched to the address counter 38 side, and the address counter 38 sequentially counts up according to the synchronization signal output by the synchronization control circuit 39 in synchronization with the horizontal synchronization signal HSYNC. , And the refresh operation is performed from the line following the previous cycle. In FIG. 3, for example, L3
After the line output of “4”, “5”,
Lines “6” and “7” are output. In the same manner, the above operation is repeated, except that two FIFOs are prepared.
This is because, on the one hand, sampling the address accessed in the memory and simultaneously outputting the sampled address on the other hand can be performed efficiently and consistently. That is, the address sampling period is from the start of output of the access line of the other FIFO to the end of the refresh cycle, and after the end of the refresh cycle, when the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started. At the same time, the address sampling period of the other FIFO is started.

As described above, in the basic operation of this example, the refresh cycle and the line rewriting cycle are alternately repeated, and in FIG. 3, the repetition cycle is set to 7 lines as one unit and T _a : T
_b = 4: has been described as 3, in this example further type of data being environmental conditions and displays such as temperature, or even T _a and the refresh rate or the like which is required according to the difference of the display device material FLCD T The ratio with _b can be changed.

By the way, the partial rewriting described above makes it possible to update the display state of only the part corresponding to the change on the display screen.
Some operations are desirably performed preferentially, such as cursor movement. This is because the movement of the cursor needs to be displayed in real time in accordance with the movement of the mouse or the like operated by the operator. On the other hand, for example, the display of input characters from the keyboard is not necessarily a key operation. It doesn't have to be real-time.

Therefore, in one embodiment of the present invention, such a predetermined partial rewrite is preferentially performed by using the access monitor circuit 50 shown in FIG. Hereinafter, priority partial rewriting will be described with reference to FIGS. 4 to 9, taking display of cursor movement as an example.

FIG. 4 is a block diagram showing details of the access monitor circuit 50 shown in FIG. 2, and FIG. 5 is a FIFO diagram shown in FIG.
(A) is a detailed timing chart, FIG. 6 is a flowchart showing a processing procedure by the CPU 11 at the time of cursor movement, and FIG. 7 (A) is a schematic diagram of a VRAM developed in the main memory 13 shown in FIG. 1, for example. FIG. 7 (B) shows this
Schematic diagram showing correspondence of VRAM addresses, FIG. 8 (A)
And (B) are schematic diagrams showing cursor mask data and cursor font data, respectively, and FIG. 9 is a schematic diagram showing a display example of a cursor.

In FIG. 4, reference numeral 501 denotes a comparison circuit which outputs a match signal when the access address of the CPU 11 input via the address driver 31 matches the event trigger address stored in the first register 46A. The event trigger address means a predetermined address that the CPU 11 always accesses when moving the cursor.

An address conversion circuit 502 converts an absolute address accessed by the CPU 11 into a line address. That is,
The address input to the access monitor circuit 50 via the address bus driver 31 is an absolute address in the system-side VRAM as shown in FIG. 7 (B), and is a display for transferring this to the FLCD 26. Convert to line address. The address conversion circuit shown in FIG.
47 is provided for the purpose of returning the converted display line address to an address for accessing the video memory 41.

A comparison circuit 503 determines whether the access address of the CPU 11 is in the display area or the work area shown in FIG. 7A or 7B, and determines whether the access address is in the display area. Is output when it is.

Here, as shown in FIG. 7 (B), the address of the system-side VRAM is, for example, an absolute address 0 to 159.
In the figure, 7 addresses in the horizontal direction and 11 lines in the vertical direction correspond to the FLCD interface 27.
Display area corresponding to the video memory 41 of FIG. That is, the data in this display area is displayed on the FLCD. On the other hand, portions other than the display area in the VRAM include a right portion having addresses of 7 to 9, 17 to 19,..., 107 to 109, and a lower portion corresponding to addresses 110 to 159. Of these, the lower part is usually used as a work area for display control.

As is clear from the above, when the CPU 11 accesses the VRAM on the system side during display control, it accesses not only the display area but also the work area. As a result, the access address of the CPU input to the access monitor circuit 50 includes the address of the work area. For this reason, the input address is determined in the comparison circuit 503, and only when this address is in the display area of the VRAM, it is written into the FIFO (A) 36 or the FIFO (B) 37 as described later. To As a configuration of the comparison circuit 503, for example,
The upper two digits of the VRAM address shown in FIG.
What is necessary is just to make the comparison circuit 10 or less. In this case, when the upper two digits of the address input to the comparison circuit 503 are 10 or less, it is output that the address is a display area address.

Referring again to FIG. 4, reference numeral 505 denotes a latch comparison circuit;
Upon receiving the output indicating that the address data is the address data of the display area from the comparison circuit 503, the address data is fetched from the address conversion circuit 502 and compared with the previously fetched and latched address data. If the comparison does not match, the newly fetched address data is latched and output to the FIFO memory 36 (37). At the same time, an output indicating access to a different line is output. This prevents continuous access to overlapping lines in the video memory 41. Note that the output indicating that the above-mentioned access to a different line is made by the sampling counter
The sampling counter 34 counts this output.

Reference numeral 504 denotes a FIFO control circuit, which outputs a reset signal in response to the coincidence signal from the comparison circuit 501, and sets the line pointer of the FIFO memory 36 (37) to the head of the FIFO memory. As a result, address data to be subsequently input to the FIFO memory is stored from the beginning, and is output first when output. The FIFO control circuit 504 also responds to an AND between the output from the comparison circuit 503 indicating that the display area is displayed and the output from the latch comparison circuit 505 indicating that the access is to a different line.
A write signal is output to the FIFO memory 36 (37), and writing of address data input through the latch comparison circuit 505 to this memory is permitted.

The operation of the access monitor circuit 50 described above will be described with reference to the timing chart of the FIFO (A) shown in FIG. When the event of cursor display movement occurs, specifically, when the CPU 11 accesses the address of the position A of the cursor font data stored in the work area shown in FIG. 7A, the first register 46A stores Since this address is stored, the comparison circuit 501 outputs a match signal. Thereby, when the CPU 11 accesses the address of the display area of the VRAM after accessing the position A,
The addresses are sampled (written) in the FIFO (A) 36, and these addresses are output first at the next output timing.

On the other hand, a processing procedure at the time of moving the cursor by the CPU 11 at this time will be described mainly with reference to FIGS. 6 and 7 (A).

When the cursor movement process is started, in step S61, V
The image at the old position of the cursor saved in the image storage area of the work area of the RAM is written to the designated position of the display area (FIG. 7 (A), the same applies hereinafter), and the new position of the cursor is set at step S62. Is saved in the image storage area (in the figure). Next, in step S63, an AND operation is performed between the retracted image and the cursor mask data as shown in FIG. 8A which is stored at a predetermined position in the work area, and is written at a predetermined position in the work area. (In the figure). In this image, the portion corresponding to “1” of the cursor mask data shown in FIG. 8A is the same as the background color, and the portion corresponding to “0” is white. Next, in step S64, an OR between the image synthesized in step S63 and the cursor font data stored in a predetermined area of the work area as shown in FIG. 8 (B) is taken and written in a predetermined position of the work area ( In the figure),
In step S65, the image obtained in step S63 is written at a new position in the display area (in the figure). This written image is
As shown in FIG. 9, a black cursor is displayed in a cursor that is outlined from the background. this is,
As shown in FIGS. 8A and 8B, the size of the cursor mask data is larger than the size of the cursor font data.

In the cursor movement process by the CPU 11 described above, when synthesizing the cursor font data in step S64, the CPU 11 accesses the position A of the cursor font data shown in FIG. 7A. Since this address is stored in the first register shown in FIG. 4 as the event trigger address, when the CPU 11 accesses the position A, the comparison circuit 501 outputs a coincidence signal, and as described above with reference to FIG. The memory 36 (37) is reset. Thereafter, when the CPU 11 accesses the display area for writing the composite image of the cursor in step S65, the addresses at the time of writing are stored in the FIFO memory 36 (37).

By the way, in the system shown in FIG. 1, for example, when executing a predetermined application program, if this program is stored in an external storage device such as a disk, the program must be transferred to the memory of the system. This causes a change in the correspondence between the data in the memory and the physical address (absolute address in the above description). In such a case, since the absolute address of the cursor font data used as the event trigger address also changes, it must be reset in the first register 46A.

FIG. 10 is a flowchart showing the processing at this time. That is, when any application program is started, the operation of this program is performed in step S101. At this time, step S103 always checks for a bus error in this operation. In step S103, for example, if the activated program is not in the memory on the system side, a bus error occurs.Next, in step S104, it is determined whether or not this bus error has occurred due to the absence of the program in the memory. In the case of a negative determination, it is determined that there is an abnormality in the system, and the process proceeds to a bus error processing routine in step S110. If it is determined that the application program is not in the memory, it is determined in step S105 whether or not a free area of the system-side memory is sufficient to transfer the application program in an external storage device such as a disk. If it is determined that it is not enough, step S1
After transferring low-priority programs to disk in 06, or directly if free space is sufficient,
Proceed to S107, where the application program is transferred from the disk to the system-side memory. Then, step
In S108, mapping in the memory is performed. As a result, the correspondence between the virtual address in the memory of the entire system and the physical address in the memory is determined. Based on this, in step S109, the position A of the cursor font data
Is set in the register 46A.

In the above-described embodiment, the address data of the line to be partially rewritten is stored in the FIFO memory. However, in this configuration, when the CPU accesses a predetermined event trigger address, the address data stored in the FIFO memory is read. Will not be output. On the other hand, by using, for example, an SRAM as an address data storage medium, after outputting a priority partial rewriting address,
It is also possible to output the previously stored address data and rewrite this portion.

FIG. 11 is a block diagram showing the configuration of the FLCD interface in such a case. In FIG. 11, 145 and 146 are SRAM (A) and SRAM (B), respectively, and 147 is SR
It is an address controller that controls write and read addresses in AM145 and 146. Reference numeral 60 denotes an access monitor circuit having substantially the same configuration as the access monitor circuit 50 shown in FIG. 2, and 148 denotes an SRAM control circuit. As will be described later, a control signal from the access monitor circuit 60 and synchronization control timing of the address data output by the address controller 147 in response to such a signal to the switch S ₃ from the circuit 39, i.e. the data in SRAM145,146 writing, controls the timing of reading.

FIG. 12 is a block diagram showing a detailed configuration of the access monitor circuit 60 and the address controller 147. The access monitor circuit 60 includes a comparison circuit 601, an address conversion circuit 602,
It has a comparison circuit 603 and a latch comparison circuit 605, and each of these circuits performs the same operation as each of the circuits shown in FIG. SR
The AM control circuit 148 outputs an event occurrence signal in accordance with the coincidence signal from the comparison circuit 601, and outputs an address indicating a display area address from the comparison circuit 603 and a latch comparison circuit.
A write signal is output when there is an output indicating access to a different line from 605, and a signal from the synchronization control circuit 39 is output.
And it outputs a read signal in synchronism with the S _3. Also, SRAM145,14
A sampling period signal for managing the period of sampling to 6 is output.

In the address controller 147, an address control circuit 1471 receives a control signal from the SRAM control circuit 148, and receives an SRAM address counter 1474 and a register 1414.
Control 72. SRAM address counter 147
Each time address data is written to (146),
This is a counter that counts up each time address data is read from (146), and this count-up is performed by an enable signal from the address control circuit 1471. Register 14
Reference numeral 72 stores the count value of the counter 1474 when an event occurs and when sampling (address data writing) to the SRAM 145 (146) is completed. Reference numeral 1473 denotes a comparison circuit which, when the count value at the end of sampling stored in the register 1472 matches the content of the counter 1474, outputs an output to that effect to the address control circuit 1471.

The operation of the address controller 147 described above will be described with reference to FIG.

At the time of writing (sampling) to the SRAM 145 (146),
At the start, the address control circuit 1471 outputs a clear signal to set the address (count value) of the address counter 1474 to "0" (FIG. 13). After that, the SRAM control circuit 148
The address control circuit 1471 outputs an enable signal for each write signal from the CPU, sequentially counts up the count value of the address counter 1474, and when the event generation signal is output, the address counter 1474 at this time is stored in the register 1472 accordingly. Is stored (in the figure). Thereafter, similarly, an enable signal is output according to the write signal, and the count value of the address counter 1474 is counted up. After the above event occurrence signal is output, SR
The address data stored in the address indicated by the count value of the address counter 1474 in the AM 145 (146) is, for example, data indicating the movement of the cursor as shown in the above-described embodiment. When the above operation is repeated and the sampling period ends, the address control circuit 1471 stores the address counter 14 in the register 1472 at that time.
The count value of 74 is stored, and the count value at the time of event occurrence stored in the register 1472 is used as the count value of the address counter 1474 (in the figure).

At the time of reading following the sampling period, the address control circuit 1471 outputs an enable signal for each read signal from the SRAM control circuit 148, and counts up the count value of the address counter 1474. As described above, since the reading is started from the address at the time when the event occurs (in the figure), the partial rewriting display such as the movement of the cursor is preferentially performed. Thereafter, similarly, an enable signal is output for each read signal to count up the count value, and when the count value matches the count value at the end of sampling stored in the register 1472 (in the figure), the address control circuit 1471 outputs a clear signal, sets the count value of the address counter 1474 to “0”,
The address data previously stored in 145 (146) is read out (in the figure).

In each of the above-described embodiments, the display in which partial rewriting is preferentially performed, that is, an example in which the cursor is moved as an event has been described. However, it is needless to say that the event is not limited to this. Hereinafter, in the system shown in FIG. 1, a series of processes performed by the user operating the keyboard 23 and the mouse 24 while viewing the display on the FLCD 26 will be described as an example.
Some of the events will be described with reference to the display examples of the FLCD 26 shown in FIGS. 14 (A) to (I). Note that “(event)” will be described later in the description of the display related to the event.

FIG. 14 (A) is an initial screen showing a state where nothing is performed after power-on.

Fig. 14 (B) Double-click the cabinet icon with the mouse (1 in the figure).

As a result, the cabinet window opens (event), and the window indicating the disk area closes (event).

Fig. 14 (C) One of the binders in the cabinet is clicked with a mouse (2 in the figure).

As a result, the clicked binder reverses black and white (event).

FIG. 14 (D) A certain document file is opened (3 in the figure).

FIG. 14 (E) Specify a range, and move the vertical cursor with the mouse or arrow keys. As a result, the portion of the sentence whose range is specified is inverted between black and white (4 in the figure) (event).

FIG. 14 (F) In the screen shown in FIG. 14 (E), click on the place where “Heading Form” is written in the lower left (5 in the figure) with the mouse or use the corresponding function key F1. push. As a result, the menu screen at the bottom of the screen changes (6 in the figure) (event).

FIG. 14 (G) shows a state where another document file is opened.

FIG. 14 (H) Click on the print portion at the top of the document window shown in FIG. 14 (G) with the mouse (7 in FIG. 14).
As a result, a sub window for printing is displayed (event).

FIG. 14 (I) When an instruction is given to print with the mouse, an error occurs and an error message is displayed (event).

[Effects of the Invention] As is apparent from the above description, according to the present invention, when a predetermined event is displayed, the CP on the host side of the display device is displayed.
When U accesses the address of the font data relating to the above event in the work area in VRAM, for example, this is detected, and the address stored in the address storage means after the detection is output with priority, and the display based on this address is displayed. Done.

As a result, a specific event to be displayed in real time can be reliably captured and displayed promptly. Further, the FLCD provided with the display control device of the present invention can be made compatible with the CRT without significantly changing the software on the information processing system side.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to an embodiment of the present invention. FIG. 2 is an FLCD as a display control device shown in FIG.
FIG. 3 is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2, and FIG. 4 is a detailed configuration of the access monitor circuit shown in FIG. FIG. 5 is a timing chart for explaining the operation of the FLCD interface shown in FIG. 2 according to an embodiment of the present invention. FIG. 6 is a cursor movement according to an embodiment of the present invention. 7 (A) is a conceptual diagram of the system-side VRAM for explaining the cursor movement, and FIG. 7 (B) explains the address correspondence between the display area and the work area in the VRAM. FIGS. 8A and 8B are conceptual diagrams of a VRAM for performing cursor movement and cursor mask data for moving the cursor, respectively. FIG. 9 is a schematic diagram showing a display example of the cursor, and FIG. 10 is a predetermined diagram for explaining setting of an event trigger address in a register according to an embodiment of the present invention. FIG. 11 is a block diagram showing the configuration of an FLCD interface according to another embodiment of the present invention. FIG. 12 is an access monitor circuit, an SRAM control circuit, and an address controller shown in FIG. FIG. 13 is a conceptual diagram of an SRAM for explaining the operation of the FLCD interface according to another embodiment of the present invention, and FIGS. FIG. 4 is a front view showing a display example of an FLCD for showing some examples of an event trigger according to the embodiment of the present invention. 11… CPU, 12… Address bus, 13… Main memory, 14… DMA controller, 15… LAN interface, 16… LAN, 17… I / O device, 18… Hard disk device, 19… ... Floppy disk drive, 20 ... Disk interface, 21 ... Printer, 22 ... Printer interface, 23 ... Keyboard, 24 ... Mouse, 25 ... Key interface, 26 ... FLCD (FLCD display), 26a ... Temperature sensor, 27 FLCD interface, 31 Address bus driver, 32 Control bus driver, 33, 43, 44, 45 Data bus driver, 34 Sampling counter, 35 Address selector, 36 ... FIFO (A) memory, 37 ... FIFO (B) memory, 38 ... address counter, 39 ... synchronous control circuit, 40 ... memory controller, 41 ... video memory, 42 ... Driver receiver, S1, S2, S3 ... switch, 46A, 46B ... register, 47 ... address conversion circuit, 50, 60 ... access monitor circuit, 145 ... SRAM (A), 146 ... SRAM (B) 147… Address controller 148… SRAM control circuit 501 601 Comparison circuit 502 602 Address conversion circuit 503 603 Comparison circuit 504 FIFO control circuit 505 605 Latch comparison circuit 1471 Address control circuit, 1472 …… Register, 1473 …… Comparison circuit, 1474 …… SRAM address counter.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G09G 5/00-5/40 G09G 3 / 18,3 / 36 G02F 1/133 505-535 G02F 1/133 545-580 G06F 3/14-3/153

Claims (2)

(57) [Claims] 1. A display control device for a display device capable of updating a display state of a display element according to a change in display, an address storage means for storing an address of the display element according to the change, Display data storage means for storing display data corresponding to each; data transfer means for transferring display data read from the display data storage means to the display device based on an address output from the address storage means; An event detecting means for detecting a predetermined event address from addresses transferred to the display control device when displaying the display device, and when the event detecting means detects the event address, The address stored in the address storage means within a predetermined period is replaced with the address before the detection time. Display control device comprising an address memory control means for output before the address stored in 憶 means, that comprises a. 2. The display control device according to claim 1, wherein the event address is an address of a font related to the event display.