JPH0470010A - Plo circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of phases of both input and output clocks to the change of the input clock frequency at application of an input clock and at the same time to prevent a big change of the output clock frequency at interruption of the input clock by fixing the input voltage of a voltage control oscillator at a fixed level when an interruption state of the input clock is detected. CONSTITUTION:A phase comparator 1 is provided to output a pulse having the width proportional to the phase difference between an input clock 10 and a feedback clock 20 together with an LPF 2 which outputs the voltage containing a smoothed pulse inputted from the comparator l, and an amplifier 3 which amplifies the voltage inputted from the LPF 2. Furthermore a voltage control oscillator 4 is added to output the clock 20 according to the output voltage supplied from the amplifier 3 together with a detection circuit 5 which changes the input voltage of the oscillator 4 into the set voltage VFR of a power supply 7 via a switch 6 when the clock 10 is interrupted. Thus a big difference of frequencies can be reduced between the clock 20 and the clock 10 which is usually applied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLO circuit, and particularly to a PLO circuit that stabilizes the operation of a voltage controlled oscillator.

[Conventional technology]

As shown in FIG. 2, the conventional PLO circuit includes a phase comparator 1 that receives an input clock 10 and an output (feedback) clock 20, and a low-pass filter that receives the output of the phase comparator 11. 12, an amplifier 13 to which the output signal of the low-band r-wave generator 12 is input, and a voltage controlled oscillator 14 to which the output signal of the amplifier 13 is input.

Next, to explain the operation, the clock phase difference between the two inputs of the phase comparator 11 is maintained so that the voltage required to obtain the output clock 20 having the same frequency as the input clock 10 is generated at the input of the voltage controlled oscillator 14. As a result, an output clock 20 having a frequency matching the frequency of the input clock 10 is obtained.

Therefore, in order to change the frequency of the output clock 20 according to the change in the frequency of the input clock 10, by changing the clock phase difference between the two inputs of the phase comparator 11, it is necessary to change the frequency between the input clock 10 and the output clock 20. Phase changes. However, even if the frequency of the input clock lO changes, it is desirable that the phase difference between the input clock 10 and the output clock 20 does not change. Therefore, a high gain amplifier 13 is used to detect slight changes in the output of the phase comparator 11. By amplifying the input clock 10 and the output clock 20
Voltage controlled oscillator 14 while suppressing the amount of change in phase difference.
I am getting the desired voltage on the input.

[Problem to be solved by the invention]

In this conventional PLO circuit, when the input clock is cut off and the phase comparator output becomes dependent only on the output clock of the voltage controlled oscillator, since a high gain amplifier is used, As a result of amplifying the small DC component generated by the voltage controlled oscillator, a voltage outside the linear operating region of the voltage controlled oscillator is applied to the input of the voltage controlled oscillator. Therefore, there is a problem in that the frequency of the output clock of the voltage controlled oscillator is far different from the normal input clock frequency.

[Means to solve the problem]

The PLO circuit of the present invention includes a phase comparator that outputs a pulse with a width proportional to the phase difference between an input clock and a feedback clock, a low-pass filter that outputs a voltage obtained by smoothing the input pulse, and an input clock. an amplifier that amplifies the voltage of the amplifier, a voltage controlled oscillator that outputs the feedback clock according to the output voltage from the amplifier, and sets the input voltage of the voltage controlled oscillator to a predetermined value when the input clock is cut off. and a detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes a phase comparator 1 that outputs a pulse with a width proportional to the phase difference between an input clock 10 and a feedback clock 20, and a low-frequency one-wavelength waveform that outputs a voltage smoothed by the input pulse from the phase comparator 1. an amplifier 3 that amplifies the voltage input from the low frequency transducer 2, and a voltage controlled oscillator 4 that outputs a feedback clock 20 in accordance with the output voltage from the amplifier 3.
and a detection circuit 5 which sets the input voltage of the voltage controlled oscillator 4 to the set voltage VFR of the power supply 7 via the switch 6 when the input clock 10 is cut off.

In this way, when the input clock 10 is applied, the voltage controlled oscillator 4 operates with the voltage from the amplifier 3, and when the input clock 10 is cut off, the detection circuit 7 operates the voltage by switching the switch 6. Since the set voltage (VFR) 7 of the power supply 7 is connected to the input of the controlled oscillator 4, the frequency of the feedback clock 20 can be set to a value that is not much different from the frequency of the input 10 that is normally applied.

〔Effect of the invention〕

As explained above, the present invention fixes the input voltage of the voltage controlled oscillator to a predetermined value when an input clock disconnection state is detected, so that when the input clock is applied, the input clock and output clock are This has the effect of suppressing a significant change in the frequency of the output clock when the input clock is cut off, while suppressing phase fluctuations with respect to the input clock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional PLO circuit. 1... Phase comparator (PC), 2... Low-pass filter (L
PF), 3... Amplifier, 4... Voltage controlled oscillator (V
C○), 5...Detector (DET>, 6...Switch, 7...Power supply (VFR).

Claims (1)

[Claims] a phase comparator that outputs a pulse with a width proportional to the phase difference between the input clock and the feedback clock; a low-pass filter that outputs a voltage obtained by smoothing the input pulse; and an amplifier that amplifies the input voltage. and a voltage controlled oscillator that outputs the feedback clock according to the output voltage from the amplifier, and a detection circuit that sets the input voltage of the voltage controlled oscillator to a predetermined value when the input clock is disconnected. Characteristic PLO circuit.