JPH0465160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide excellent contact characteristic and to improve driving capacity by forming a second polysilicon layer of a P-type and forming a gate electrode of a PMOS transistor of the layer. CONSTITUTION:After NMOS transistors Trs 34, 35 are formed on a P-type well layer 31, first and second PMOS Trs 39, 40 are formed thereon through an interlayer insulating film 38. The Trs 39, 40 are formed at a gate electrode 41 of a second P<+> type polysilicon layer, and an active region 42 is formed of a third polysilicon layer. Since the gate electrodes 41 of the Trs 39, 40 are formed of the second layers, the contact of a P<+> type diffused layer 44 as a drain region of the Tr39 with the electrode 41 of the Tr39 is a connection of the P<+> type layers to obtain excellent contact characteristic and to improve driving capacity by increasing an ON current.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device having a stacked CMOS inverter element structure.

(Prior Art) FIG. 3 shows a conventional method for manufacturing a semiconductor device having a stacked CMOS inverter element structure. This figure 3 shows the laminated type CM
This is a part of the case where a pair of OS inverter elements, ie, a pair of NMOS transistors and a pair of PMOS transistors are formed to configure, for example, a buffer circuit.

First, as shown in FIG. 3 t8+, a P-type well layer 1 is formed on a silicon substrate, and an element isolation region 2 is selectively formed on the surface thereof. Furthermore, a first N layer is formed on the surface of the P-type well N1.
The gate oxide films 5 of the MOS transistor 3 and the second NMO3I-transistor 4 are formed, and the gate oxide films 5 of the first MOS transistor 3 and the second NMO3I transistor 4 are formed.
N2 diffusion layers 6 (only one diffusion layer of the second NMOS transistor 4 is shown) serving as the source and drain of the second NMOS transistor 3.4 are formed in the P-type well layer 1 by ion implantation and annealing. Then the first NM
The gate electrode of the OS transistor 3 and the second NM, which will be described later.
After a contact hole 7 for connecting one N' diffusion layer 6 of the OS transistor 4 is opened in the gate oxide film 5 of the second NMOS transistor 4, an I-th polycide layer is formed, and N is connected to the polycide layer. type impurity doping,
By performing patterning, gate electrodes 8 of the first and second NMOS transistors 3 and 4 (only the gate electrode of the first NMOS transistor 3 is shown) are formed. Here, the gate electrode 8 of the first NMOS transistor 3 is connected to the second NMOS transistor through the contact hole 7.
It is connected to one of the N diffusion layers 6 of the OS transistor 4. After that, an interlayer insulating film 9 is formed on the entire surface, and a gate electrode 8 of the first NMO transistor 3 is formed on this interlayer insulating film 9.
A contact hole 10 is opened at the top.

After that, a second polysilicon layer is formed on the entire surface, and this second polysilicon layer is formed on the entire surface.
By ion-implanting N-type impurities (phosphorous or arsenic) into the second polysilicon layer and further patterning, the first PMOS transistor 11 and the second PMOS transistor 12 are formed as shown in FIG. A gate electrode 13 is formed.

At this time, either the ion implantation or the patterning indicated by the arrow 14 may be performed first. In addition, in this gate electrode formation, the gate electrode 13 of the first PMOS transistor 11
is the first NM through the contact hole 10.
It is formed so as to be connected to the gate electrode 8 of the OS transistor 3.

Thereafter, the gate electrodes 13 of the first and second PMOS transistors 11 and 12 are
A gate oxide film 15 is formed on the surface of the gate oxide film 15 as shown in FIG. 3 tc+. Then, a contact hole 16 is opened in the gate oxide film 15 of the first PMOS transistor 11. Thereafter, a third polysilicon layer is generated on the entire surface and patterned to form active regions 17 of the first and second PMOS transistors 11 and 12 (second PM
Only the active region of the OS transistor 12 (shown in the figure) is formed. At this time, the active region 17 of the second PMOS transistor 12 is formed so that a portion that will become a P diffusion layer as a drain region in the future is connected to the gate electrode 13 of the first PMOS transistor 11 through the contact hole 16. be done.

Thereafter, as shown in FIG. 3 (d+), by performing ion implantation 19 of P-type impurity (boron) using the resist pattern 18 as a mask, active regions 17 of the first and second PMOS transistors 11 and 12 (but (The active region of the first PMOS transistor 11 is not shown) is provided with a pair of P diffusions 20 as a source and drain.
form.

As a result, in the second PMOS transistor 12, one P diffusion layer 20 serving as a drain region is connected to the gate electrode 13 of the first PMOS transistor 11 through the contact hole 16.

After that, after removing the resist pattern 18, normal CM
Similar to OS devices, formation of intermediate insulating film, reflow
Performs operations such as opening contact holes, forming metal wiring, and forming a pansivation film.

(Problems to be Solved by the Invention) However, as shown in FIG. 4, which is a schematic cross-sectional view of the conventional semiconductor device manufactured as described above,
P diffusion layer 20 as the drain region of the second PMOS transistor 12 and the first PMOS transistor 11
In the contact part of the gate electrode 13, the P° layer and the N
Since the layers are connected, a PN junction is formed at the contact portion, resulting in a problem in that good contact characteristics cannot be obtained.

Further, the PMOS transistor has a high threshold voltage, and sufficient driving ability cannot be obtained at the power supply voltage (for example, 3 to 5 V) under normal usage conditions.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device that can solve the above conventional problems.

(Means for Solving the Problems) In the present invention, a plurality of NMOS transistors are formed on a semiconductor substrate with a first polycide layer as a gate electrode, and a second polycide layer is formed thereon with a gate electrode and a third polycide layer as a gate electrode. Multiple PMOs using the second polysilicon layer as an active region
An S transistor is formed and P as the drain region is part of the active region of the PMOS transistor.
In a semiconductor device in which the wave rectifying layer portion is connected to the gate electrode of another PuO transistor, and the gate electrode is connected to the gate electrode of an NMOS transistor, PuO
3) The second polysilicon layer constituting the gate electrode of the transistor is a P-type polysilicon layer.

(Function) The second polysilicon layer is a P-type polysilicon layer, and i
If the gate electrode of a PuO3) transistor is formed using a P-type polysilicon layer, as shown in FIG. Since the layers are connected to each other, good contact characteristics (ohmic characteristics) can be obtained.

At this time, the gate electrode of the PuO3) transistor and the NMO5
) The connection of the gate electrode of the transistor is a P-N connection because the first polycide layer is N type, but the second polycide layer is used for the gate electrode, and the third layer is used for the active region. Since the P-type impurity concentration can be made higher than in the polysilicon layer and the I-th layer is made of polycide (the upper layer is solicide and the lower layer is N-type polysilicon), good contact characteristics can be obtained.

Also, if the gate N pole of the PuO3) transistor is formed with a P-type polysilicon layer, it will become a P-type gate structure, and as a result, the threshold voltage of the PuO3) transistor will shift (lower) by about 1. The on-state current increases, and the driving ability improves.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. In this figure, 31 is a P-type well layer formed on a silicon substrate, and an element isolation region 32 is formed on the surface portion. Then, on this P-type well layer 31, a gate electrode 33 is formed using a first N polycide layer, and the first and second NMO layers are formed.
S transistors 34 and 35 are formed, 36 is a gate oxide film thereof, and 37 is an N diffusion layer as its source and drain. However, only the N diffusion layer 37 serving as the drain region of the second NMOS transistor 35 is illustrated, and the gate electrode 33 is the drain region of the second NMOS transistor 35.
Only the gate electrode of transistor 34 is shown. After forming such NMOS transistors 34 and 35, first and second Pu
O3) Transistors 39 and 40 are formed. The first and second PMOS transistors 39 and 40 are formed by forming a pole 41 using a second layer of polysilicon layer 9993 and forming an active region 42 using a third layer of polysilicon. 43 is a gate oxide film on the surface of the gate electrode 41, and 44 is a P diffusion layer as a source/drain formed in a part of the active region 42. however,
The active region 42 and a portion thereof, the P° diffusion layer 44, are only shown as the active region and the P° diffusion layer of the second PuO3) transistor 40. And the second PuO
3) One P diffusion layer 44 serving as the drain region of the transistor 40 is formed through a contact hole 45 opened in the gate oxide film 43 of the first PuO transistor 39.
1. Gate electrode 41 of first PMOS transistor 39
The gate electrode 4I is connected to the gate electrode 33 (formed of N'' polysilicon layer) of the first NMOS transistor 34 through a contact hole 46 formed in the interlayer insulating film 38. Furthermore, the gate electrode 33 of the first NMOS transistor 34 is connected to the drain of the 26th NMOS transistor 35 through a contact hole 47 formed in the gate oxide film 36 of the second NMOS transistor 35. It is connected to the N9 diffusion layer 37 as a region.

FIG. 2 is a schematic cross-sectional view of one embodiment as described above. In particular, as can be clearly seen in FIG. 2, according to the above-mentioned embodiment, the second polysilicon layer is made of polysilicon, and this second polysilicon layer is used as the first and second polysilicon layer. 2 PMOS
Since the gate electrode 41 of the transistor 3940 is formed, the contact part of the P° diffusion [44 and the gate electrode 41 of the first PMOS transistor 39 as the drain region of the second PMOS transistor 39 is the connection between the P'' layers. Thus, good contact characteristics were obtained.

In addition, in the device of this embodiment, when ion-implanting impurities into the non-doped second polysilicon layer, only the P-type impurity (boron) is ion-implanted, and the rest is carried out using the conventional manufacturing method shown in FIG. It can be manufactured in exactly the same manner.

Also, 1st. 2nd PMO5) transistor 39°40 and 1st. When completing a flip-flop circuit with the second NMO3I-run star 3435, the first PMOS transistor 39
The P diffusion layer serving as the drain region of the transistor is connected to the gate electrode 41 of the second PMOS transistor 40, the gate electrode 41 is connected to the gate electrode of the second NMOS transistor 35, and the gate electrode is connected to the gate electrode of the first NMOS transistor 35. It is connected to the P diffusion layer as the drain region of the transistor 34, and the contact portion between the P diffusion layer as the drain region of the first PMOS transistor 39 and the gate electrode 41 of the second PMOS transistor 40 is also connected to P.
``Connection between layers and good contact characteristics have been achieved.

(Effects of the Invention) As described above in detail, according to the semiconductor device of the present invention, the second polysilicon layer is a P-type polysilicon layer, and this P-type polysilicon layer forms the gate electrode of the PMOS transistor. Therefore, the gate electrode and other PMOS
The contact portion with the P-type diffusion layer serving as the drain region of the transistor serves as a connection between the P-type layers, and good contact characteristics (ohmic characteristics) are obtained.

At this time, the gate electrode of the PMOS transistor and the NMOS
The connection part of the gate electrode of the transistor is a P-N connection because the first polycide layer is N type, but 2NN type polysilicon is used for the gate electrode, and the third polycide layer used for the active region is a P-N connection. Since the P-type impurity concentration can be made higher than that of the first layer, and the I-th layer is made of polycide (the upper layer is silicide and the lower layer is N-type polysilicon), good contact characteristics can be obtained.

In addition, if the gate electrode of a PMOS transistor is formed with a P-type silicon layer, it will become a P-type gate structure, which shifts the threshold voltage of the PMOS transistor by about 1. It is possible to increase the current and improve the driving ability 6

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic sectional view of the device of the embodiment, and FIG. FIG. 4 is a schematic cross-sectional view of the device obtained by the conventional manufacturing method shown in FIG. 31...P-type well layer, 33...gate electrode, 34
...First NMOS transistor, 35... Second NMOS transistor, 39... First PMOS transistor, 40... Second PMOS transistor, 4
1... Gate electrode, 42... Active region, 44
...P゛diffusion layer. P-type well layer Gate electrode First NMOS transistor Second NMOS transistor First PMO5h transistor Second PMOS transistor Gate electrode Near-active region: P+ diffusion layer An embodiment of the present invention! Figure 44P: Schematic cross-sectional diagram of the embodiment of the diffusion layer of the present invention Figure 2 Schematic cross-sectional diagram of the conventional device Figure 4

Claims (1)

[Claims] A plurality of NMOS transistors are formed on a semiconductor substrate using a first polycide layer as a gate electrode, and
A plurality of PMOS transistors are formed using the second polysilicon layer as a gate electrode and the third polysilicon layer as an active region, and a P-type diffusion layer portion serving as a drain region that is a part of the active region of the PMOS transistor is In a semiconductor device that is connected to the gate electrode of another PMOS transistor and whose gate electrode is connected to the gate electrode of an NMOS transistor, the second polysilicon layer constituting the gate electrode of the PMOS transistor is a P-type polysilicon layer. A semiconductor device characterized by: