JPH0461161A - Memory pattern layout of semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce fail rate during a manufacturing process by arranging a dummy memory so as to surround the main memory area of a semiconductor memory device. CONSTITUTION:A dummy memory 7 is disposed so as to completely surround a main memory area 5. The dummy memory 7 is arranged so as to surround the main memory area 5 constituted of word lines W1-Wn and bit lines b1-bn in a matrix shape. The word lines W1-Wn and the bit lines b1-bn are shared mutually. Word lines Wd1, Wd2 and bit lines bd1, bd2 are used as ones exclusive for the dummy memory. Even when a selective High signal is applied to the word lines W1-Wn, the dummy memory is turned 'OFF' positively. Even when the selective High signal is applied to the bit lines b1-bn, the dummy memory is turned 'OFF' positively, thus operating only the main memory area. Accordingly, since the dummy memory is disposed at the terminal section of a main memory array section, a crack does not reach the main memory array section even when the crack is generated in the insulating film, etc., of the terminal section of the memory area, thus stably operating a semiconductor memory device normally.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pattern layout of a memory array using dummy memory in a semiconductor memory device, which greatly reduces manufacturing defects in a regular memory array, and It is also intended to significantly improve quality.

[Conventional technology]

FIG. 4 is a block diagram of a conventional semiconductor memory device. (1) is a chip of a t-conductor memory device, (2)
is an input circuit such as an address buffer, (3) is an X-decoder that selects the word line of the memory array, (4) is an X-decoder that selects the bit line of the memory array, (5) is the memory array, and (6) is the sense active. and an output circuit such as an output buffer.

In order to facilitate understanding of the invention, a block circuit diagram of a conventional semiconductor memory device is further shown in FIG. The memory array is a mask ROM (Read Only Memory) in which "l"0" information is written by changing the threshold voltage (V + h) of the memory transistor during the manufacturing process.
ory) as an example.

The same symbols as in FIG. 4 indicate the same parts. (Δ,.)~(
A,,) is the X address input code, (Aa.) ~ (△7
．． ) is the Y address human horn signal, (Wl) to (W, ) are the word lines that serve as the gates of the memory transistors, (bl)
~(b,) is the bit line of the memory transistor, (D
, ) to (D, ) are output data signals. Word lines (W l) to (W,) and bit lines (b l) to (b,) are selected by the X and Y address input signals, and are output as output data signals through the sense amplifier/output buffer 7 (6). be done.

Figures 6 (A) and (B) are plan views of the memoria area (A).
) and a side sectional view (B) taken along the dotted line Z in the plan view (A). In Figure 6, (W) is the gate material that will become the word line, (b) is the metal material that will be the bit line, αD is the impurity diffusion layer, and α2 is the material for connecting the metal material (b) and the impurity diffusion layer aυ. Contact hole, 03 is field insulating film, a is thin gate oxide film to have transistor characteristics, a9
is a semiconductor substrate, OQ is an insulating film between the gate material (W) and metal material (b), and αn is a surface protection film.

Next, the function and operation of the prior art will be explained.

Among semiconductor memory devices, in highly integrated memories whose memory capacity exceeds M (mega) hints, the plane (turn design standards) of the memory area and the peripheral circuit are different.
Attempts are made to reduce the area of the memory area by using the finest pattern in the memory area. In a highly integrated memory, the memory area portion is 70 to 8004 of the entire chip, so reducing the area of the memory area portion significantly reduces the area of the entire chip.

For example, if the gate width in the memory area is 1.5 μm, the width in the peripheral portion is about 2.0 to 2.5 μm.

The peripheral area includes sense amplifiers for sensing minute levels and output (output) buffers that require large drive capabilities, and is susceptible to process fluctuations as changes in transistor characteristics. The minimum pattern width is generally not used as much as possible.

In addition, the memory area section stores the type of memory (for example, mask ROM, EPROM, DRAM, SRAλ4, etc.)
The repetition pattern may differ depending on the pattern, or it is generally a single basic memory pattern or a matrix pattern that is repeatedly arranged in the memory area.

Therefore, at the end of the memory area section, as shown in Fig. 6 (
As shown by the arrow in A), the stress of the insulating film 0G and the stress of the protective film αη ((γ) in FIG. 6(B)) are applied. These stresses at the edge of the memory area cause cracks OFj in the insulating film aO.
Furthermore, microcracks may occur in the memory transistor portion at the end of the memory area, changing the characteristics of the memory transistor and preventing it from operating normally.

[Problem to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, it is necessary to strictly control the conditions for forming the insulating film and the protective film so that minute manufacturing defects are less likely to occur at the edge of the memory area. In addition, manufacturing defects that increase the memory area can cause a large number of defective products, resulting in a high defect rate during the manufacturing process (also, if there are microcracks that cannot be removed by screening during the manufacturing process), Sometimes there was a problem with malfunctions.

This invention consists of 1. This method was developed to solve the problems described above, and does not require special conditions for forming insulating films or protective films, and allows semiconductor memory devices to operate normally even if manufacturing defects occur at the edge of the memory area. This is considered LJ-like.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, at least one row of dummy memories is arranged at the end of the main memory array section, and the dummy memories that share the word line of the main memory array section have bit lines connected to each other. Further, in the dummy memory that shares the bit lines, the word lines are each set to floating or ground level.

[For production]

In the semiconductor memory device of the present invention, a dummy memory is placed at the end of the main memory array, so even if a crack occurs in the insulating film or the like at the end of the memory area, it will not reach the main memory array. So the semiconductor memory device can operate stably and normally.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. 1st
The figure is a chip plane block diagram of a semiconductor memory device according to the present invention. The same symbols as in the conventional example (FIG. 4) indicate the same parts. (7) is a dummy memory section.

FIG. 2 shows a block circuit diagram of a semiconductor memory device according to the present invention. The same symbols as in the conventional example (FIG. 5) indicate the same parts. (7) is a dummy memory section, (Wd,)(Wd
2> is the word line of the dummy memory, (b d,) (b
a, ) are the bit lines of the dummy memory.

Figure 3 shows a plan view (A) of the memory array section and a plan view (A) of the memory array section.
, ) is shown in a side sectional view (B) along the dotted line Z. The same symbols as in FIG. 6 of the conventional example indicate the same parts. (bdz) is a bit line of the dummy memory, and (Wd,) is a word line of the dummy memory.

In Figures 1.2.3, explanations of parts that are the same as those of the conventional example have been omitted.

The key point of the present invention is that the dummy memory (7) or the main memory area (5) is arranged so as to completely surround it, as can be seen in FIG.

In the block circuit diagram of FIG. 2, a mask ROM is shown as an example for ease of understanding. Word lines (Wl) to (Wa
) and bit lines (bl) to (b,) in a matrix configuration, and a dummy memory (7) is arranged to surround the main memory area (5). The word lines (Wl) to (W7) and the bit lines (bl) to (b,) are shared with each other. The word line (W d , ) (W d 2) and the bit line (b d , ) (b d 2) are dedicated to the dummy memory. Here, the part marked ■ (Σ) is set as floating or ground level (GND'). This prevents it from operating as a dummy memory or a normal transistor. Word line (W 1) to (W, ) selected) 1i
Even if the gh signal is applied, the dummy memory is always "OFF" because the source or bit line of the dummy memory is floating or GND. Also, the bit line (b
Even if the selection High signal is applied to 1) to (b,), the dummy memory is always “OFF” because the source or gate (word line) of the dummy memory is floating or GND, so the main memory area It can operate without any change from conventional methods.

Now, in the plan view of FIG. 3A, the source of the impurity diffusion layer at+ between the main memory and the dummy memory is cut. Generally, the source is connected to GND, so in this case,
The source of the dummy memory is floating.

Of course, if it is connected to GND, it may be connected in the same way as the main memory.

Here, it is easy to understand that even if a crack 0 sand is generated due to the stress of the insulating film Oe and the protective film a and the dummy memory is destroyed, the main memory is not affected at all. In other words, since the main memory is separated by a distance of one memory or more compared to the case where a crack occurs at the end of the memory, which is most likely to occur, damage to the main memory can be prevented.

(3) Examples of application to other uses In the above embodiments, mask ROM among semiconductor memory devices has been described, but EPROM, DRAM, SRAM, or other semiconductor memory devices may be used. Furthermore, although it has been described that the dummy memories are arranged in one column each in the word line direction and the bit line direction in the main memory, even if the dummy memories are arranged in one column each in the word line direction and the bit line direction, the same or better effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the dummy memory is arranged to surround the main memory area of a semiconductor memory device, manufacturing defects that tend to occur at the edge of the memory area are prevented from reaching the main memory area, and This has the effect of significantly reducing the defective rate during the manufacturing process and providing highly reliable products.

[Brief explanation of drawings]

FIG. 11 is a chip plane block diagram of a semiconductor memory device of the present invention, FIG. 2 is a block circuit diagram according to the present invention, and FIG.
Figures (Δ) and (B) are a memory plane pattern diagram and a side sectional view thereof according to the present invention, Figure 4 is a conventional chip plane block diagram, Figure 5 is a conventional block circuit diagram, and Figure 6 (A) (
B) A planar pattern diagram and a side sectional view of a conventional memory. (1)...Semiconductor memory device chip, (2)...
Input circuit, (3)...X decoder, (4)...X decoder, (5)...Memory memory, (6)...Output circuit, (7)...Dummy memory, ( Δ,.)～(A
,,)...X address input signal, (Aa.) ~ (A,
A)...Y atsushi input signal, (W l) ~ (W yo)...
... Word line, (b 1) ~ (b c... Bit line, (
Do) to (D,)...output data signal, (W d ,
') CW d 2>... Dummy memory word line, (
b d , ) (b a 2)... Bit line of dummy memory, aυ... Impurity diffusion layer, 021... Contact hole, a3... Field insulating film, (14)... Gate oxide film , α9...semiconductor substrate, shout...insulating film,
a.Protective film, 0 mark...Crack agent Masuo Oiwa Figure 3 Figure 1 Figure 4

Claims (2)

[Claims] (1) In a semiconductor memory device having a memory array consisting of a plurality of MOS transistors, a decoder circuit for selecting the memory, and peripheral circuits including an address input circuit and a data output circuit, at least one column or more is provided at the end of the memory array. A memory pattern layout of a semiconductor memory device characterized by arranging dummy memories. (2) A dummy memory whose word line is shared with the word line of the memory array has the bit line and the source of the memory transistor floating or at ground level. A memory pattern layout of a semiconductor memory device characterized in that word lines and sources of memory transistors are floating or at ground level.