JPH0461157A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the effective surface area of a lower electrode by curvedly forming the lower electrode along eave structure formed by side-etching a spacer film. CONSTITUTION:Conductor films 4, 5 for forming word lines constituting the gate electrode of a MIS transistor, a spacer film 10 and a specified film 11 are formed successively on the whole surface, and the film 11, the spacer film 10 and the conductor films 4, 5 are patterned in specified shapes in succession. The spacer film 10 is side-etched, a conductor film 13 for shaping the lower electrode of a stacked capacitor is formed on the whole surface, and the conductor film 13 is patterned, thus forming the lower electrode. A conductor film 15 for shaping the upper electrode of the stacked capacitor is formed onto the lower electrode through an insulating film 14, and the conductor film 15 is patterned, thus forming the upper electrode. Accordingly, the capacitance of the stacked capacitor can be increased without complicating processes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor memory, and in particular, to a method of manufacturing a semiconductor memory.
It is suitable for application to the manufacture of semiconductor memories having a tor cell.

(Summary of the Invention) The present invention provides a method for manufacturing a semiconductor memory having a stacked capacitor cell, in which a spacer film is used to form a conductor film that becomes a lower electrode of a stacked capacitor in a bent shape. By using this method, a word line is formed on the field oxide film in a floating state from the field oxide film, and a conductor film that becomes the lower electrode is also formed on the outer periphery of the word line, or a conductive film is formed on the semiconductor substrate. By forming a word line on the slope of the convex part and extending the lower electrode on this word line,
The effective area of the stacked capacitor is increased so that a sufficiently large capacitance can be obtained.

[Conventional technology]

In recent highly integrated MOS dynamic RAM,
A one-transistor, one-capacitor type memory cell is used. As a capacitor constituting this memory cell, a stacked capacitor (st
ackeii capacitor) (for example,
Nikkei Electronics, June 3, 1985, pp.
209-231. ).

This stacked capacitor is the second Jiil! It has a structure in which an upper electrode formed from a third-layer polycrystalline Si film G is stacked on a lower electrode 1° formed from a polycrystalline silicon (Si 2 ) film G with an insulating film interposed therebetween.

According to this stacked capacitor, it is possible to obtain a larger capacitance than a conventional Brenna type capacitor because the capacitor is not flat but curved and a capacitor is also formed on the side wall of the lower electrode. can. However, as the dimensions of memory cells decrease, it has become difficult to obtain sufficiently large capacitance with conventional stacked capacitors.

Therefore, in order to increase the capacitance of the stacked capacitor, the area of the capacitor formed on the side wall of the lower electrode is increased by increasing the thickness of the second layer of polycrystalline Si film that becomes the lower electrode. A method has been adopted in which the effective area of the capacitor is increased by forming the lower electrode into a fin shape.

(Problem to be Solved by the Invention) However, the method described above increases the thickness of the second layer polycrystalline Si film serving as the lower electrode (thereby increasing the area of the capacitor formed on the side wall of the lower electrode). Therefore, it is becoming difficult to increase the capacitance of a stacked capacitor sufficiently.Furthermore, when the thickness of the second layer of polycrystalline Si film, which serves as the lower electrode, is increased, the lower When this second layer of polycrystalline Si film is etched by, for example, reactive ion etching (RUE) to form an electrode, this second layer of polycrystalline Si film is etched on the sidewall of the step portion of the base. It is necessary to perform overetching to prevent the formation of wall-like formations, that is, so-called stringers.
There was a problem that the conditions during etching were severe and it was not productive. Furthermore, when the film thickness of the second layer of polycrystalline 5ill serving as the lower electrode is increased, the level difference on the surface becomes correspondingly large, which is not preferable for the subsequent processes.

On the other hand, the method of increasing the effective area of the capacitor by forming the lower part in the form of a fin has the problem of complicating the process.

An object of the present invention is to provide a method for manufacturing a semiconductor memory that can sufficiently increase the capacitance of a stacked capacitor without complicating the process too much.

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as follows.

A first invention provides a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, in which a conductor III (4 ，
5), Suhe-4J-Wa (10) and certain III (
Steps of sequentially forming 11) on the entire surface and a predetermined film (11)
, Spacer rII! (10) and a step of sequentially patterning the conductor films (4, 5) for forming word lines into a predetermined shape, and a step of side etching the spacer film (10);
Conductor film for forming the lower electrode of stacked capacitor (13
) is formed on the entire surface, and a conductor film for forming the lower electrode (
13) forming a lower electrode by patterning; forming a conductive film (15) for forming an upper electrode of a stacked capacitor via an insulating film (14) on the lower electrode; and forming an upper electrode. forming an upper electrode by patterning a conductive film (15) for use in the process.

A second invention provides a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, in which a word line (WL, ~WL,) forming a gate electrode of the MIS transistor is After the formation, there is a step of forming spacers W (20) on the entire surface, and a step of forming a word line (WL).

~WL,) A step of patterning a spacer film (20) into a predetermined shape on which both ends of the lower electrode of the stacked capacitor extend when viewed in the longitudinal direction, and a conductor film (13) for forming the lower electrode. a step of forming a lower electrode on the entire surface, a step of forming a lower electrode by patterning a conductive film (13) for forming the lower electrode, and a step of forming an insulating film (14) on the lower electrode.
A step of forming a conductor film (15) for forming an upper electrode of a stacked capacitor through a conductor film (15) for forming an upper electrode of a stacked capacitor;
f! (15) forming an upper electrode by patterning.

A third invention is a method for manufacturing a semiconductor memory having a memory cell consisting of one MISI transistor and one stacked capacitor, in which a field oxide film (2)
After forming a spacer film (21) on the entire surface, a word line (WL) forming the gate electrode of the MIS transistor is formed.

A process of patterning the spacer M (21) in a predetermined shape extending at least on the field oxide film (2) when viewed in a direction perpendicular to the longitudinal direction of the word line (WL, );
, ~WL, ), a process of removing the spacer film (21), a process of forming the insulation Jl (12) on the word line (WL, ~WL, ), and a step of forming the lower electrode of the stacked capacitor. A step of forming a conductor film (13) for formation on the entire surface, a step of forming a lower electrode by patterning the conductor film (13) for forming a lower electrode, and a step of forming a conductor film (13) on the lower electrode with an insulating film (14) interposed therebetween. and a step of forming an upper electrode by patterning the conductor film (15) for forming an upper electrode.

A fourth invention is a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, after forming a field oxide film (2), the gate electrode of the MIS transistor is The constituent word lines (WL.

A step of forming a film (23) that can be selectively etched on the entire surface of the word line (W L + ~ WL, );
) for patterning the film (23) that can be selectively etched into the shape of the inverted pattern of the word lines (WL, ~WL4), and the conductor I! for forming the word lines. (24) on the entire surface, a step of forming a surface flattening film (25) on the entire surface, and at least the word lines (WLI to WL).
, ), the word lines (WL, ~WL
4), removing the film (23) that can be selectively etched with respect to the surface flattening film (25) and the word lines (WL, -WL4), and forming the lower electrode of the stacked capacitor. Conductor 11 for! (13) on the entire surface, forming a lower electrode by patterning the conductive film (13) for forming the lower electrode, and forming a stacked capacitor on the lower electrode via the insulating film (14). The method includes a step of forming a conductor film (15) for forming the upper electrode, and a step of forming the upper electrode by patterning the conductor film (15) for forming the upper electrode.

A fifth invention provides a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, in which the main surface of the semiconductor substrate (1) is A process of forming a convex portion (1a) having a slope sloped with respect to the word line (WL, -WL4) constituting the gate electrode of the MISI transistor.
on the slope of the convex portion (1a) via the gate oxide film (3), a step of forming a conductor film (13) for forming the lower electrode of the stacked capacitor on the entire surface, and a step of forming the conductor film (13) for forming the lower electrode of the stacked capacitor. A step of forming a lower electrode by patterning the conductor II (13), and forming an insulating film (13) on the lower electrode.
4) forming a conductor film (15) for forming an upper electrode of a stacked capacitor; and forming an upper electrode by patterning the conductor film (15) for forming an upper electrode. .

[Function] According to the method for manufacturing a semiconductor memory according to the first invention configured as described above, by side-etching the spacer film (10), a predetermined film is removed from the side-etched spacer film (10). An eaves structure from which (11) protrudes is formed.

Therefore, the conductor film (13) for forming a partial electrode of the stacked capacitor, which will be formed later, has a bent shape along this eave structure. As a result, the effective surface area of the lower electrode can be made sufficiently larger than that of the conventional method when compared with the same occupied area. As a result, the effective area of the stacked gear nozzle can be made sufficiently large, and the capacitance of the stacked capacitor can therefore be reduced to 1.
You can make it bigger in minutes. Moreover, the process is relatively simple.

According to the method for manufacturing a semiconductor memory according to the second invention configured as described above, the shape of both ends of the lower electrode of the stacked capacitor is shaped like an inverted 17 character when viewed in the longitudinal direction of the word lines (WL to WL,). Since it can be made into a shape, the effective surface area of the lower electrode can be made sufficiently larger than the conventional one when compared with the same occupied area due to the contribution of the surface area of the inverse [,-shaped part. As a result, the effective area of the stacked gear vacacitor can be increased on the upper back, and therefore the capacitance of the stacked capacitor can be sufficiently increased. Moreover, the process is relatively simple.

According to the method for manufacturing a semiconductor memory according to the third invention configured as described above, after removing the spacer film (21), the spacer W! The word lines (WL, , WL4) where (21) were are field oxidized to a height corresponding to the film thickness of this spacer film (21).
It becomes a floating structure. Therefore, when a conductor film (13) for forming a lower electrode of a stacked capacitor is formed after that, the outer periphery of the word line (WL, WLJ) floating from this field oxidation M(2) and The conductor film (13) for forming the lower electrode is also on the field oxide film (2) below the word lines (WL, , WL,).
) is formed. Therefore, the effective surface area of the lower electrode can be made sufficiently larger than that of the conventional method when compared with the same occupied area. Thereby, the effective area of the stacked capacitor can be made sufficiently large, and therefore the capacitance of the stacked capacitor can be made sufficiently large.

Moreover, the process is relatively simple.

According to the method for manufacturing a semiconductor memory according to the fourth aspect of the invention configured as described above, at least the word lines (WL, ~W
The word lines (WL, ~WL,) are formed by etching back in a direction substantially perpendicular to the surface of the semiconductor substrate (1) until the film (23) that can be selectively etched with respect to L4) is exposed. , has a U-shaped shape when viewed in cross section perpendicular to its longitudinal direction. Therefore, the conductor film (13) for forming the lower electrode of the stacked capacitor to be formed later
) is formed with a large curve along this U-shaped cross-sectional shape. Therefore, the effective surface area of the lower electrode can be made sufficiently larger than that of the conventional method when compared with the same occupied area. Thereby, the effective area of the stacked capacitor can be made sufficiently large, and therefore the capacitance of the stacked capacitor can be made sufficiently large.

Moreover, the process is relatively simple.

According to the method for manufacturing a semiconductor memory according to the fifth invention configured as described above, word lines (WL+ to WL4) are formed on the slopes of the convex portions (1a) formed on the semiconductor substrate (1). Therefore, this word line (WL, -WL4)
The upper surface of the semiconductor substrate (1) is also inclined with respect to the main surface of the semiconductor substrate (1). The lower electrode of the stacked capacitor extending on the word line (WL, -WL4) is also inclined with respect to the main surface of the semiconductor substrate (1).

Therefore, the effective surface area of this lower electrode can be made sufficiently larger than that of the conventional method when compared with the same occupied area. Thereby, the effective area of the stacked capacitor can be made sufficiently large, and therefore the capacitance of the stacked capacitor can be made sufficiently large. Moreover, the process is simple.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following embodiments are all embodiments in which the present invention is applied to a stacked capacitor cell type MOS dynamic RAM. In addition, in all the figures of the embodiment, the same or corresponding parts are given the same reference numerals, and redundant explanation will be omitted as appropriate.

1 and 2 show a MOS dynamic RAM according to a first embodiment of the present invention, in which FIG. 1 is a plan view and FIG. 2 is a sectional view taken along line I-n in FIG. 1. It is.

As shown in FIGS. 1 and 2, the MOS dynamic RAM according to the first embodiment uses, for example, P-type Si.
A field oxide film 2, such as a Si0g film, is selectively formed on the surface of a semiconductor substrate 1, such as a substrate, to provide isolation between elements. The code 3 is, for example, Si
n, indicating a film-like gate oxide. Also, the code WL+
, WLz, WLs, WL4 indicate word lines; these word lines WLr, WL! , WL3, WL4
is a polycrystalline 5tWj! doped with an impurity such as phosphorus (P), for example. For example, tungsten silicide (
It is formed of a polycide film overlaid with a high melting point metal silicide film 5 such as WSi□) film. Here, the film thicknesses of the polycrystalline 5iWX4 and the high melting point metal silicide film 5 are, for example, about 1000 layers. For example, code 6 is 5i
A sidewall spacer made of ot film is shown. code 7
, 8.9 indicate, for example, an n° type semiconductor region, and
The word line WLz and the semiconductor region 7.8 form an n-channel MO3) transistor as an access transistor. Similarly, the word line W L 3 and the semiconductor region 8.9 serve as an access transistor.
Channel MO3) transistor is formed. In this case, these semiconductor regions 7.8.9 have, for example, n-type low impurity concentration portions 7a, 8a, 9a below the sidewall spacer 6. Therefore, these n-channel MO3) transistors as access transistors are LDDs in which the electric field in the vicinity of the semiconductor region 7.9 as the drain region is relaxed by the low impurity concentration portions 7a and 9a.
(lightly doped drain) structure.

On the words @WLx, WLz, WL3, and WL4, a spacer film 10 such as a Si0g film is interposed, for example.
Polycrystalline 51M1 doped with impurities such as P
l is formed. For example, a rectangular opening 10a is formed in this spacer film IO. In the opening 10a, the polycrystalline Si film 11 protrudes from the spacer film 10 into the opening lOa in the shape of an eave.

The thickness of the spacer film 10 is, for example, about 4,000, and the thickness of the polycrystalline film 10 is, for example, about 1,000.
There are about 7 people. Also, the word line WL,.

When the widths of WLz, WLs, and WLa, that is, the gate length, are, for example, 0.5 μm, the width of the spacer film 10 is, for example, about 0.2 μm.

The reference numeral 12 is, for example, Sin, a film, or phosphosilicate glass (
13 indicates an interlayer insulating film such as PSG) film, C3°C2 indicates a contact hole for Veri-Rad contact formed in this glabellar insulating film 12, and 13 indicates a polycrystalline Si doped with an impurity such as P. This polycrystalline S
The i film 13 has contact holes C,,C! formed in the glabella insulation [112]. Through each semiconductor area 7.9f
I am in contact. Moreover, in this case, this polycrystalline Si
The film 13 includes the lower surfaces of the polycrystalline Si film 11 protruding like an eave from the spacer film 10, the end face of the spacer film 10 in the opening 10a, and the word line wt,..., WL2°WL,...
It is formed along the upper surface of WL.

Further, an insulating film 14 is formed on this polycrystalline Si film 131. As this insulating film 14, for example, SiO□
ONO (Oxide-Nitride-Oxide) consisting of a film, a 5iOz film and a Si3N film, and a film and a SiO
e)! Ya, 5itNaF! 1 and siO,! A N 2 O (Nitride Oxiae) film made of I and the like can be used. Reference numeral 15 indicates a polycrystalline Si film doped with an impurity such as P, and the polycrystalline Si film 1
A stacked capacitor is formed by a lower electrode (charge storage layer) made of 3, an upper electrode (cell plate) made of an insulating film 14, and a polycrystalline 5iyi5.

Reference numeral 16 indicates a glabellar insulating film such as a PSG film.

Here, the interlayer insulating film 16 and the interlayer insulating film 12 in the region between the words tlA W L z and W L s
A contact ball C3 is formed in a predetermined portion of the contact ball C3. 6BL indicates a vinyl wire made of, for example, an aluminum (A1) film. Then, this bit line BI1. is in contact with the semiconductor region 8 through the contact hole C1.

Next, the MOS dynamic RAM according to the first embodiment
The manufacturing method will be explained.

As shown in FIG. 3A, first, by selectively thermally oxidizing the surface of the semiconductor substrate 1, a field oxide film 2 is formed to perform device isolation, and then an active region surrounded by this field oxide WI2 is formed. A gate oxide film 3 is formed on the surface by thermal oxidation. Next, polycrystalline Si was deposited on the entire surface using the CVD method.
After forming the film 4, the polycrystal 5iWj1.4 is doped with an impurity such as P by thermal diffusion or ion implantation to lower its resistance. Next, for example, sputtering or C
A high melting point metal silicide film 5 such as a W S i z film is formed on the entire surface by a VD method. Next, a CVD method is used to coat the entire surface with a spacer IIWI, such as a film made of, for example, Sin.
Form O. Next, polycrystalline Si was deposited on the entire surface using the CVD method.
After forming the film 11, for example, P is applied to this polycrystalline Si film 11.
The resistance is lowered by doping with impurities such as.

Next, these polycrystalline Si film 11, spacer MlO1, refractory metal silicide film 5, and polycrystalline film 5il14 are sequentially patterned into a predetermined shape by, for example, the RUE method. As a result, as shown in FIG. 3B, the word lines WLi,
WLz, Wl3, and Wl4 are formed, and polycrystalline si! i! ii and spacer film 10 are patterned to have the same shape as these word lines wt, , WL, , WL3WL, . Thereafter, a resist pattern 17 having, for example, a rectangular opening 17a (see FIG. 1 for the planar shape) is formed by lithography in a portion corresponding to the opening 10a.

Next, using this resist pattern 17 as a mask, the spacer film 10 is side-etched by a predetermined amount by, for example, wet etching, and then the resist pattern 17 is removed. This results in the state shown in FIG. 3C. Note that during this wet etching, the spacer film 10 is
In the case of the SiO□ film formed by the VD method, the etching rate of the spacer film 10 is much higher than that of the gate oxide WX3 formed by the thermal oxidation method. It is rarely etched.

Next, word lines WL, , WL2 . WL, 3. For example, by ion-implanting an n-type impurity such as P into the semiconductor substrate I at a low concentration using Wl,4 as a mask, for example, n-
A low impurity concentration semiconductor region (not shown) of the type is formed. Next, after forming, for example, a SiO□ film on the entire surface by CVD, this SiO□ film is etched in a direction perpendicular to the substrate surface by, for example, RIE. As a result, side wall spacers 6 are formed as shown in FIG. 2.

Next, using the sidewall spacer 6 as a mask, an n-type impurity such as arsenic (As) is ion-implanted into the semiconductor substrate 1 at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities.

As a result, the word lines WL+, WLz, WLs
.

For example, n-type semiconductor regions 7.8.9 are formed in self-alignment with Wl4. These semiconductor SMti1,
8.9, for example, an n-type low impurity concentration region consisting of the previously formed low impurity concentration semiconductor region? a, 8a, 9
a is formed.

Next, after forming an interlayer insulating film 12 on the entire surface by CVD, a predetermined portion of the glabellar insulating film 12 is removed by etching to form contact holes C, C2. Next, C.V.
A polycrystalline Si film 13 is formed on the entire surface by method D, and this polycrystalline Si film 13 is doped with an impurity such as P to lower the resistance.After that, this polycrystalline Si film 13 is etched to form a stacked capacitor. Pattern it into the shape of the lower electrode.

Next, an insulating film 14 is formed on this patterned polycrystalline St film 13. Next, a polycrystalline Si film 15 is formed on the entire surface by the CVD method, and after doping the polycrystalline Si film 115 with an impurity such as P to lower the resistance, the polycrystalline Si film 15 is etched to form a stacked capacitor. The upper part is patterned in the shape of t&. This forms a stacked capacitor.

Next, for example, PSGWJ is applied to the entire surface by, for example, CVD method.
7. Forming an interlayer insulating film 16 like . After that, predetermined portions of the interlayer insulating film 16 and the interlayer insulating film 12 are removed by etching to form a contact hole 0. form. Next, after forming, for example, 111% Al on the entire surface by sputtering, for example, this AI film is patterned into a predetermined shape by etching to form bit lines 13L. After this, a passivation film (not shown) is formed to obtain the desired MO
Complete S dynamic RAM.

According to the first embodiment, after the eaves structure in which the polycrystalline Si film 11 protrudes from the spacer film 10 is formed by 7g etching, the polycrystalline Si film that becomes the lower electrode of the stacked capacitor is formed. 13, the lower electrode of the stacked capacitor has a bent shape along this eave structure, and therefore the effective surface area of the lower electrode increases accordingly. Therefore, the effective area of the stacked capacitor is sufficiently large (and therefore, the capacitance of the stacked capacitor can be made sufficiently large. As a result, soft error resistance can be improved. Since it is not necessary to increase the thickness of the polycrystalline Si film 13 that becomes the lower electrode of this stacked capacitor in order to increase the capacitance of the capacitor, the problem of stringer generation is eliminated, and this polycrystalline silicon
Etching of the i-film 13 can be easily performed. Furthermore, since there is no need to increase the thickness of the polycrystalline 51M13, it is possible to prevent the surface level difference from becoming too large. Furthermore, the process is simpler than the conventional method of forming the lower electrode into a fin shape.

Note that the above-mentioned spacer film 10 is made of polycrystalline 5ill.
Any material can be used as long as it can be selectively etched with respect to 1115, 1115 and high melting point metal silicide. Specifically, in addition to 5NOx#, for example, a non-doped polycrystalline Si film, and even molybdenum ( Mo) membrane or W
It is possible to use a metal film such as a film. spacer s
When using these 60 films or W films as the film 10, for example, a nitric acid-based etching solution can be used. Further, instead of the polycrystalline Si film 11, it is also possible to use, for example, a high melting point metal silicide film.

4, 5, and 6 show a MOS dynamic RAM according to a second embodiment of the present invention. Here, FIG. 4 is a plan view, FIG. 5 is a sectional view taken along the line V-VX in FIG.
FIG. 6 is a sectional view taken along the line ■-■ in FIG. 4.

As shown in FIGS. 4, 5, and 6, in the MOS dynamic RAM according to the second embodiment, word lines WL, , WL, , WL, , WL.

When viewed in the longitudinal direction, both ends of the polycrystalline 5ilII 13 constituting the lower electrode of the stacked capacitor have an inverted shape. Further, numerals 18 and 19 respectively indicate a Sm0g film and a Si2N4 film, both of which are interlayer insulating films.

Next, the MOS dynamic RAM according to the second embodiment
The manufacturing method will be explained.

As shown in FIGS. 7 and 8, first, the field oxide film 2, the gate oxide M3, the word lines W L IWL, , WL
, , WL, and semiconductor region 7.81], C
Si(')2 films 18 and 5i3N are formed on the entire surface by VD method.
The a film 19 is sequentially formed. Step 6: After forming a spacer film 20 such as a 5iOz film on the entire surface by CVD, this spacer film 20 is patterned by etching into the shape shown in FIG. 8 (see FIG. 4 for the planar shape). . Also, this spacer! The planar shape of 20 is determined by 2'2'' as necessary.

Next, as shown in FIGS. 9 and 10, Si.

Contact holes C, C2 are formed by removing predetermined portions of the N4 film 19 and the 5iOz film 18 by one length. Next, a polycrystalline Si film 13 is formed on the entire surface by the c v 1111) method.
7, and after doping this polycrystalline Si film 13 with an impurity such as P to lower its resistance, this polycrystalline Si film 13 is
ll:13 is patterned by etching into the shape of the lower electrode of the stacked capacitor. As a result, a polycrystalline Si film 13 is formed as a partial electrode, and both ends of the word lines WL, , WL, , WL3°WL have an inverted shape when viewed in the longitudinal direction.

In the next step C, after removing the spacer film 20 by -1° by wet etching, the insulating film 14 is formed on the polycrystalline Si film 131, as shown in FIGS. Furthermore, the polycrystalline Si of the upper electrode LL7
A stacked capacitor is formed by forming a film IS.

Thereafter, as in the first embodiment, the interlayer insulating film 16, the contact hole C1 and the via line (line B1.,
, 4h to form the desired MOS dynamic RA
Complete M.

As described above, according to the second embodiment, after forming the spacer film 20 so as to surround the memory cell portion, the lower part of the stacked capacitor is formed. A polycrystalline Si film 13 serving as a pole is formed and this polycrystalline Si film 13 is tanned to form word lines WL, , WL,.

Wl, 3. When viewed in the longitudinal direction of W1, 4, both ends form a lower electrode having an inverted letter shape, so the effective surface area of this lower electrode is increased by the contribution of the surface area of this inverted I7 shaped part. It gets bigger over time. Therefore, the effective area of the stacked capacitor becomes large, and therefore the capacitance of the stacked capacitor can be increased to one minute. This makes it possible to improve soft error resistance. Furthermore, the method according to the second embodiment is similar to the conventional star
Compared to the manufacturing method of a closed gear pacita cell type MOS dynamic RAM, only a step of forming a spacer film 20 is added, and the number of steps does not increase much.

FIGS. 11, 12, and 13 show a MOS dynamic RAM according to a third embodiment of the present invention.

Here, Fig. 11 is a plan view, and Fig. 12 is x■ in Fig. 11.
A cross-sectional view along the -xm line, Figure 13 is xm of Figure 11.
FIG. 3 is a cross-sectional view along -xm.

As shown in FIGS. 11, 12, and 13, in the MOS dynamic RAM according to the third embodiment, when considering a certain memory cell, a word that is not for selecting this memory cell is line, i.e. the first
Word lines WL I, Wl4 when viewed in the cross section shown in Figure 2
A portion of the field oxide film 2 that is located above the field oxide film 2 is floating by a predetermined height from the field oxide film 2. Therefore, the polycrystalline Si film 13 constituting the lower electrode of the stacked capacitor is also connected to the outer periphery of these floating word lines WL, , WL through an interlayer insulating film j2 such as a Sin film. It is also formed on the field oxide film 2 below these word lines WL, , WL.

Next, the MOS dynamic RAM according to the third embodiment
The manufacturing method will be explained.

As shown in FIGS. 14 and 15, first a field oxide film 2 is formed and then Si is deposited on the entire surface by CVD.
3N4 film (not shown) is formed. Next, a spacer film 21, such as a SiO□ film, is formed over the entire surface by CVD.
After forming the spacer film 21, the spacer film 21 is patterned by etching into the shapes shown in FIGS. 14 and 15 (see FIG. 11 for the planar shape). This spacer I! 2
1, the film thickness is at least the polycrystalline Si film 13 as the lower electrode, the insulator 1114, and the polycrystalline Si film as the upper electrode in the portion between the word lines WL, , WL and the field oxide film 2 below them. The film 15 is chosen such that a stacked capacitor consisting of the film 15 is formed. Next, the above Si:+N− film is oxidized by thermal oxidation, and the gate oxidation M3 is
form. Next, a polycrystalline Si film is formed on the entire surface by the CVD method, and after doping the polycrystalline Si film with an impurity such as P to lower the resistance, the polycrystalline Si film is patterned into a predetermined shape by etching. word line WL
t, WLz, W'l-3.

WL is formed. Here, when viewed in cross section in FIG. 14, the word lines WL, , WL are formed on the spacer film 21.

Next, by etching the entire surface, the spacer M21
After removing the word lines WL+, WL+, by performing thermal oxidation, for example, as shown in FIGS.
An interlayer insulating film 12, such as a 5iOz film, is formed on the surfaces of z, WLs, and WL-. Next, gate oxide film 3
A contact hole C+ is formed by etching a predetermined portion of
, Cz. Next, a polycrystalline Si film is formed on the entire surface by the CVD method, and after doping this polycrystalline Si film with an impurity such as P to lower the resistance, the polycrystalline Si film is etched to form the lower electrode. pattern. Next, after forming an insulating film 4 on the polycrystalline 51M1a, a polycrystalline Si film 15 is formed as an upper electrode to form a stacked capacitor.

Thereafter, an interlayer insulating film 16, a contact hole C3, and a bit line BL are formed to complete the intended MOS dynamic RAM.

As described above, according to the third embodiment, when considering a certain memory cell, the word line (for example, word line Wl7.) adjacent to the word vA (for example, word line Wl7.) for selecting this memory cell The part of wi, 4) on field oxide film 2 has a floating structure from 2 to field oxide 11, so the lower electrode of the stacked capacitor and the polycrystalline 5illia of L7 are connected to this floating part. The field oxide film 2J is also formed on the outer periphery of the word line and on the lower side of the word line. For this reason,
The effective surface area of this lower electrode is extremely large compared to the conventional one. Therefore, the effective area of the stacked capacitor increases accordingly, and the capacitance of the stacked capacitor can be sufficiently increased. Moreover, the method according to the third embodiment is similar to the conventional stacked capacitor cell type MOS.
Compared to the manufacturing method of dynamic RAM, the spacer film 21
The only additional step is to form the , and the increase in the number of steps is small.

FIG. 16 shows a MOS dynamic RAM according to a fourth embodiment of the present invention.

As shown in FIG. 16, M, OS according to this fourth embodiment
In the dynamic RAM, word lines WLI, W
La, WLs, and WLa have a U-shaped cross-sectional shape, and the film thickness is small at the center and thick at both ends. And polycrystalline 5il as the bottom electrode
lI13 is a word line WL+ whose cross section is U-shaped.
, WLt , WL,s , Wl, , -.

Next, the MOS dynamic RAM according to the fourth embodiment
The manufacturing method will be explained.

As shown in FIG. 17A, first, field oxidation Wj! 2
After forming, for example, Si3N,
A film 22 is formed. Next, a portion of the S i :I Na film 22 formed on the active region is removed by etching. Next, the entire surface is coated with, for example, 5iO by the CVD method.
After forming a spacer film 23 such as a Z film, this spacer film 23 is connected to a word line WL1. WLz, Wl3
, Wl4 is patterned by etching. Next, the word line WL+ is
, Wl2, Wl3.

Gate oxide film 3 is formed on the surface of the active region between Wl4. Next, the entire surface is coated with, for example, polycrystalline S by the CVD method.
An i film 24 is formed 1, and this polycrystalline Si film 24 is coated with, for example, P.
The resistance is lowered by doping with impurities such as. Next, as a film for surface flattening, for example, spin-on glass (SO
G) After applying the film 25 to the entire surface and flattening the surface, etching back is performed in a direction perpendicular to the substrate surface by the RUE method until at least the spacer WX23 is exposed. After this,
For example, the 5OGllI 25 and the spacer film 23 are etched away by wet etching. By this,
As shown in FIG. 17B, a U-shaped cross-sectional shape is
'7-)' line WL,, WLz, wt, v WL4
is formed. After this, an n-type impurity such as P is ion-implanted into the semiconductor substrate 1 at a low concentration.
, WL, for example, n-type semiconductor regions 25, 26, 21 are formed in a self-aligned manner.

Next, after forming, for example, 5iOzllW on the entire surface by CVD, this Si0g film is etched in a direction perpendicular to the substrate surface by, for example, RIE. This allows the first
As shown in Figure 7C, the word lines WL, , WL, , WL,
, WL, sidewall spacers 6 are formed on the side walls of , WL. Next, by a thermal oxidation method, a gate oxide [3] is formed on the surface of the semiconductor substrate 1 exposed by etching by the above-mentioned RIE method. At the same time, the word lines WL, , WL
, , WL, , the glabellar insulating film 12 is formed on WL.

Next, using these sidewall spacers 6 and word lines WLI, WLz, WLs, and WL4 as masks, n-type impurities such as As are ion-implanted into the semiconductor substrate 1 at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities. As a result, as shown in FIG.
．． 9 is formed. Next, gate oxidation [l! 30 predetermined portions are etched and removed to form contact holes C and C.

form. Next, a polycrystalline Si film 13 is formed on the entire surface by the CVD method, and after doping the polycrystalline Si film 3 with an impurity such as P to lower the resistance, the polycrystalline Si film 13 is
The film 13 is patterned by etching into the shape of the lower electrode of the stacked capacitor. Next, this polycrystalline Si
Insulation II on film 13! ! After forming the polycrystalline Si film 14, a stacked capacitor is formed by forming a polycrystalline Si film 15 as an upper electrode.

Thereafter, an interlayer insulating film 16, a contact hole C3, and a bit line BL are formed to complete the intended MOS dynamic RAM.

As described above, according to this fourth embodiment, word III
Since the cross-sectional shapes of WLI, WLz, WL3, and WLa can be made into a U-shape, polycrystalline 5iill can be used as the lower electrode of the stacked capacitor that will be formed later.
13 is a word line wi, I having this U-shaped cross-sectional shape.
, WL! , WL3, WL, Ii, has a greatly curved shape along 1 m, and therefore the effective surface area of this lower electrode becomes sufficiently large. Therefore, the effective area of the stacked capacitor becomes large, and therefore the capacitance of the stacked capacitor can be made sufficiently large. However, compared to the conventional manufacturing method of stacked capacitor cell type MOS dynamic RAM, the method according to the fourth embodiment only adds a step of forming the spacer WjI23, etc., and the number of steps does not increase. few.

FIG. 18 shows a MOS dynamic RAM according to a fifth embodiment of the present invention.

As shown in FIG. 18, in the MO>dynamic RAM according to the fifth embodiment, a convex portion 1a having a triangular cross-sectional shape is formed on a semiconductor substrate 1. As shown in FIG. Here, the planar shape of the convex portion 1a is, for example, a rectangle. In this case, the word line W[7. , WL3 are formed on one slope and the other slope of this convex portion 1a, respectively,
Therefore, the upper surfaces of these word lines WL, , WL are inclined with respect to the main surface of the semiconductor substrate l. The polycrystalline Si film I3 extending over these word lines WL2 and WLs, with the bottom as the pole, is also inclined.

Next, the MOS dynamic RA according to this fifth embodiment,
The manufacturing method of M will be explained.

As shown in FIG. 19A, first, the semiconductor substrate 1 is etched to form a convex portion 1a having a triangular cross-sectional shape.
form. Here, the convex portion 1a can be formed, for example, by taking advantage of the fact that the etching rate of wet etching depends on the crystal orientation, or by physically etching the semiconductor substrate 1 using a dry etching method. You can also do this.

Next, as shown in FIG. 19B, after selectively thermally oxidizing the surface of the semiconductor substrate 1 to form a field oxide W12, the surface of the active region surrounded by the field oxide film 2 is thermally oxidized. A gate oxide film 3 is formed by a method. Next, 50 word lines wL, , WL, , WL, l made of a polycrystalline Si film doped with an impurity such as P
, WL, are formed.

Next, these word lines WL,,WL,,WL,.

By ion-implanting n-type impurities such as As into the semiconductor substrate 1 at a high concentration using WL as a mask,
These word lines WL, , WL, Wi, t, wt,
n-type semiconductor regions 7, 8.9 in self-alignment with respect to 4.
form. Next, after forming an interlayer insulating film 12 on the entire surface by, for example, the CVD method, a predetermined portion of the glabellar insulating film 12 is removed by etching to form contact holes C+ and Cz. Next, a polycrystalline Si film 13 doped with an impurity such as P and having a predetermined shape is formed as a lower electrode.

Next, as shown in FIG. 18, an insulating film 14 is formed on the polycrystalline Si film 13, and a polycrystalline 5i is further formed as an upper electrode.
WA15 is formed to form a stacked capacitor.

After that, an interlayer insulating film 16, a contact hole C3, and a contact line BL are formed, and the M o S
Complete Dynamink RAM.

As described above, according to the fifth embodiment, 1, a convex portion la having a triangular cross-sectional shape is formed, and the convex portion 1 passes through the convex portion 1a.↓, -') iZ"Since the lead wires WL, , WL3 have been formed, this protrusion 1
a'-, these word lines Wi, , 2 . The upper surface of WL3 is inclined with respect to one surface of the conductor base &1, and therefore the polycrystalline Si film 13 serving as the f-section electrode extending to these word lines WLt, WL+l, and h is also on the main surface of the semiconductor substrate I. It will be tilted against. Therefore, the effective surface area of the lower electrode increases by that much, so the effective area of the stacked capacitor increases to one minute, and therefore the capacitance of the stacked capacitor can be sufficiently increased.

This makes it possible to improve soft error resistance. Moreover, in the method according to the fifth embodiment, compared to the conventional method for manufacturing a stacked capacitor cell type MOS dynamic RAM, only the formation of the convex portion 1a -1 is added, and the increase in the number of J is extremely large. few.

Furthermore, according to this fifth embodiment, the word line WL! ,
Since WL, s is formed on the slope of the convex portion 1a, an n-channel MO transistor as an access transistor formed by the word line WL and the semiconductor region 7.8) and the word line WL.

The channel length of the n-channel MO3) transistor as an access transistor formed by the semiconductor region 8.9 and the word line WL, respectively.

The dimensions can be made larger than the dimensions of the resist pattern used as a mask when forming Wt by etching. This can make it difficult for the short channel effect to occur.

Furthermore, in this fifth embodiment, since the bit line BL is brought into contact with the semiconductor region 8 at the top of the convex portion 1a, the depth of the contact hole C5 for bringing the bit line BL into contact with the semiconductor region 8 is becomes smaller, and therefore it becomes easier to make contact with the bit line BL.

For example, as shown in FIG. 20, a gate electrode G is formed on the top of a convex portion 1a formed on a semiconductor substrate I, and an n° type semiconductor region 28. as a source region or a drain region is formed on both sides of the gate electrode G. By forming 29, the n-channel MO3! - A transistor can be formed. Further, as shown in FIG. 21, for example, a convex portion 1a having a ρ-triangular cross-sectional shape is formed on the semiconductor substrate 1, and a gate electrode G is formed on the slope of the convex portion 1a. An n-channel MOS transistor can also be formed by forming n-type semiconductor regions 28 and 29 as source or drain regions in the semiconductor substrate 1 on both sides. In addition, in FIGS. 20 and 21, C, , C, represent contact holes, and numerals 30 and 31 represent electrodes.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the first embodiment described above, the word line WL+
, WLz, WLs, and WLa are formed of polycide films, but these word lines Wl, +, WL
z, WL:I, and WL- can also be formed from a polycrystalline Si film doped with impurities. Furthermore, in the second, third, fourth, and fifth embodiments described above, the word lines WL, wt, z, WL3
, WL4 are formed of a polycrystalline Si film doped with impurities, but these word lines WL, , WL, , WL
,, WLJ can also be formed from a polycide film.

Furthermore, in the above-mentioned first example and fourth example,
Although the case has been described in which the n-channel MOS transistor as an access transistor has an LDD structure, it goes without saying that the n-channel MOS transistor as an access transistor does not necessarily have to have an LDD structure. Furthermore, in the second, third, and fifth embodiments described above, the n-channel MO3) transistor serving as the access transistor may have an LDD structure.

C. Effects of the invention] As explained above, according to the first invention, the lower electrode is formed by being bent along the eave structure formed by side etching the spacer film, so that the effective effect of the lower electrode is The surface area becomes larger. Therefore, the effective area of the stacked capacitor becomes sufficiently large, and therefore the capacitance of the stacked capacitor can be sufficiently increased. Moreover, the process is relatively simple.

Further, according to the second invention, since the shape of both ends of the lower electrode when viewed in the longitudinal direction of the word line is inverted, the effective surface area of the lower electrode is increased accordingly, and therefore the stacked capacitor capacity can be made sufficiently large. Moreover, the process is simple.

Further, according to the third invention, since the lower electrode is formed also on the outer periphery of the word line that is floating from the field oxide film and on the field oxide film below it, the effective effectiveness of the lower electrode is increased accordingly. The surface area is increased and therefore the capacitance of the stacked capacitor can be made sufficiently large. Moreover, the process is relatively simple.

Further, according to the fourth invention, since the word line has a U-shape when viewed in a cross section perpendicular to its longitudinal direction, the lower electrode has a largely curved shape along this U-shaped cross section, and therefore The effective surface area of the lower electrode increases accordingly. This allows the capacitance of the stacked capacitor to be sufficiently increased. Moreover, the process is relatively simple.

Further, according to the fifth invention, since the upper surface of the word line formed on the slope of the convex portion formed on the semiconductor substrate is inclined with respect to the main surface of the semiconductor substrate, it is possible to extend the word line onto the word line. The lower electrode formed thereon is also inclined with respect to the main surface of the semiconductor substrate. Therefore, the effective surface area of the lower electrode increases accordingly, and the capacitance of the stacked capacitor can therefore be made sufficiently large. Moreover, the process is simple.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a MOS dynamic RAM according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIGS. 3A to 3C are according to the present invention. FIG. 4 is a plan view of the MOS dynamic RAM according to the second embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line -v of FIG. 4.
7 to 10 are cross-sectional views taken along line VI, and FIGS. 7 to 10 are cross-sectional views for explaining the manufacturing method of a MOS dynamic RAM according to the second embodiment of the present invention in the order of steps. FIG. 11 is a cross-sectional view taken along the line VI. A plan view of a MOS dynamic RAM according to an embodiment,
FIG. 12 is a sectional view taken along xn-XIIwA in FIG. 11, FIG. 13 is a sectional view taken along xm-xm line in FIG. 11, and FIGS. 16 is a cross-sectional view for explaining the manufacturing method of the MOS dynamic RAM according to the embodiment; FIG. 16 is a cross-sectional view of the MOS dynamic RAM according to the fourth embodiment of the present invention; FIGS. 17A to 1.7C;
is a MOS dynamic RAM according to a fourth embodiment of the present invention.
18 is a cross-sectional view for explaining the manufacturing method in order of steps, and FIG. 18 is a MOS dynamic RAM according to a fifth embodiment of the present invention.
FIG. 19 [NA and FIG. 19B are cross-sectional views of
20 and 21 are cross-sectional views for explaining the manufacturing method of the MOS dynamic RAM according to the embodiment in the order of steps).
FIG. 3 is a cross-sectional view showing an example of forming an Ios transistor having a gate electrode. Explanation of main symbols in the drawings 1: Semiconductor substrate, 2: Field oxide film, 3: Gate oxide film, WL++, WLz, WL, l. WL4: word line, 7, 8, 98 semiconductor region, 1.0
, 20, 21. 23 Ni spacer film, 12: Glabella insulating film,
13: Polycrystalline Si film (lower electrode), 14: Insulating film, 15: Polycrystalline Si film (earth electrode), 24: Polycrystalline 5ill, 25: SOG film, C,,C,,
C: contact hole, BL: bit line. Figure 3 A Manufacturing method Figure 3 C Counting method C No. 40 V-axis, one side one side) Manufacturing method (η
4(2) Vl-Vl connected cross section In) 8th figure drawing method (V-V line folding plane opening of Yu 4I71) 9th figure Exhibition 1 (direction; t (4th tZlnv+-vlaM+it+F
]) Fig. 19 53T) k i9su (,, vif, fi) Fig. 11' PJf i Fig. fi ) No. 14
Figure 1) Lid left method (X1l-Xlll stitched folded view of pattern) Figure 15 - +1η X1ll -Xll Construction method Figure 17 A 5T Ai Like Creation Figure 18 χ 7 method Figure 19 A Rebellion 7y ta Figure 19 B It='s Ijiri pole 2. N figure says seven examples? Figure 1

Claims (5)

[Claims] (1) In a method of manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, a conductive film for forming a word line, a spacer film, and a predetermined a step of sequentially forming a film on the entire surface; a step of sequentially patterning the predetermined film, the spacer film and the conductor film for forming the word line into a predetermined shape; a step of side etching the spacer film; a step of forming a conductor film for forming a lower electrode of the capacitor over the entire surface; a step of forming the lower electrode by patterning the conductor film for forming the lower electrode; and a step of forming the lower electrode on the lower electrode through an insulating film. A semiconductor memory comprising the steps of: forming a conductor film for forming an upper electrode of the stacked capacitor; and forming the upper electrode by patterning the conductor film for forming the upper electrode. Production method. (2) In a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, after forming a word line constituting the gate electrode of the MIS transistor, a spacer film is formed on the entire surface. patterning the spacer film into a predetermined shape such that both ends of the lower electrode of the stacked capacitor extend thereon when viewed in the longitudinal direction of the word line; and a conductor for forming the lower electrode. a step of forming a film on the entire surface; a step of forming the lower electrode by patterning the conductor film for forming the lower electrode; and a step of forming the upper electrode of the stacked capacitor via an insulating film on the lower electrode. A method for manufacturing a semiconductor memory, comprising: forming a conductor film; and forming the upper electrode by patterning the conductor film for forming the upper electrode. (3) A method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, comprising: forming a field oxide film and then forming a spacer film over the entire surface of the MIS transistor; patterning the spacer film into a predetermined shape extending at least over the field oxide film when viewed in a direction perpendicular to the longitudinal direction of the word line constituting the gate electrode; and forming the word line; a step of removing the spacer film; a step of forming an insulating film on the word line; a step of forming a conductor film for forming the lower electrode of the stacked capacitor over the entire surface; and patterning the conductor film for forming the lower electrode. forming the lower electrode by forming the lower electrode; forming a conductor film for forming the upper electrode of the stacked capacitor on the lower electrode via an insulating film; and patterning the conductor film for forming the upper electrode. A method of manufacturing a semiconductor memory, comprising the step of forming the upper electrode. (4) In a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, after forming a field oxide film, a method is applied to a word line constituting the gate electrode of the MIS transistor. forming a film that can be selectively etched over the entire surface; patterning a film that can be selectively etched with respect to the word line in the shape of an inverted pattern of the word line; and forming a conductive film for forming the word line over the entire surface. a step of forming a surface flattening film over the entire surface; and etching back in a direction substantially perpendicular to the surface of the semiconductor substrate until at least a film that can be selectively etched with respect to the word line is exposed. a step of forming the word line by performing a step of removing the film for surface flattening and a film that can be selectively etched with respect to the word line, and a conductor film for forming a lower electrode of the stacked capacitor. a step of forming the lower electrode by patterning the conductor film for forming the lower electrode, and a step of forming the upper electrode of the stacked capacitor with an insulating film on the lower electrode A method for manufacturing a semiconductor memory, comprising the steps of: forming a conductor film; and forming the upper electrode by patterning the conductor film for forming the upper electrode. (5) In a method for manufacturing a semiconductor memory having a memory cell consisting of one MIS transistor and one stacked capacitor, a protrusion having a slope inclined with respect to the main surface of the semiconductor substrate is formed on the semiconductor substrate. forming a word line constituting the gate electrode of the MIS transistor on the slope of the convex portion via a gate oxide film; and forming a conductor film for forming the lower electrode of the stacked capacitor on the entire surface. forming the lower electrode by patterning the conductor film for forming the lower electrode; and forming the conductor film for forming the upper electrode of the stacked capacitor on the lower electrode via an insulating film. and forming the upper electrode by patterning the conductive film for forming the upper electrode.