JPH0458070B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention makes it possible to simulate the operation of a hard logic simulator device, particularly a logic device consisting of a combination of a large number of gates, using dedicated hardware. This invention relates to a hard logic simulator device.

(2) Background and issues When designing a new logic device with a large number of gates, such as an LSI, it is important to check whether the designed logic device operates normally and whether it has the desired functionality. In order to check whether the device is working or not, the operation of the logic device is simulated on a computer before it is actually manufactured. Conventionally, this logic simulation uses a software program to calculate how the state of a gate output signal line (hereinafter referred to as a net) changes due to a change in the input to each gate (hereinafter referred to as an event). This was done by performing calculations in sequence. However, when processing is performed by software using a general-purpose computer, it is not possible to process and obtain the state changes of each net in parallel, and the commands must be fetched one after another and executed one by one. Therefore, there was a problem in that the simulation required a very long processing time. In particular, as logic devices become more multifunctional and integrated in recent years,
The above-mentioned processing time problem is becoming more prominent.

(3) Purpose of the invention The present invention aims to solve the above problems and provides an architecture for a dedicated machine for a logic simulator.
The aim is to significantly improve the processing time required for logical simulation.

(4) Structure of the Invention In order to achieve the above object, the present invention parallelizes access to various memories that store input/output state changes of each gate of a simulated logic device,
The hard logic simulator device of the present invention focuses on pipelining processing, and the hard logic simulator device of the present invention is a device that simulates the operation of a logic device consisting of a combination of a large number of gates. a new event memory in which is registered, a new status memory in which the output state of the gate is stored corresponding to each of the above gates, and a fan out gate address in which the fanout gate address is stored in correspondence to each of the above gates. an input vector memory in which the input state to each gate is stored for each gate in the new status memory; A dictionary memory in which an output state value related to a logical operation according to an input value is defined, and address information of a position in the dictionary memory where an output state value according to the type of each gate is defined, - The address information used for referencing the dictionary memory together with the contents of the vector memory includes the new status and a dictionary address memory stored corresponding to the arrangement of gates in the memory,
Each of the above memories is configured to be accessible in parallel, and the new status memory and the fanout memory are referenced based on the contents of the new event memory, and the input vector memory is referenced based on the contents of the new event memory. said dictionary, the contents of which are configured to be updated by information in said new status memory and said fanout memory, and determined by the contents of said input vector memory and a corresponding said dictionary address memory; It is characterized in that it is configured to simulate the contents of the memory as a new gate output. Embodiments will be described below with reference to the drawings.

(5) Embodiments of the Invention Figure 1 is a diagram for explaining the logical data structure of an embodiment of the present invention, Figures 2 and 3 are diagrams for explaining the data structure shown in Figure 1, and Figure 4 is a diagram for explaining the data structure shown in Figure 1. A block diagram of the structure of an embodiment of the present invention, and FIGS. 5 to 8 are diagrams illustrating the operation of an embodiment of the present invention.

In the figure, 1 is the new event memory (NEM), 2 and 3 are registers, and 4 is the new event memory (NEM).
Status memory (NSM), 5 is input
Vector memory (IVM), 6 is not memory (NOT), 7 is dictionary address memory (BEA), 8
is an adder, 9 is a dictionary memory (EVM), 10 is a fan-out pointer memory (FOP), 11 is a fan-out memory (FOM), and 12 is an event memory.
Gate buffers (EGB), 13 and 14 represent registers. In FIGS. 2 and 3, 16 and 17 represent gates. Also, in Figure 4, 20
32 to 32 are registers, and 33 to 34 are exclusive OR (EOR) circuits.

In Figure 1, NEM1, NSM4, IVM5,
NOT6, BEA7, EVM9, FOP10, FOM1
Each memory, such as 1, is comprised of, for example, a random access memory (RAM).

NEM1 is a memory in which gate information regarding an event net, that is, a signal line whose state has changed, and its new state information are registered in association with each other. For example, if the number of gates can be processed up to 4096, the event net area will be divided into 12-bit units and the maximum number of events (for example,
1024 pieces) will be prepared. The status of each net is "0"
(L level) state, “1” (H level) state,
Since it takes either the "X" state (undefined as "1" or "0") or the "Z" state (high impedance), each state is represented by 2 bits. The start address (Nhead) of the currently active event net is indicated by register 2, and the end address (Ntail) is indicated by register 3.

The NSM 4 is a memory that stores and holds the states of all gates of the logic device that is the subject of simulation. Two bits are assigned to each gate in the order of arbitrarily assigned gate numbers to indicate the output state of each gate. The IVM 5 is a memory that stores the input state to each gate corresponding to each gate shown in the NSM 4. Assuming that up to seven inputs are possible for each gate, 14 (=7×2) bits are prepared for each gate.

NOT6 is a memory provided with one bit for each gate in order to save EVM9 to be explained later by half. For example, if the input of the gate 17 shown in FIG. 3A and the input of the gate 17' shown in FIG.
This is to define only one output state value in the EVM 9 when there is a relationship such as a gate and a NAND gate. If the value of NOT6 is "0", the contents of EVM9 are used as is,
When the value of NOT6 is "1", the contents of EVM9 are inverted and used.

BEA7 is a memory in which an address value determined by the attribute of each gate is stored for each gate, and the address value is the beginning of the area where all output state values of that gate for EVM9 are stored. Indicates an address.

EVM9 is a memory that defines the output state determined by the input to each gate for each gate attribute, and contains the contents of BEA7 corresponding to each gate and the IVM
5 are added by the adder 8, and referenced by the address determined by the output result.

FOP10 stores the output destination gate information for each gate of NSM4.
This is a memory that holds and points to addresses within the FOM11. FOM11 is referenced by FOP10. For each gate, FOM11 stores the gate address for the gate that becomes the fanout of that gate, that is, the gate number in NSM4, and input number information indicating which input terminal of the output destination gate the output is input to. has been done. This input number information corresponds to the bit position of IVM5. Assuming that the average value of the fan-out of each gate is, for example, "3", three times as many entries as the number of gates are provided, and 12288 (=4096×3) entries are prepared. The end of fanout for one gate is indicated by the first check bit of each entry. If this bit is “1”,
Indicates the end. For example, when the gate connections are as shown in FIG. 2, the fanout of the gate 16 is 4, and the gate address of the output destination is made known by the FOM 11 pointed from the FOP 10. . For example, looking at the third output gate 17C, it can be seen from the FOM 11 that the output of the gate 16 is input to the second input terminal of the gate 17C. EGB12
is the gate information to be processed when FOM11 is referenced in the first processing phase.
This is a memory that is copied from the FOM 11 and stored for use in the second processing phase. The starting and ending locations of the stored valid gate addresses are in register 13 and register 14, respectively.
It is shown by.

Now, the calculation procedure of the logical simulation will be briefly explained. This logic simulator uses an algorithm called the event method, and uses a unit delay model in which it takes one unit time for an event (change in signal) that occurs at the input of a gate to be transmitted to the output.

What the logic simulator should do is (1) extract the state change (event) of a signal line at a certain time from NEM1 (hereinafter referred to as processing (1)), and (2) extract the state change (event) of the signal line from NEM4, which maintains the state of the signal line. to update the contents of the file to a new state (hereinafter referred to as processing
(2)).

(3) A gate that has the change as an input (the gate after the change is extracted using FOP10 and FOM11 (hereinafter referred to as processing (3)), (4) the contents of IVM5 that holds the input value of the gate are Update it to a new input value, and then open that gate once.
Storing and accumulating in the buffer of EGB12 (hereinafter referred to as process (4)).

(5) In order to determine whether the state change of the signal line that occurs at the input propagates to the output
Read such gate from 2 and IVM5
new input value, NOT6 output value inversion information, EVM
This is done using offset information for accessing the truth table of 9 and the truth table of BEA7 (hereinafter referred to as processing).
(5)), (6) If a change occurs, it is registered in NEM1 as a new event at the next time (hereinafter referred to as process (6)).

The overall block configuration is as shown in FIG. In Figure 4, the start of the simulation is first determined by the contents of registers 2 and 3, which point to the event net of NEM1.
This is done by reference to NEM1. The event net stored in NEM1 and the state value given to that net are read into register 20 and register 21, respectively. The FOP 10 is referenced by the contents of the register 20, and
When NSM4 is accessed, the contents of register 21 are set to NSM4 as the output state of its corresponding gate.
is set to

Here, NEM1 shown in Figure 4, register
Nhead2 and Ntail13 are shown in Figure 1, respectively.
Compatible with NEM1, Nhead2, and Ntail3.
As mentioned above, NEM1 holds the gate information regarding the signal line whose state has changed and its new state information, and the range that it holds is NEM1.
Registers Nhead2 to Ntail that give addresses to
It is shown as 3.

Data in this range is read and gate information (event net) is stored in register enet20.
Then, new status values are sequentially set in the register news21. This process is the process (1) described above as what the logic simulator should perform.

Using this enet20 value as an address, NSM4
By writing the contents of news21 into , the above-mentioned process (2) is executed.

The value of enet20 also serves as the address for FOP10, and the above-mentioned process (3) is started.

When the content of FOP10 is "0", it indicates that there is no fanout, but since there are usually several fanouts, the content is read to register 22 and FOM11 is referred to. The check bit, which is the contents of FOM 11, is set in register 23, the input number is set in register 24, and the gate address is set in register 25. The gate information set in the register 25 is stored for later access at the address location of the EGB 12 pointed to by the value obtained by adding "1" to the contents of the register 14. On the other hand, register 25
According to the contents of , the status information of the register 21 is set in the IVM 5 for the gate indicated by the contents, based on the input number of the register 24.
At this time, the contents of the register 23, that is, the check
If the bit is 0, "1" is added to register 22, FOM11 is similarly referred to, and check is performed.
The processing is repeated until the bit becomes "1" and all fan-out processing is completed. Note that when the check bit in the register 23 becomes 1, processing of the next event net is started and is similarly processed in parallel.

“Here, FOP10 and FOM11 shown in Figure 4
are FOP10 and FOM1 shown in Figure 1, respectively.
It corresponds to 1. Since these hold the contents as explained according to FIG. 1, the above-mentioned process (3) is executed by the operation explained here using FIG.

Similarly, IVM5, EGB12 shown in FIG.
ehead 13 and etail 14 correspond to those with the same name shown in FIG. The valid range of data stored in the EGB 12 is shown as ehead 13, which gives an address to the EGB 12, to etail 14. IVM
The above-mentioned process (4) is executed for EGB 5 and EGB 12. Also, regarding process (5) and process (6) above,
It is executed as follows.

It was memorized in EGB12." The points from the register 13, which are initialized so that the gate address indicates the beginning, are sequentially read into the register 25. The contents of IVM5 are read to register 27 according to the contents of register 25, and the corresponding
The contents of BEA7 are read into register 26.
Further, the contents of the corresponding NSM4 are read to the register 29 by the register 25, and the contents of the register 25 are transferred to the register 32-1.

Next, the contents of register 26 and register 27 are
Adder 8 adds the result, and the result is stored in register 28.
is set to . At that time, register 32-1
The contents of are transferred to register 32-2. Registers 32-1 to 32-5 are for synchronizing parallel processing. Thereafter, the contents are sequentially transferred from register 32-2 to register 32-5 at each timing.

The EVM 9 is referenced based on the contents of the register 28, and a new output state of the gate currently being processed is determined. Note that if NOT6 indicates "1", the result is inverted by the EOR circuit 34, and the result is set in the register 21. Next, the contents of register 21 and register 29 are compared by EOR circuit 33. That is, a comparison is made to see if there has been a change in the gate output of the NSM 4, and the result is stored in the register 30. On the other hand, the contents of register 21 are transferred to register 31-1 and register 32 is transferred to register 31-1.
The contents of -3 are transferred to register 32-4. When the contents of register 30 are not 0, that is, when there is a change in the output of the gate, "1" is added to the contents of register 3, and register 32-
4 to register 32-5, and register 3
The contents of 1-1 are transferred to register 31-2. Then, the contents of the register 32-5 and the contents of the register 31-2 are written to the position of NEM1 indicated by the register 3. In other words, a new event net and its status have been registered in NEM1.

Similarly, the process for the gates stored in the EGB 12 is repeated. Furthermore, by repeating the same process for event nets newly registered in NEM1, it will be possible to easily determine whether the designed logical device is operating correctly based on the contents of NEM1.

Next, referring to FIG. 5, the operation of the first phase will be described in relation to cycle time.

(o) As an initial setting, in cycle 0○, register 2
and sets "-1" in register 14.

Add "1" to register 2 in the () cycle. In this operation, the contents of register 23 are "0".
It starts when the value changes from 1 to 1.

In the () cycle, the event net of NEM1 and its state indicated by the contents of register 2 are read into registers 20 and 21. Note that the final position of the event net is stored in advance in register 3, and this processing is performed when the values in register 2 and register 3 do not match.

In the () cycle, the FOP 10 is referenced by the register 20 and the address of the FOM 11 is read into the register 22. Also, N.S.M.
The new state information of the register 21 is written to the position of the gate to be processed No. 4. register 23
is set to "0".

() In the next cycle, when the contents of the register 22 are not "0", the FOM 11 is accessed and the information corresponding to the registers 23, 24 and 25 is read. “1” is added to the register 14.

In the () cycle, the contents of the register 21 are written to the position of IVM5 indicated by the register 25. Note that the output of the register 24 is used as a chip select signal to determine the position of the input terminal. EGB1 indicated by register 14
The contents of register 25 are stored in position 2.
If the value of the register 23 is "0", "1" is added to the register 22.

The above processing () and processing () are repeated until the contents of the register 23 change to "1".
Note that when the contents of the register 23 change to "1", processing () is started, and processing for the next event net is performed in parallel. That is, as shown in FIG.
The process of is repeated by the number of fanouts, and the final one is processed in parallel with the process of cycle , thereby reducing the processing time.

Next, the second phase will be explained with reference to FIG.

() In the cycle, register 3 and register 13 are set to "-1".

Add "1" to register 13 in () cycle.

() In the next cycle, the contents of EGB 12 are read to register 25 based on the value of register 13, provided that the values of register 13 and register 14 do not match. register 1
``1'' is added to the contents of 3.

In the () cycle, based on the contents of the register 25, the contents of the IVM5 and BEA7 are read into the register 27 and the register 26, respectively. Also, the state information before NSM4 is
It is saved in the register 29. The contents of register 25 are transferred to register 32-1.

In the () cycle, addition of registers 27 and 26 is performed by adder 8, and the address to EVM 9 is stored in register 28. The contents of register 32-1 are transferred to register 32-2.

In the (xi) cycle, EVM9 is referenced and new output status information is set in register 21. The contents of register 32-2 are register 3
Shifted to 2-3.

(xii) In the cycle, the contents of register 21 and register 29 are compared in EOR circuit 33,
The result is set in register 30. The contents of register 21 are transferred to register 31-1, register 3
The contents of 2-3 are shifted into register 32-4.

() In the cycle, when the value of register 30 is not "0", the contents of register 3 are counted up by "1", and register 32-
The contents of 4 are sent to register 32-5 and register 31
The contents of -1 are shifted to register 31-2.

In the () cycle, the contents of register 32-5 and register 31-2 are stored in the location of NEM1 indicated by register 3.

As shown in FIG. 8, the processing of the next event stored in the EGB 12 is started in parallel from process() when the first event enters the cycle, and all events stored in the EGB 12 are processed in parallel. The processes from process() to process() are repeated until the process for is completed.
In particular, in the second phase, the degree of multiplicity of parallel processing is large, and processing can be performed at extremely high speed compared to the case where processing was performed serially using conventional software.

``Next, a simulation example of a specific circuit will be explained according to FIGS. 9 to 11.

For example, assume that the operation of a logic circuit as shown in FIG. 9 is simulated. In FIG. 9, g1 to g7 are gates, especially g1 to g
3 is buffer (BUF), g4 is inverter (INV), g5 and g6 are and gate (AND),
g7 is an or gate (OR).

The EVM 9 stores information as shown in FIG. 10 in advance.

That is, a truth table is stored for each type of gate such as inverter, AND, OR, etc. In this example, for the inverter,
From address 200 of EVM9, regarding and,
Stored starting from address 300 of EVM9.

Each input and output status value is represented by 2 bits, and “0” (L level) is “00”, “1” (H level) is “11”, and “X” (undefined value) is “01”. ”, “Z”
(high impedance) is represented by “10”.

For example, in the case of an inverter, the truth table is the 10th
As shown in the figure (b), when the input is 0, the output is 1, when the input is 1, the output is 0, and when the input is X and Z, the output is X, so the truth value of the inverter in EVM9 In the table storage section, 1, X, X, and 0 are stored as output state values according to the input value.

Information regarding the fan-out of each gate g1 to g7 shown in FIG. 9 is managed by the FOP 10 and FOM 11, as shown in FIG. 11A.
The output destinations of the gate g1 are the No. 0 input terminal of g5 and the No. 0 input terminal of g4. Check
A check bit of "1" indicates the end of fan-out for each gate. The output destination of g2 is
This is the first input terminal of g5. Fan-out information is similarly set for the others.

Now, consider a state in which an event (0→1) occurs at g1 when the output values of gates g1, g2, and g3 are 0, 0, and 1, respectively.

In NEM1, as shown in Figure 11,
It is written that g1 has become 1.

As shown in FIG. 11D, the entry portion indicated by address g1 of NSM4 is updated from 0 to 1.

At the same time, the event of g1 causes FOP10 to
and FOM11, and EGB12 has the 11th
As shown in Figure C, the fan out of g1
Gates g5 and g4 are stored.

Furthermore, the values of the input vectors g5 and g4 in IVM5 are changed from 00 to 10 and from 0 to 1, respectively.

When this process is finished, information on g5 and g4 is read from the EGB 12. For example, in the process for g4, BEA7 reads out the start address 200 where the truth table of the inverter (INV) is stored. A new value "1 ("11" in 2-bit status display)" is read from IVM5. From these values, the address of EVM9 to be referenced is 200 + (value representing signal value 1) = 200 + 3
(referring to “11”) = address 203. If you access this, you will get an output of "0" for an input of "1". On the other hand, since the old value "1" of g4 is written in NSM4, the occurrence of the event is recognized.

The event that g4 became "0"
It is written to NEM1 and the simulation continues for this.

As described above, the simulation will be executed. ”.

(6) Effects of the Invention As explained above, according to the present invention, logic simulation can be executed and processed at extremely high speed by a dedicated machine. In logic simulation, more than 95% of processing is spent on RAM access, and processing speed depends on element speed and processing parallelism. If we calculate the RAM access time as a slightly slower 200 nanoseconds, we get the following.

The number of events is e, and the average number of fanouts is f.
shall be. As shown in FIG. 6, in the first phase, the final fan-out cycle,
Since the next gate cycle can be processed in parallel, the processing time _T1 is as follows.

T ₁ =1+(5+(f-1)×2-2)e+2=e
(f+1)+3 Also, in the second phase, as shown in FIG. 8, cycle ~ and cycle ~ are
Since it will be processed in parallel, the processing time T ₂
becomes as follows.

T ₂ =3ef+5 Therefore, the entire processing time T is: T=T ₁ +T ₂ =e(f+1)+3+3ef+5 =e(4f+1)+8.

The processing time for one event is T/e=4f+1+8/e≒4f+1, and if the average number of fanouts f is 3 and the RAM access speed is 200 nanoseconds, it takes about 2.6 microseconds to process one event. It will take seconds. This corresponds to 10 times the performance of processing using software on a large general-purpose computer, for example, and has a significant effect on speeding up processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the logical data structure of one embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the data structure shown in FIG. 1, and FIG. 4 is a configuration block diagram of one embodiment of the present invention. 5 to 8 are diagrams for explaining the operation of an embodiment of the present invention, FIG. 9 is an example of a circuit for explaining the operation of the simulation, and FIG. 10 is a dictionary memory according to an embodiment of the present invention. (EVM) configuration example, FIG. 11 shows an explanatory diagram of the operating state according to the embodiment of the present invention. In the figure, 1 is a new event memory, 4 is a new status memory, 5 is an input vector memory, 7 is a dictionary address memory, 8 is an adder, 9 is a dictionary memory, and 11 is a fanout memory.
Represents memory.

Claims (1)

[Scope of Claims] 1. A device for simulating the operation of a logic device consisting of a combination of a large number of gates, including a new event memory in which at least an event net and a new state of the net are registered, and a memory corresponding to each of the above gates. a new status memory in which the output state of the gate is stored; a fanout memory in which the gate address of the fanout is stored corresponding to each of the above gates; An input vector memory stores the input state to the gate, and for each type of gate to be simulated, the output state value associated with the logical operation corresponding to each input value to that gate is defined. Address information of the dictionary memory where the input vector memory is located and the location where the output state value corresponding to the type of each gate in the dictionary memory is defined, and is used to refer to the dictionary memory together with the contents of the input vector memory. and a dictionary address memory in which address information to be displayed is stored in correspondence with the gate arrangement in the new status memory, and each of the memories is configured to be accessible in parallel, and the new event - The new status memory and the fanout memory are referenced based on the contents of the memory, and the contents of the input vector memory are determined based on the information in the new status memory and the fanout memory. configured to be updated, and configured to simulate the contents of the dictionary memory determined by the contents of the input vector memory and the corresponding dictionary address memory as a new gate output. A hard logic simulator device characterized by: