JPH0458037B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a matrix type liquid crystal display device, and particularly to a drive circuit and a driving method for a matrix type liquid crystal display device for displaying images.

FIG. 1 is a diagram showing the configuration of a matrix type liquid crystal display device, in which 101 is a liquid crystal panel, 102 is a scanning line, 103 is a data line, 104 is a scanning side drive circuit, and 105 is a data side drive circuit. Conventionally, the data side drive circuit 105 serially transfers an input data signal using an N-stage shift register, converts it into a liquid crystal drive signal after the transfer is completed, and drives N data lines in parallel. In order to serially transfer an M-bit image signal using such a conventional N-stage shift register, convert it into a liquid crystal drive signal, and drive the data line, () M x N shift registers for data transfer are used. , or ()N
It is necessary to rely on a method of transferring data at M times the transfer speed using M shift registers.

When using the method (), the number of elements constituting the shift register increases, and power consumption during data transfer also increases. Therefore, if this drive circuit is made of an integrated circuit (hereinafter abbreviated as IC), the chip size and power consumption of the IC will be large, resulting in a product that is costly and consumes a large amount of power. In addition, if the method in () is used, IC
Not only does it require an expensive and complicated manufacturing process to speed up the process, but it also consumes a lot of power.

The present invention solves the above-mentioned drawbacks, and its purpose is to provide a data-side drive circuit and drive method for image display that can be manufactured at low cost and operate with low power consumption.

The feature of the present invention is to avoid serially transferring an M-bit image data signal in N stages, and
It sequentially writes to the stage memories, then imports the contents of the first memory into the second N stage memory in synchronization with the trigger signal, and then generates a gradation signal according to the contents of the second memory and converts it into a liquid crystal drive signal. Convert to N
The problem lies in configuring the data side drive circuit to drive the data line of the book. Hereinafter, the present invention will be explained in detail based on Examples.

In FIG. 2, 200 is a data bus that supplies an M-bit image data signal, and 3 in FIG.
As shown in 21, there are N cycles of changes within one period. The M-bit image data signal is written into the first memory corresponding to the address determined by the outputs of the N-stage shift registers 201-205. 251 to 255 in FIG. 2 indicate output signals of the shift registers 201 to 205, respectively. The output signals 251 to 255 are normally a logic "0" and sequentially become a logic "1" only once in one cycle, causing the contents of the data bus 200 to be written into the first memories 211 to 215.

The timing chart in Figure 3 shows this situation, and the timing chart of 301, 302, 303, 30
4 and 305 are shift registers 251 and 2, respectively.
The output signals of 52, 253, 254, 255 are
11, 312, 313, 314, 315 are first memories 211, 212, 213, 214, respectively.
The contents of the data stored in 215 are shown. Note that diagonal lines indicate a state in which the data is uncertain.

In FIGS. 2 and 3, the image data signal carried on the data bus 200 is stored in the memory 211 at the timing _T1 , the memory 212 at the timing _T2 , and the memory 213 at the timing _T3 .
will be written to. Thereafter, the image data is sequentially written to the memory, and at the timing T _N , the image data is written to the memory 215, and one cycle of the image data writing operation to the memory is completed. The image data for one period described above corresponds to the image data for one scanning line in FIG. Further, the number N of cycles within one period is equal to the number N of data lines in FIG.
260 is the first memory 211 to 215
This is a trigger signal that controls the transfer of data to the second memories 221 to 225, and its signal waveform is shown in FIG. 3 322. trigger signal 32
During the period when 322 is a logic "1", the data in the first memory is written to the second memory all at once, and during the period when 322 is a logic "0", the data in the second memories 221 to 225 are written to the second memory. The data remains stable as shown in 323. second memory 22
Each of 1 to 225 is M-bit data 27
1 to 275, and this M-bit data and basic pulse group 2, which is the constituent element of the gradation signal.
61 are synthesized by the gradation signal generation circuits 231 to 235 to generate gradation signals 281 to 28 of each stage.
5 is made. Here, the basic pulse group 261 is
For example, it consists of 2 ^M pulses with different pulse widths. 262 is the voltage level that turns on the liquid crystal, 26
3 is a signal that provides a voltage level to turn off the liquid crystal, and 262, 263 and grayscale signals 281 to 28
5, liquid crystal drive signals 291 to 295 are generated.

FIG. 4 shows a specific example of the circuit configuration of one stage of the drive circuit of the present invention. The figure shows an example in which the number of bits M of the image data supplied to the data bus is M=2, and both the first memory and the second memory are composed of 2 bits.
In FIG. 4, 401 is a shift register;
2 is a transfer clock, 403 is an output signal of 401, and 403 specifies the address of the first memory. First memories 412 and 413 are each composed of two inverters and two transfer gates. Image data _D1 and _D2 supplied to the 2-bit data bus 411
is written to the first memory when shift register output 403 goes high. 422 is a second memory, and two inverters 424, 4
25 and two transmission gates 426,
427. 423 is also a second memory, and its configuration is the same as 422.

421 consists of a pair of trigger signals T, and during the period when T is high, the first memory 412,
413 data is stored in the second memory 422, 423
will be forwarded to. 431 is a 4-channel multiplexer, which outputs the combination (0, 0), (0,
1), (1,0), and (1,1), one of the four types of gradation signals 432 to 435 is selected.
The gradation signal 436 generated in 431 as described above
is two transmission gates 441, 4
The signal is converted into a liquid crystal drive signal 451 by a liquid crystal drive signal generation circuit consisting of 42. Here, 443,
444 is the voltage level that turns on each liquid crystal
V _ON , and the voltage level V _OFF to turn off is given.

FIG. 5 shows another specific example of the circuit configuration. The difference between the example shown in the same figure and the example shown in FIG.
The clocked inverter 524 is active when the trigger signal T is high, and is inactive when T is low. A clocked inverter 524 is used to properly write data to the second memory 522.
The output impedance of the inverter 526 needs to be set sufficiently smaller than the output impedance of the inverter 526. In FIG. 5, the same symbols as those in FIG. 4 represent the same components as explained in FIG.

As described above, the drive circuit for a matrix type liquid crystal display device of the present invention has an N-stage shift register, and an M-bit data signal applied to a data bus in N-cycle time series is controlled by an output signal of the shift register. The first N written to the specified address
a second N-stage memory in which the contents of the first N-stage memory are written in synchronization with a trigger signal; a gradation signal for each stage is generated from data in each stage of the second N-stage memory; It consists of an N-stage gradation signal generation circuit, and an N-stage liquid crystal drive circuit that generates a liquid crystal drive signal from the output signal of the N-stage gradation signal generation circuit, and transfers M-bit image data to the first N stages. Since the data is sequentially written to the memory and the data written in the first N-stage memory is transferred to the second N-stage memory by a trigger signal, the circuits of the first memory and second memory are similar to the conventional N-stage shift register. It is much simpler than the shift register circuit for transferring M×N data that is required to serially transfer an M-bit image signal and convert it to a liquid crystal drive circuit to drive 1,000 data. Become something. Furthermore, the transfer speed of the drive circuit of the present invention is
With the above configuration, there is no need for high-speed transfer, and the N shift required to serially transfer an M-bit image signal using a conventional N-stage shift register, convert it into a liquid crystal drive signal, and drive the data line. Compared to a drive circuit that uses registers to perform transfer at M times the speed, there is no need to use an expensive high-speed IC to speed up the drive circuit.

Further, each stage of the above-described first and second N-stage memories of the present invention is constituted by a plurality of bits of memory, and each bit of the plurality of bits of memory is connected to a first terminal, a second terminal, and the second terminal. a first inverter having an input terminal connected to the first terminal and an output terminal connected to the second terminal; and a first inverter having the input terminal connected to the second terminal and the output terminal connected to the first terminal. and a second inverter, the number of transistors constituting each bit of the multi-bit memory is only four, resulting in a very simple circuit configuration. Therefore, when the memory of the present invention is integrated into an IC, the size of the IC chip is significantly reduced and power consumption is significantly reduced, which is a special effect.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the outline of the structure of a matrix type liquid crystal display device. FIG. 2 is a diagram for explaining an embodiment of the present invention. FIG. 3 is a diagram for explaining how signals change in each part in FIG. 2.
FIG. 4 and FIG. 5 are diagrams specifically showing a configuration example of the drive circuit of the present invention.

Claims (1)

[Claims] 1 N-stage shift register, a first N-stage memory in which an M-bit data signal applied to the data bus in N-cycle time series is written to an address specified by the output signal of the shift register;
a second N-stage memory into which the contents of the first N-stage memory are written in synchronization with a trigger signal;
an N-stage gradation signal generation circuit that generates a gradation signal at each stage from data at each stage of an N-stage memory;
It consists of an N-stage liquid crystal drive circuit that generates a liquid crystal drive signal from the output signal of a grayscale signal generation circuit of stages, and each stage of the first and second N-stage memories is composed of a plurality of bits of memory, and the plurality of Each bit of the memory of bits is connected to a first terminal, a second terminal, a first inverter having an input terminal connected to the first terminal and an output terminal connected to the second terminal, and a first inverter having an input terminal connected to the first terminal and an output terminal connected to the second terminal. A driving circuit for a matrix type liquid crystal display device, comprising a second inverter having an input terminal connected to the terminal and an output terminal connected to the first terminal.