JPH0456892A - Video processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video processing device that superimposes another video screen on a part of one video screen, and in particular, relates to a video processing device that superimposes another video screen on a part of one video screen, and in particular, the present invention relates to a video processing device that superimposes another video screen on a part of one video screen. The present invention relates to an image processing device capable of processing images.

[Conventional technology]

In the field of so-called personal computers (PCs), image processing called picture-in-picture, which displays television images superimposed on computer images, has become popular. In other words, it is interposed between a personal computer and a personal computer monitor, and in addition to personal computer video signals, video signals from outside, especially general 2:1 interlaced video signals, are captured in the video memory, and one part of the personal computer video screen is captured. A video processing device that synthesizes and displays video signals read from the video memory is currently being developed.

[Problem to be solved by the invention]

By the way, since the above-mentioned pixel address walk to the read start position on the video memory is performed at a relatively high speed,
A first clock signal with a high frequency is applied. Further, when reading the pixel address from the top position of the video memory using the trail, a second clock signal having a lower frequency is applied compared to the reading of the pixel address from the top position of the video memory. This means that the readout processing speed of the pixel address from the top position of the video memory is fast, or that the digital RGB luminance signal that has been read out is converted into an analog signal.
This is because the /A conversion process is relatively slow, and a second clock signal with a low frequency is applied to synchronize with the D/A conversion process.

Conventionally, when switching from the first clock signal with a higher frequency to the second clock signal with a lower frequency, that is, at the rising edge of each field, the pixel address is incremented from the beginning of the video memory to the readout start position, and the image is started from the readout start position. When reading out signals, the video screen sometimes flickered. The reason for this is that there is an unstable lock region called jitter in the PLL section of the tarlock generator, and this jitter generates one extra clock pulse. This flickering on the video screen is not noticeable when the video is moving relatively quickly, as the human eye is fooled by the movement, but when the screen is stationary or changes slowly, I find it bothersome.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the video processing device of the present invention includes:
A/D conversion means for converting the RGB luminance signal of the first video signal into a digital RGB luminance signal; a video storage means for storing the digital RGB luminance signal from the A/D conversion means; and a video storage means for reading from the video storage means. a D/A converting means for converting the digital RGB luminance signal into analog; a mixing means for partially replacing the RGB luminance signal of the second video signal with the RGB luminance signal from the D/A converting means;
RG from the D/A conversion means during the screen of the video signal
and a control means for controlling each of the means based on a command indicating how to insert the screen based on the B brightness signal,
This control means can arbitrarily set the readout start reference position in the horizontal direction based on the timing control of the readout start signal. The clock signal is switched from a first clock signal with a faster frequency to a second clock signal with a slower frequency at a reading start reference position or a position where a predetermined number of dots is counted from there,
This second clock signal is generated by a PLL (phase locked group) which inputs a signal synchronized with the read start signal as a reference phase signal.

[Effect]

With the video processing device according to the present invention, since the first clock signal and the second clock signal, which are lock signals that are optimal for reading and reading data in the video memory, are respectively given to the video memory, efficient and high-speed operation can be achieved. is possible. Also,
The second clock signal given to the video memory at the start of reading from an arbitrarily set video memory can be generated at a timing that is not affected by jitter.

[Embodiment] FIG. 1 is a block diagram of a video processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the connection relationship between the video processing device, a personal computer, and a personal computer monitor.

The video processing device 1 receives a personal computer video signal 3 (RGB luminance signal and vertical/horizontal synchronization signal) coming from a personal computer 2 and an NT video signal coming from a video input terminal 4.
The SC composite video signal 5 is input. Then, the video processing device 1 synthesizes these two video signals and outputs a video signal 8, in which the screen 7 of the NTSC composite video signal 5 is inserted into the screen 6 of the PC video signal 3, to the computer monitor 9. How the screen 7 is inserted into the screen 6 is determined based on a command 10 from the personal computer 2.

The NTSC composite video signal 5 is applied to the video input terminal 4 from a TV tuner, video deck, etc. (not shown).

Next, the internal configuration of the video processing device 1 will be explained.

The video signal decoder 21 receives the NTS from the video input terminal 4.
A C composite video signal is input, and RGB luminance signals and horizontal and vertical synchronization signals are extracted from this video signal. The A/D converter (ADC) 22 converts the RGB luminance signal 23 coming from the video signal decoder 21 into a digital RGB luminance signal 25 at the timing of the clock signal CKAD from the digitizing control section 24 . Video memory 26 has 960 lines x 3
It has a configuration of 06 columns x 4 bits, and this is RlG, B
are provided for each color.

The digitizing control section 24 sends a clock signal C to the ADC 22.
In addition to outputting KAD, a write control signal WETV is output to the video memory 26. The clock signal CKAD is a signal synchronized with the horizontal synchronization signal from the video signal decoder 21, and has a period of 1/1 of the period of the horizontal synchronization signal (for example, 63.5 μs).
It has a period of N (N is a positive integer). Write control signal WE
TV is a signal that allows writing of the digital RGB luminance signal 25 coming from the ADC 22. The specific form of the write control signal WETV varies depending on the specifications of the video memory 26, but it is generally a set of a plurality of control signals. For example, a signal that specifies or advances a pixel address on the storage screen of the video memory 26,
A control signal that allows writing in pixel units on the screen of the video memory 26, a control signal that allows writing only to a desired edge area on the storage screen of the video memory 26, and a control signal that allows writing only to a desired area in the horizontal direction on the screen of the NTSC composite video signal 5. The control signal includes a control signal that permits writing in only a desired area in the vertical direction, and a control signal that permits writing only in a desired area in the vertical direction. These control signals are all created by counting write basic synchronization signals created inside the digitizing control section 24 and changing the signal level when the counting result reaches a set value. These set values can be adjusted based on instructions from the personal computer 2. By appropriately selecting these setting values, it becomes possible to arbitrarily specify resolution, aspect ratio, etc. Further, the count for creating each control signal is reset for each vertical synchronization signal of the NTSC composite video signal 5. Therefore, as in the NTSC composite video signal 5, a vertical synchronization signal is inserted for each field.
Writing of an interlaced video signal is performed in units of fields.

The superimpose control unit 31 controls reading of video data stored in the video memory 26.

The superimpose control unit 31 sends a readout control signal to the video memory 26 based on the conditions commanded from the personal computer 2, and outputs a readout control signal to the D/A converter (DAC).
A clock signal CKDA is sent to the video switch 32, and a bar impose permission signal 42 is sent to the video switch 34. The reading of video data by the superimpose control section 31 is performed completely independently of the writing by the digitization control section 24. The internal configuration of the superimpose control section 31 will be described later in conjunction with FIG.

The DAC 32 samples the digital RGB luminance signal 40 read from the video memory 26 at the timing of the clock signal CADA and converts it into an analog RGB luminance signal 41.

The video switch 34 receives a superimpose permission signal 4.
2, the analog RGB luminance signal output from the DAC 32 is superimposed on the RGB luminance signal of the PC video signal 3 arriving from the input terminal 35, and is output as a new RGB luminance signal 44.

The video signal output terminal 38 is connected to the R from the video switch 34.
This terminal outputs the GB luminance signal 44 and the horizontal and vertical synchronization signals from the video signal input terminal 35, and the video signal 8 (RGB luminance signal and synchronization signal) from this output terminal 38 is given to the computer monitor 9. .

Here, the superimpose control section 31 will be explained in detail. FIG. 3 is a block circuit diagram of the superimpose control section 31 and its peripheral circuits shown in FIG. 1. The video memory 26 shown here is Sony CXK1206.
and the second part of its data sheet number 71215-ST
Timing charts related to read ports are described on pages 7 to 31. The port used is read port 1 on page 2 of the above data sheet.

In the video memory 26, the memory drive clock signal HDCK
is the port 1 shift signal terminal CKRI, and the memory vertical/horizontal reset signal MR5T is the port 1 vertical clear terminal VC.
Connect the horizontal direction reset signal HRST to LRI or the vertical offset signal VOF to the port 1 horizontal clear terminal HCLR1.
T or vertical line clock signal VLCK or port 1 line increment terminal lNCl, port 1 output enable REI (negative logic) is connected to port 1 output enable terminal R
Each is given to EI (negative logic). Also, analog R
The GB signal LSMIli (one data in each of R, G, and B) is read from the port 1 data output DO□O=DO13.

Port 1 shift signal CKR1, port 1 vertical clear VCLRI, port 1 horizontal clear signal HCLR1, port 1 line increment signal INC corresponding to each terminal above
l, port 1 output enable REI (negative logic),
The analog RGB signal LSMEM to be read is controlled by R,
For example, 4 bits are output for each of G and B from the port 1 data output DO-Do13.

The video switch 34 has a switching signal CNT (-superimpose permission signal 42) inputted to a switching signal input terminal.
As a result, the input from the A terminal or B terminal is output from the C terminal. Specifically, when the switching signal CNT is at a high level rHJ, the input from the B terminal is output, and when the switching signal CNT is at a low level rLJ, the input from the A terminal is output from the C terminal.

CPU bus 610 is connected to personal computer 2 . Reference numeral 421 indicates a horizontal reference read dot clock generator that outputs a horizontal reference read dot clock signal HBDCK, 422 indicates a horizontal read start counter that outputs a horizontal read start A signal HRSA and a horizontal read direction reset signal HR5T, and 423 indicates a horizontal read start counter that outputs a horizontal read start A signal HRSA and a horizontal read direction reset signal HR5T. Horizontal reference start B signal H
Shows a horizontal 64 clock counter outputting RSB, 4
Reference numeral 24 indicates a horizontal read number counter that outputs the horizontal read number signal HRT, and 425 indicates a horizontal read dot clock generator that outputs the horizontal read dot clock signal HDDA.

Further, the memory vertical read offset counter 426 has a function of arbitrarily setting the count number of the horizontal reference read dot clock generator 421 from the personal computer 2, and outputs a vertical read offset signal VROFT. The vertical blacking number counter 427 outputs the vertical blacking end signal VBE, and the vertical reading start counter 4
28 outputs a vertical read start signal VR5, a vertical read count counter 429 outputs a vertical read count signal VRT, and a vertical read line clock generator 430 outputs a vertical read line clock signal VRLCK. AND circuit 431 outputs superimpose permission signal 5ENBL and performs OR
The circuit 432 outputs either the vertical read offset signal VTOFT or the vertical read line increment signal VRLCK as the vertical read clear signal VCLRI,
NOR circuit 433 outputs a read enable REI signal. Further, reference numerals 434 and 435 indicate tri-state circuits, and 436 indicates an inverter circuit.

Analog RGB luminance signals coming from a color input terminal 506 forming part of the video input terminal 35 are applied to the A terminal of the video switch 34. The horizontal synchronization signal HSPC arriving from the synchronization terminal 507 forming a part of the input terminal 35 includes a horizontal reference read dot clock generator 421, a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read number counter 424, and a vertical read offset. counter 4
26, is given to a vertical blacking number counter 427, a vertical read start counter 428, a vertical read number counter 429, a vertical read line clock generator 430, and
Synchronous signal terminal 490.491 forming part of output terminal 38
are sent to each. Further, the vertical synchronization signal VSPC arriving from the synchronization terminal 508 forming a part of the input terminal 35 is transmitted to the video memory 26, the vertical offset counter 426, the vertical blacking number counter 427, the vertical read start counter 428, the vertical read number counter 429, It is applied to the vertical read line clock generator 430 and sent to a synchronization signal terminal 491 forming part of the output terminal 38.

The horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read circuit counter 424 have their respective count values reset by the horizontal synchronization signal H5PC. Vertical read offset counter 426, vertical blacking number counter 427, vertical read start counter 42
8 and vertical read count counter 429, their count values are each reset by vertical synchronization signal VSPC.

The signal HBDCK generated by the horizontal reference read dot clock generator 421 is applied to a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read count counter 424, and a vertical read offset counter 426, and is also applied via a tristate circuit 435. The clock signal HDCK of the video memory 26 is used as the clock signal HDCK of the video memory 26.
The port 1 shift signal terminal CKRI of the port 1 is sent to the port 1 shift signal terminal CKRI.

Further, the horizontal read dot clock generator 425 is synchronized with the horizontal read start B signal HR8B, and is synchronized with the horizontal read start B signal HR8B.
PLL that outputs a signal with a frequency N2 times the frequency of SB
It is composed of a circuit and outputs a horizontal read dot clock signal HDDA.

FIG. 4 shows the configuration of the horizontal readout section including the PLL circuit. This PLL circuit is a circuit that synchronizes a voltage controlled oscillator (VCO) signal with a reference clock signal to generate a stable lock signal.

The horizontal read dot clock signal HDDA generated by the horizontal read dot clock generator 425 is converted into a clock signal HD of the video memory 26 via a tri-state circuit 434.
Port 1 shift signal terminal C of the video memory 26 as CK
KRI and the DAC 32, and used as a read clock signal for the digital RGB luminance signal LSMEM and a conversion clock signal for the DAC 32.

Further, the vertical read line clock generator 430 is configured with a PLL circuit that is synchronized with the vertical synchronizing signal vspc and outputs a signal with a frequency N3 times the frequency of the vertical synchronizing signal VSPC, and is synchronized with the vertical read line clock signal VRLCK.
Output. This vertical successive line clock generator 430
The vertical read line clock signal VRLCK generated from the port 1 line increment terminal lNCl is synchronized with the clock signal HDCK of the video memory 26 and advances the line address, which is the vertical address of the video memory 26, via the OR circuit 432. is given to O
It is applied to the port 1 output enable REI terminal (negative logic) via the R circuit 432 and the NOR circuit 433.

The superimpose control unit 31 controls the horizontal reference read dot clock signal HBDCK, the horizontal read dot clock signal HDDA, and the vertical read line clock signal VRL.
CK provides basic timing.

Further, in order to determine the read start offset point of the video memory 26, the vertical successive offset counter 426 uses the horizontal reference read dot clock output from the horizontal reference read dot clock generator 421 after the count value is reset by the vertical synchronization signal vspc. An OR circuit 432 generates a vertical offset signal VROFT that increments the vertical line address of the video memory 26 in synchronization with the signal HBDCK.
Send to.

Furthermore, the vertical blacking number counter 427 includes a counter (not shown) for deleting the vertical back porch area of the analog RGB luminance signal LSPC. This counter counts the number of clocks of the horizontal synchronization signal H5PC,
After passing the vertical back porch area, a vertical blacking end signal VBE is output to the vertical read start counter 428.

The vertical read start counter 428 receives the permission signal (vertical blacking end signal VBE) sent from the vertical blacking number counter 427, counts the number of clocks of the horizontal synchronization signal H8PC, and continuously reads data from the video memory 26 in the vertical direction. Start permission signal (vertical read start signal) to VH
3 Output to vertical readout counter 429. The vertical readout counter 429 receives the permission signal (control signal VH5) sent from the vertical readout start counter 428, counts the number of clocks of the horizontal synchronization signal HSPC, and calculates a signal indicating the readout period in the vertical direction from the video memory 26. , that is, outputs the vertical read count signal VRT to the AND circuit 431.

Then, the vertical read offset counter 4 described above
26, a vertical blacking number counter 427, a vertical read start counter 428, a vertical read number counter 429, and a vertical read line clock generator 430 perform vertical read control for the video memory 26.

Note that the number of clocks of the horizontal reference read dot clock signal HBDCK counted by the vertical read offset counter 426, the number of clocks of the horizontal synchronization signal H3PC counted by the vertical read start counter 428, and the number of clocks of the horizontal synchronization signal H3PC counted by the vertical read count counter 429. The clock numbers are each set to a required value by an instruction from the personal computer 2.

On the other hand, the horizontal readout start counter 422 counts the number of clocks of the horizontal reference successive dot clock signal HBDCK sent from the horizontal reference readout dot clock generator 421, and receives a readout start permission signal (horizontal readout start permission signal) for the horizontal direction of the video memory 26. Ai No. HRSA) is sent to the horizontal 64 clock counter 423. The horizontal 64 clock counter 423 receives the permission signal (horizontal read start A signal HR3A) sent from the horizontal read start counter 422, and clocks the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. Count the numbers.

When the count value reaches 64 clocks, which is the characteristic when reading out the video memory 26, the horizontal readout start B signal H
The RSB is output to the horizontal read count counter 424, the horizontal read dot clock generator 425, and the AND circuit 431. The horizontal readout number counter 424 counts the number of clocks of the horizontal reference readout dot clock signal HBDCK sent from the horizontal reference readout dot clock generator 421, and outputs a readout period permission signal (
The horizontal read count signal HRT) is sent to the AND circuit 431.

Thus, the horizontal reading start counter 422, the horizontal 64 clock counter 423, and the horizontal reading number counter 424 perform horizontal reading control for the video memory 26. Note that the number of clocks of the horizontal reference read dot clock signal HBDCK counted by the horizontal read start counter 422 and the number of clocks of the reference dot clock signal HBDCK counted by the horizontal read number counter 424 are respectively set to required values by the personal computer 2. Ru.

Next, regarding the operation of the superimpose control section 31,
This will be explained with reference to FIGS. 5, 6, and 7. Note that FIG. 5 is a timing chart of permission to read the video memory 26 in the vertical direction, FIG. 6 is a timing chart of vertical offset of the video memory 26, and FIG. 7 is a timing chart of permission to read the video memory 26 in the horizontal direction. FIG. 8 is a timing chart of reading the video memory 26 in the horizontal direction.

First, regarding permission to read the video memory 26 in the vertical direction,
This will be explained with reference to FIG.

When the vertical synchronization signal vspc reaches the high level rHJ (see FIG. 5(a)), the vertical blacking number counter 427
, the vertical read start counter 428 and the vertical read count counter 429 are reset, and the vertical blacking end signal V
BE, vertical read start signal VR5 and vertical read count signal V
RT becomes low level rLJ (Fig. 5(d)
(see (e), (f)), vertical blacking number counter 4
27 counts the number of clocks of the horizontal synchronizing signal HSPC, and when it passes the vertical hack porch area, sets the vertical blacking end signal VBE to high level rHJ (Fig. 5(d)).
reference). When the vertical blacking end signal VBE reaches the high level rHJ, the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronizing signal HSPC. When the vertical read start counter 428 counts the value set by the personal computer 2, the vertical read start signal VR5 is set to high level rHJ (see FIG. 5(e)). When the vertical read start signal VR8 becomes high level rHJ, it means that the start of reading of the digital RGB signal LSMEM is permitted in the vertical direction of the video memory 26, so the vertical read number counter 429 changes to the horizontal synchronizing signal H8PC. Start counting the number of clocks.

After counting the value set by the vertical reading port number counter 429 or the personal computer 2, the vertical reading number signal VRT is set to high level rHJ (see FIG. 5(f)).

During the period when the vertical read start signal VRS is at high level rHJ and the vertical read count signal VRT is at low level rLJ, the horizontal read start B signal HR3B is at high level "H" and the horizontal read count signal HRT is at low level rLJ. If so, the AND circuit 431 outputs a superimpose enable signal 5ENBL of high level rHJ. Therefore, in the video memory 26, the digital RGB signal LSMEM is read out based on the vertical read permission during this period.

Next, regarding the vertical offset of the video memory 26, the sixth
This will be explained with reference to the figures.

When the vertical synchronization signal vspc becomes high level rHJ (see FIG. 6(a)), the vertical read offset counter 426
After being reset, it starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK. While counting the value set by the vertical read offset counter 426 or the personal computer 2, the vertical read offset signal VROFT is applied to the port line increment lNCl of the video memory 26 via the OR circuit 432 (see FIG. 6(c)). , offset the vertical read address value of the video memory 26.

At this time, since the vertical synchronization signal VSPC and the vertical read offset signal VROFT are applied to the NOR circuit 433, the read enable signal RE1 (negative logic) is applied to the read enable terminals R and E1 (negative logic) of the video memory 26. , readable. Then, since a vertical offset is performed by counting the value set by the personal computer 2, the vertical read offset counter 426 stops outputting the vertical read offset signal VROFT until the arrival of the next vertical synchronization signal vspc.

Next, permission to read the video memory 26 in the horizontal direction will be explained with reference to FIG.

When the horizontal synchronization signal H5PC is output, the horizontal readout start counter 422, the horizontal 64 clock counter 423, and the horizontal readout number counter 424 are reset, and the horizontal readout start start A signal HR3A and the horizontal readout start start B signal HR5 are reset.
B and horizontal read count signal HRT become low level, "L" (see FIGS. 7(d), (e), and (f)). and,
The horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421, and when the count value reaches the value set by the personal computer 2, the horizontal read start A signal is output. High level HR3A
Set to HJ (see Figure 7(d)). When the horizontal read start A signal HRSA becomes high level rHJ, the horizontal 64 clock counter 423 outputs the reference read dot clock signal HBD.
Count the number of CK clocks and the count value is 64.
, the horizontal read start B signal HR3B is set to high level r.
Set to HJ (see Figure 7(e)).

Note that the horizontal 64 clock counter 423 is connected to the video memory 2.
6, the high level rHJ of the horizontal read start B signal HR3B is generated at a count value of "64", but it is not limited to 64.

The horizontal read start B signal HR3B is at the noise level rHJ.
When this happens, horizontal reading of the video memory 26 is permitted, and the horizontal reading counter 424 starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK.

When the count value reaches the value set by the personal computer 2, the horizontal reading number signal HRT is set to high level rHJ (see FIG. 7(f)). moreover,
Horizontal read dot clock generator 425 starts horizontal read B
In synchronization with signal HR5B, horizontal read dot clock signal H
Output DDA.

When the vertical read start signal VR3 is at high level rHJ and the vertical read count signal VRT is at low level rLJ, the period during which the horizontal read start B signal HR3B is at high level rHJ and the horizontal read count signal HRT is at low level rLJ AND circuit 4 receiving the horizontal read count signal HRT
31 outputs a superimpose enable signal 5ENBL of high level rHJ. Therefore, in the video memory 26, based on the vertical read permission during this time,
The digital RGB signal LSMEM is read out.

Next, regarding horizontal reading of the video memory 26,
This will be explained with reference to FIGS. 8 to 11.

The video memory 26 is supplied with a drive clock signal HDCK, which is composed of a horizontal reference read dot clock signal HBDCK (see FIG. 8(e)) and a horizontal read dot clock signal HDDA (see FIG. 8(f)).
reference). That is, when the superimpose enable signal 5ENBL is at the low level rLJ, the tri-state circuit 435 operates and the horizontal reference read dot clock signal HBDCK is applied to the video memory 26 as the drive clock signal HDCK (FIG. 8(d) ), (e)
, see (g)). Also, superimpose permission signal 5
When ENBL reaches the high level rHJ, the horizontal readout dot clock signal HDDA is applied to the video memory 26 as the drive clock signal HDCK (FIGS. 8(d) and (f)).
, see (g)). At this time, reading of the digital signal LSMEM from the video memory 26 and analog conversion by the DAC 32 are performed.

To explain this in detail, when the superimpose enable signal 5ENBL is at a low level rLJ, reading from the video memory 26 is not performed, and the address is incremented to the vertical read offset point and superimposition is performed. Only the digital RGB signals in the horizontal/vertical regions that are not available are skipped, so to speak. In this case, since the operation is only within the memory, the horizontal reference read dot clock signal HBDCK, which is a high frequency signal, is applied to the video memory 26 as the drive clock signal HDCK. On the other hand, when superimpose permission signal 5ENBL is at high level rHJ, only reading from video memory 26 is performed. In this case, it is only necessary to synchronize with the analog conversion of DAC32,
Horizontal read dot clock signal H, which is a low frequency signal
DDA is used as drive clock signal HDCK for video memory 2.
given to 6.

The horizontal reference read dot clock HBDCK has a frequency approximately 100 times higher than the horizontal read dot clock HDDA. Horizontal reference read dot clock HBDC in Figure 8(e)
K is actually a finer waveform, but if the actual waveform is used as it is, it will be too fine and difficult to draw, so it is displayed after changing the frequency to about one-tenth.

By the way, in the conventional image processing device, the clock signal given to the video memory 26 is the horizontal reference readout dot clock H.
Horizontal read dot clock HDDA at the timing of switching from BDCK to horizontal read dot clock HDDA
condition was not constant. The reason for this is as follows.

The timing of switching from the horizontal reference read dot clock HBDCK to the horizontal read dot clock HDDA is given by the superimpose enable signal 5ENBL, and this signal is synchronized with the timing at which the horizontal reference start B signal HR5B becomes high level rHJ. This horizontal reference start B signal HR3B is converted into the horizontal reference start A signal H.
R3A becomes high level rHJ after 64 clocks have passed from the time when it became high level rHJ. Further, the timing at which the horizontal reference start A signal HR5A reaches the high level rHJ can be freely changed by rewriting the set value of the horizontal read start counter 422 in the personal computer 2. The superimpose permission signal 5ENBL is a horizontal reference start A signal HRSA which is such a variable signal.
Since it is indirectly synchronized with , the timing at which the superimpose enable signal 5ENBL becomes high level rHJ is also variable. On the other hand, the horizontal readout dot clock HD
DA is a signal having a constant period synchronized with the horizontal synchronization signal HSPC. Therefore, superimpose permission signal 5
The state of the horizontal read dot clock HDDA at the timing when ENBL becomes high level rHJ is not certain.

Superimpose enable signal 5ENBL is at high level r
If the state of the horizontal read dot clock HDDA at the timing of HJ is uncertain, an extra pulse may be generated in the drive clock signal HDCK due to the effect of the sick mentioned above.

This problem will be explained below.

First, there are four possible states of the horizontal read dot clock HDDA at the timing when the tarlock signal applied to the video memory 26 switches from the horizontal reference successive dot clock HBDCK to the horizontal read dot clock HDDA as shown in FIG. The first state is a state in which a high level rHJ is maintained before and after switching (see Figure 9(c)).
. And the second state is low level rLJ before and after switching.
is maintained (see FIG. 9(d)). Also the third
The state changes from /1 level rHJ to low level rLJ at the switching timing (Fig. 9(e)).
reference). Furthermore, the fourth state is a state in which the low level rLJ changes to the low level rHJ at the switching timing (see FIG. 9(f)). Drive clock signal HDCK
is a signal obtained by combining the horizontal reference read dot clock HBDCK and the horizontal read dot clock HDDA (see FIGS. 9(g), (h), (i), and (j)).

In this third state, it is affected by jitter. In other words, in the third state, if there is no influence of jitter, the timing at which the superimpose enable signal 5ENBL becomes high level rHJ and the timing at which the horizontal read dot clock HDDA changes from high level rHJ to low level rLJ coincide ( (See Figure 10(c)), or does the signal shift backward when affected by jitter (See Figure 10(d))?
, or the signal shifts before (see FIG. 10(e)).

Due to this shift, the drive clock signal HDCK also becomes a signal containing a shift (see FIGS. 10(f), (g), and (h)). If the signal shifts backward due to the influence of jitter, one extra pulse or lock signal will be generated compared to when there is no influence of jitter or when the signal shifts forward due to the influence of jitter. For this reason, in conventional video processing devices, partial image disturbances occur.

This embodiment has been devised to prevent the generation of these extra pulses. In other words, superimpose permission signal 5E
By generating the horizontal read dot clock HDDA at the same timing as NBL becomes high level rHJ, the fourth state signal (see FIG. 9(f)) is always maintained. Then, the drive clock signal HDCK in the fourth state is applied to the video memory (see FIG. 9(j)). With this timing, no extra pulses will be generated even if jitter occurs. The reason for this is as follows.

Even when the drive clock signal HDCK maintains the fourth state, the signal shifts backward or forward due to the influence of jitter, as in the third state. In this case, the driving clock signal HDCK will either be a signal that includes a deviation, as in the third state, or the pulse width of the clock signal will only change, but the number of pulses itself will not change (Fig. 11(f), (g)
, (h)). In other words, if the fourth state can be maintained at all times, even if jitter occurs, no extra pulses will be generated and a clear image can be obtained.

In this embodiment, the conventional problem was solved by maintaining the fourth state, but the same effect can be obtained even if the first state or the second state is maintained.

Furthermore, the timing chart described above is an example;
For example, the above operation can be performed even if each signal has positive logic or negative logic.

Next, the operation of this embodiment after reading out from the video memory 26 will be explained.

Analog R coming from color input terminal 506 as described above
The GB signal LSPC is input to point A of the video switch 34. Also, it is read out from the video memory 26 and sent to the DAC 32.
Analog RGB signal LSDA converted to analog by
is input to point B of the video switch 34. Therefore, by switching the video switch 34 using the superimpose enable signal 5ENBL, the analog RGB signal LSMON, which is the output of the video switch 34, is converted into an image corresponding to the analog RGB signal LSPC arriving from the color input terminal 506. RGB signal LS
It is output from the output terminal 505 as a signal LSMON corresponding to an image obtained by superimposing the image corresponding to DA. Further, along with the output of the analog RGB signal LSMON, a horizontal synchronization signal and a vertical synchronization signal vspc are also output from the output terminal 38 (including the output terminal 505).

Note that the above-mentioned timing chart is an example, and the above-mentioned operation can be performed even if each signal is positive logic or negative logic.

Furthermore, as can be seen from the configuration of FIG.
36, the tristate circuit 434 operates and the horizontal read dot clock signal HDDA is output to the drive clock signal H.
Sent as DCK. Conversely, when superimpose enable signal 5ENBL is at low level rLJ, tristate circuit 435 operates and horizontal reference read dot clock signal HBDCK is applied to video memory 26 as drive clock signal HDCK.

That is, when superimposition is performed with the superimpose enable signal 5ENBL at high level rHJ, the horizontal read dot clock HDDA output from the horizontal read dot clock generator 425 causes the video memory 2
6 is accessed to read out the digital RGB signal LSMEM at a speed sufficient for superimposition. On the other hand, when superimposition is not performed with the superimpose enable signal 5ENBL or low level rLJ, the horizontal reference read dot clock whose frequency is 100 times higher than the horizontal read dot clock HDDA output from the horizontal reference read dot clock generator 421 is used. The video memory 26 is accessed by HBDCK, and the address path up to the vertical readout offset point and the digital RGB signal in the horizontal/vertical area where superimposition is not performed are simply skipped, and the next superimposition is permitted. This prepares for the timing when the signal 5ENBL becomes high level rHJ.

Through this operation, it is possible to obtain a composite screen in which a sub-screen 7 based on an external video signal is inserted into a main screen 6 based on a personal computer video signal, as shown in the personal computer monitor 9 in FIG.

〔Effect of the invention〕

As explained above, according to the image processing device of the present invention, it is possible to provide a clock signal with a stable number of dots to the video memory without being affected by jitter, and it is possible to provide an image with no horizontal fluctuation. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIG. 3 is a block diagram showing the internal configuration of a superimpose control section, and FIG.
The figure is a block diagram showing the internal configuration of the horizontal readout part of the superimpose control section, FIGS. 5 to 9 are waveform diagrams showing the operation of the superimpose control section, and FIG. Waveform diagram showing the influence, Figure 11 is the 4th
FIG. 3 is a waveform diagram showing the influence of state jitter. DESCRIPTION OF SYMBOLS 1...Video processing device, 2...Personal computer, 3...PC video signal, 5...NTSC composite video signal, 6...Main screen, 7...Subscreen, 9...
PC monitor, 21... video signal decoder, 22...
...ADC. 24... Digitization control unit, 26... Video memory,
31...Superimpose control unit, 32...DAC
. 34...Video switch, 35...Video input terminal,
38...Video output terminal.

Claims (1)

[Scope of Claims] A/D conversion means for converting the RGB luminance signal of the first video signal into a digital RGB luminance signal; video storage means for storing the digital RGB luminance signal from the A/D conversion means; D/A converting means for analogizing the digital RGB luminance signal read from the video storage means; and mixing means for partially replacing the RGB luminance signal of the second video signal with the RGB luminance signal from the D/A converting means. and a control means for controlling each of the means based on a command indicating how to insert a screen according to the RGB luminance signal from the D/A converting means into the screen according to the second video signal. In the processing device, the control means is capable of arbitrarily setting a readout start reference position in the horizontal direction based on timing control of a readout start signal, and in reading dots of a horizontal line from the video storage means, The dot clock signal applied to the video storage means is switched from a first clock signal with a faster frequency to a second clock signal with a slower frequency at the reading start reference position or a position where a predetermined number of dots is counted from there, and this second clock signal is A video processing device characterized in that the video processing device is generated by a PLL (phase locked group) that inputs a signal synchronized with the readout start signal as a reference phase signal.