JPH0456513A - Logic circuit - Google Patents

Abstract

PURPOSE:To make the circuit operation stable by feeding back an inphase signal being a delayed output signal to an input 1st stage transistor(TR) to control an input switching level. CONSTITUTION:The circuit is provided with a circuit block PL comprising P-channel MOS TRs Qpl1, Qpl2 and a circuit block PN comprising N-channel MOS TRs Qnl1, Qnl2. Moreover, a 1st P-channel MOS TR Qpl receiving a signal in phase with an output signal O as its gate input and a 2nd P-channel MOS TR Qp2 receiving a ground voltage VSS as its gate input are connected in parallel between the circuit block PL and a power supply VCC. In such a case, since the TR QP1 acts like a current control TR, not only an output signal is settled quickly but also a current flowing between power supplies is less when at least one of input signals 11,12 transfers to a logic voltage H. Thus, the entire circuit is operated stably.

Description

[Detailed description of the invention] Industrial applications The present invention relates to logic circuits.

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuit devices has progressed at a remarkable pace. At that time, it is an important technology to operate logic circuits used in integrated circuit devices at high speed and stably.

FIG. 9(A) is a diagram showing a general example of a conventional logic circuit.
FIG. 9(B) is a diagram showing a logical OR NOT circuit as an example of FIG. 9(A), and FIG. 9(C) is a diagram showing a logical OR NOT circuit as an example of FIG.
FIG. 3 is a signal waveform diagram of an example of FIG. In Figure 9(B), Q
pH, Qp12 is a P-channel type MOS transistor,
Qnll, Qn12 are N-channel MOS transistors, PL is a P-channel MOS) circuit block, NL is a circuit block composed of N-channel MOS transistors,
is a natural number) is an input signal to the circuit block PL composed of P-channel type MOS transistors, I or In (n is a natural number) is an input signal to the circuit block NL composed of N-channel type MOS transistors, 0
is the output signal, VCC is the power supply voltage, VSS is the ground voltage, I
NV is a negative circuit. As a general example of a conventional logic circuit, as shown in FIG. A logic circuit in which a second circuit block configured of a plurality of N-channel type MOS transistors to which input signal groups are input is connected in series between a power supply voltage vCC and a ground voltage vSS. be. The circuit operation will be explained with reference to an embodiment shown in FIG. 9(B). When input signals 11 and 12 are both logic voltage "L", P channel type MOS transistors QpH and Qp12 are turned on, and N channel type MOS transistors QpH and Qp12 are turned on.
S function registers Qnll and Qn12 are turned off and the output signal is 0.
becomes a logic voltage "H". When at least one of the input signals II and I2 is at logic voltage "H", at least one of the P-channel MOS transistors QpH and Qp12 is turned off, and at least one of the N-channel MOS transistors Qnll and Qn12 is turned on. Then, the output signal 0 becomes a logic voltage "L". In this way, the operation of the logical OR NOT circuit is performed. Further, as shown in FIG. 9(C), the input signal 11. When I2 transitions, both the P-channel MOS transistor and the N-channel MOS transistor are turned on, and a through current flows between the power supply voltage and the ground voltage.

Problems to be Solved by the Invention In the logic circuit having the conventional circuit configuration, when an input signal transitions to an intermediate level between the logic voltages "H" and "L", this input signal is applied to the input P channel. Both the type MOS transistor (PL) and the N-channel type MOS transistor (NL) are turned on, and a through current flows between the power supply voltage and the ground voltage, and this through current lowers the potential of the power supply voltage, causing the circuit to operate. This poses a problem in that it makes the output signal unstable and makes it difficult for the output signal to be set to "H" or "L", which becomes a major obstacle to increasing the speed of the logic circuit.

Means for Solving the Problems In order to solve such problems, a first circuit block constituted by a plurality of P-channel type MOS transistors, and a plurality of circuit blocks formed in the first circuit block are provided. a first input terminal; a second circuit block composed of a plurality of N-channel type MOS transistors;
A plurality of second input terminals formed in a circuit block are connected to a drain of the first circuit block and a drain of the second circuit block, and the drain of the first circuit block is used as an output terminal. , a source of the second circuit block is connected to ground, a power terminal connected to the source of the first circuit block, and a gate is output to the output terminal between the power terminal and the ground. a first MOS transistor to which a signal in phase with the signal is input;
A second M whose gate is input with ground voltage or power supply voltage
OS type transistors are connected in parallel.

By feeding back the delayed in-phase signal from the output signal to the transistor in the first stage of the active input and controlling the input switching level, the input signal transitions more easily, and by shortening the transition time, the output signal is determined quickly, and the power supply The through current between the voltage and the ground voltage is also smaller than in the conventional case, and the drop in power supply voltage is also reduced.

EXAMPLES Hereinafter, the present invention will be explained by examples. 1 to 8 are diagrams showing one embodiment of the logic circuit of the present invention.

Figure 1 (A), Figure 2 (A), Figure 3 (A), (B)
, FIG. 4(A), FIG. 5(A), FIG. 6(A).

(B), FIG. 7(A), and FIG. 8(A) are general examples of implementation of the present invention, and FIG. 1(B), FIG. 2(B), and FIG.
B).

5(B), FIG. 7(B), and FIG. 8(B) are circuit examples of the implementation, FIG. 1(C) is a signal waveform diagram of the embodiment of FIG. 1(B), and FIG. FIG. 7(C) is a signal waveform diagram of the embodiment of FIG. 4(B), and FIG. 7(C) is a signal waveform diagram of the embodiment of FIG. 7(B). Qpl, Qp2. QpH, Qpl2 are P-channel type MOS) transistors, Qnl.

Qn2. Qnll to Qnl4 are N-channel MOs
S) transistor, PL is a circuit block composed of a P-channel type MO transistor, NL is a circuit block composed of an N-channel type MOS) transistor, 11 to Im (m is a natural number) is a P-channel type MOS) transistor. The input signals 11 to In (n is a natural number) to the configured circuit block PL are N-channel MOs.
An input signal to a circuit block NL composed of S transistors, 0 is an output signal, CC is a power supply voltage, VSS is a ground voltage, and INV is an inversion circuit.

First, FIG. 1(B) is a diagram showing a logical sum negation circuit as a specific example of the general example of the logic circuit of the present invention shown in FIG. 1(A).
This will be explained with reference to FIG. 1(C) which is a signal waveform diagram thereof. Regarding the circuit configuration, a first N-channel MOS transistor Qnll whose gate input is the first input signal 11 is connected between the output signal O and the ground voltage vSS.
and a second N-channel MOS transistor Qn12 whose gate input is the second input signal I2 are connected in parallel, and whose gate input is the first input signal 11 between the output signal O and the power supply voltage VCC. The first P-channel MO
S) Second P-channel type MOS transistor Q whose gate input is transistor QpH and second input signal ■2
A third P-channel MOS transistor Qpl whose gate receives a signal in phase with p12 and the output signal O is connected in series, and a fourth P-channel MOS transistor Qpl whose gate receives a ground voltage VSS.
A P-channel MOSI transistor Qp2 is connected in parallel with a third P-channel MOSI transistor Qpl. For circuit operation, input signal 1
1. When I2 are both logic voltage "L", P channel type MOS) transistor Qp l 1. Qp 12. Q
p2 is on, Qpl is off, N-channel MOS transistor QnllQn12 is turned off, and the output signal O becomes a logic voltage "H". Input signal 11. When at least one of I2 transitions to the logic voltage "H", at least one of the P-channel MOS transistors QpH and Qpl2 is turned off, and the N-channel MOS transistor Q
At least one of nll and Qnl2 is turned on, and the output signal O becomes a logic voltage "L". At this time, since the P-channel MOS transistor Qpl is off, the power supply voltage vCC is
2, the output signal 0 tends to transition to the logic voltage "L". Moreover, conversely, the input signal 11
．． When both I2 transition to the logic voltage "L", the P-channel MOS transistor Qpl is on, so the power supply voltage vCC is supplied through both the P-channel MOS transistors Qpl and Qp2, so the output signal O easily transitions to logic voltage "H". In this way, the P-channel MOS transistor Qpl inserted between the source of the circuit block PL made up of P-channel MOS transistors and the power supply voltage vCC works as a current control transistor, so the output signal O is fast. In addition to determining, in this example, the input signal I
When at least one of I and 12 transitions to logic voltage "H", the current flowing between the power supply voltages is small.

FIG. 2(A) shows that the P-channel MOS transistor Qp1, which is working for current control in FIG. The structure is inserted between the two, and the operation is the same as that in FIG. 1(A). FIG. 2(B) shows a logical AND NOT circuit as a specific example of FIG. 2(A).

Figure 3 (A) and Figure 3 (B) are respectively Figure 1 (A).
.

In the modification of FIG. 2(A), two sets of circuit blocks PL each composed of P-channel MOS transistors are prepared, and in the case of FIG. 3(A), P-channel MOS transistors are used for current control. The transistor Qpl is inserted between the source of one of the two-string circuit blocks PL and the power supply voltage vCC, and in the case of FIG. 3(B), it is a P-channel type transistor that works for current control. A MOS) transistor Qpl is inserted between the drain of one of the two-string circuit blocks PL and the output signal O, and its operation is the same as in FIG. 1(A).

Figure 4 (A) shows the P-channel MOS shown in Figure 1 (A).
In place of the P-channel MOS transistor Qpl inserted between the source of the circuit block PL composed of transistors and the power supply voltage vCC and working for power supply control, the circuit block NL is composed of an N-channel MOS transistor. An N-channel MOS transistor Qn is connected for current control between the source of
4(B) is a logical sum negation circuit as a specific example of FIG. 4(A), and FIG. 4(C) is a signal waveform diagram of FIG. 4(B). It shows. Regarding circuit operation, input signal 11. When both I2 are at logic voltage "L", P channel type Mos transistors QpH, Qp
12 is turned on, N-channel MOS) transistor Qn
11. Qn I 2 is turned off, Qnl and Qn2 are turned on, and the output signal 0 becomes a logic voltage "H". When at least one of the input signals II and 12 transitions to logic voltage "H", the P-channel MOS transistor Qp
At least one of the N-channel MOS transistors Qnll and Qnl2 is turned on, and the output signal 0 becomes the logic voltage "L".
” At this time, since the N-channel MOS transistor Qnl is on, the ground voltage VSS is supplied through both the N-channel MOS transistors Qnl and Qn2, so the output signal O becomes the logic voltage “L”. Conversely, when both input signals 11 and 12 transition to the logic voltage "L", the N-channel MO
Since the S transistor Qnl is off, the ground voltage vS
Since S is supplied only through the N-channel MOSI transistor Qn2, the output signal O is a logic voltage “H”.
”. In this way, N-channel MOS
N-channel MO inserted between the source of the circuit block NL composed of transistors and the ground voltage vss
Since the SI transistor Qnl works as a current control transistor, not only is the output signal O determined quickly, but in this embodiment, when the input signals 11 and 12 both transition to the logic voltage "L", the voltage between the power supply voltages is The current flowing through is small.

FIG. 5(A) shows that the N-channel MOS transistor Qnl working as a current controller in FIG. 5(A) connects the drain of the circuit block NL composed of N-channel MOS transistors with the output signal 0. The structure is inserted between the two, and the operation is the same as that in FIG. 4(A). FIG. 4(B) shows a logical AND NOT circuit as a specific example of FIG. 4(A).

Figure 6 (A) and Figure 6 (B) are respectively Figure 4 (A)
, in a modification of FIG. 5(A), two sets of circuit blocks NL each composed of N-channel MOS transistors are prepared,
In the case of Fig. 6 (A), N is working for current control.
A channel type MOS transistor Qnl connects the source of one of the two-string circuit blocks NL to a ground voltage vSS.
In the case of FIG. 6(B), an N-channel MOS (MOS) transistor Qnl working for current control is inserted between one of the two-string circuit blocks NL.
The configuration is inserted between two drains and the output signal O,
The operations are the same as in FIG. 4(A).

Figure 7 (A) shows the connection between the source of the circuit block PL composed of P-channel type MOSI transistors and the power supply voltage CC by using both Figure 1 (A) and Figure 4 (A) above. A P-channel MOS inserted in the
This circuit configuration includes a transistor Qpl and an N-channel MOS transistor Qnl inserted between the source of a circuit block NL composed of an N-channel MOS transistor and the ground voltage VSS and functioning for current control. FIG. 7(B) shows a logical OR NOT circuit as a specific example of FIG. 7(A), and FIG. 7(C) shows a signal waveform diagram of FIG. 7(B). For circuit operation, input signal 1
1. When both I2 are at the logic voltage "L", the P-channel MOS transistors QpHQp12. Qn2 is on, Qpl is off, and N-channel MOS) transistor Qn11. Qn12 is off, Qnl and Qn2 are on,
The output signal 0 becomes a logic voltage "H". input signal II,
When at least one of 12 transitions to logic voltage “H”, P-channel WMOS) transistors QpH, Qp
At least one of the 12 is off, and the N-channel type M
At least one of the OS transistors Qn11°Qnl2 is turned on, and the output signal O becomes a logic voltage "L".

At this time, the P-channel MOS transistor Qpl is turned off and the N-channel MOS transistor Qnl is turned on, so the power supply voltage VCC is
It is supplied only through the S transistor Qn2, and the ground voltage (SS is an N-channel MOS) transistor Qnl,
Qn2, so the output signal O is
It is easy to transition to logic voltage “L”. Conversely, when both input signals II and I2 transition to logic voltage "L", P channel type MOS transistor Qpl is turned on, and N
Since the channel type MOS transistor Qnl is off, the ground voltage VSS is supplied only through the N channel type MOS transistor Qn2, and the power supply voltage VCC is P
Since the output signal O is supplied through both transistors Qpl and Qp2 (channel type MOS), the output signal O is a logic voltage “H”.
"Transition to ".

In this way, the P-channel MOS transistor Qp is inserted between the source of the circuit block PL composed of P-channel MOS transistors and the power supply voltage VCC.
The output signal 0 is determined quickly because the N-channel MOS transistor Qnl inserted between the source of the circuit block NL made up of N-channel MOS transistors and the ground voltage Vss works as a current control transistor. In addition to input signals 11. When at least one of I2 transitions to the logic voltage "H" and when both input signals 11.degree. I2 transition to the logic voltage "L", the current flowing between the power supply voltages is small in both cases.

FIG. 8(A) is a modification of FIG. 7(A).
) P-channel type MOS working for current control
A transistor Qpl is inserted between the drain of a circuit block PL composed of P-channel MOS transistors and output signal 0, and two sets of circuit blocks NL composed of N-channel MOS transistors are prepared to control the current. The N-channel type MOS) transistor Qnl working as a
The configuration is inserted between two drains and the output signal O,
The operation is the same as in FIG. 7(A). Figure 8 (B
) shows an AND negation circuit as a specific example of FIG. 8(A).

In the conventional example, it is possible to reduce the through current between the power supply voltage and the ground voltage by increasing the gate length of the transistor or reducing the gate width, but this takes time for the output signal to transition, making it difficult to determine the output signal quickly. However, in the present invention, it is possible to quickly determine the output signal and to reduce the through current between the power supply voltage and the ground voltage.

As described in detail, according to the logic circuit of the present invention, the output signal can be determined quickly, and the current flowing between the power supply voltages can be reduced.
This has the great effect of making the entire circuit operate stably.

[Brief explanation of drawings]

1 to 8 (A) and (B) are diagrams showing embodiments of the logic circuit of the present invention, FIG. 1(C) is a signal waveform diagram of the embodiment of the core diagram (B), and FIG. Figure 4 (C) is Figure 4 (
FIG. 7(C) is a signal waveform diagram of the embodiment of FIG. 7(B).
) Signal waveform diagram of the embodiment of Fig. 9 (A) and (B)
9 is a diagram showing an embodiment of a conventional logic circuit, and FIG. 9(C) is a signal waveform diagram of the embodiment of FIG. 9(B). Qpl, Qp2. QpH, Qpl2...P channel type MOS) transistor, Qnl, Qn2Qnll
or Qnl4...N-channel MOS transistor, PL...Circuit block composed of P-channel MOS transistor, NL...
A circuit block composed of N-channel type MOS) transistors, I to 1 m (m is a natural number)...P
Input signal to circuit block PL composed of channel type MOS transistors, 11 to In (n is a natural number)... Input signal to circuit block NL composed of N channel type MOS transistors, O...
...Output signal, VCC...Power supply voltage, VS
S...Ground voltage, INV...Negation circuit.

Claims (4)

[Claims] (1) A first circuit block composed of a plurality of P-channel type MOS transistors, a plurality of first input terminals formed in the first circuit block, and a plurality of N
a second circuit block composed of channel-type MOS transistors, a plurality of second input terminals formed in the second circuit block, a drain of the first circuit block, and the second circuit block. is connected to the drain of the first circuit block, and the drain of the first circuit block is used as an output terminal;
A source of the second circuit block is connected to ground, a power supply terminal connected to the source of the first circuit block, and a signal output to the output terminal at a gate between the power supply terminal and the ground. The first M to which a signal in phase with is input
A logic circuit comprising a third circuit block in which an OS type transistor and a second MOS type transistor whose gate is connected to a ground voltage or a power supply voltage are connected in parallel. (2) In claim 1, the third circuit block is located between the source of the first circuit block and the power supply terminal, or between the drain of the first circuit block and the output terminal. or between the third circuit block and the source of the second circuit block and the ground;
Alternatively, the logic circuit is connected to at least one position between the drain of the second circuit block and the output terminal. (3) In claim 1, the third circuit block is located between the source of the first circuit block and the power supply terminal, or between the drain of the first circuit block and the output terminal. The MOS transistor constituting the third circuit block connected to at least one position between the two is a P-channel transistor, and the gate of the second MOS transistor is at ground voltage, or The third circuit block is connected to at least one position between the source of the second circuit block and the ground or between the drain of the second circuit block and the output terminal. A logic circuit characterized in that the MOS type transistor constituting the logic circuit is an N-channel type transistor, and the gate of the second MOS type transistor is connected to a power supply voltage. (4) In claim 1, the first circuit block or the second circuit block is composed of a plurality of blocks, and at least one of the blocks
A logic circuit characterized in that the third circuit block is connected to the third circuit block.