JPH0456160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure a sufficient capacitor capacitance and to enhance reliability by a method wherein a tantalum oxide film is used as a capacitor insulating film and regions, as an upper-part electrode and a lower-part electrode, which come into contact with at least the capacitor insulating film are constituted of a material by which the arithmetic mean of work function values becomes a specific value. CONSTITUTION:When a DRAM of a laminated memory cell structure is manufactured, a tungsten film 109 is formed and patterned and a capacitor lower-part electrode 109 is formed. After that, a tantalum oxide film to be used as a capacitor insulating film 110 is formed by a CVD method. Lastly, a platinum film as a capacitor upper-part electrode 111 is formed on the whole surface; after that, it is patterned by using a photoetching method; a memory cell is formed. The tantalum oxide film 110 is used as the capacitor insulating film; a material whose arithmetic means of work function values is 4.7eV+ or -0.2eV is used for the upper-part and lower-part electrodes. Thereby, even when this semiconductor device is integrated highly, a leakage current is reduced, a sufficient capacitor capacitance is maintained and a charge-holding ability can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a capacitor structure in a DRAM or the like.

(Prior Art) One of the semiconductor devices is a DRAM (Dyn
naa+ic RandolW Access r
ead write Memory).

In recent years, due to advances in semiconductor technology, particularly advances in microfabrication technology, so-called MO5 type DRAMs are rapidly becoming more highly integrated and have larger capacities.

With this increase in integration, the area of capacitors that store information (charge) has decreased, resulting in problems such as erroneous reading of memory contents or soft errors in which memory contents are destroyed by alpha rays, etc. It has become.

Furthermore, there is an increasing need not only to reduce the capacitor area, but also to reduce the dimension in the thickness direction due to the demand for higher precision of element patterns. Under these circumstances, capacitor insulating films are becoming thinner and thinner, and it has become almost impossible to obtain capacitor capacitance on the side surfaces.

Conventionally, silicon oxide films have been used as capacitor insulating films, but in order to compensate for the decrease in capacitor capacity due to miniaturization, silicon nitride films or tantalum oxide films, which have a higher dielectric constant than silicon oxide films, are used as insulating films. is being considered.

In particular, tantalum oxide is a promising material because its dielectric constant is about seven times higher than that of silicon oxide.

However, the band gap of tantalum oxide is about 4°7 eV.
Since the current is small, the problem is that the leakage current is large. In order to suppress such leakage current, a method has been proposed in which, for example, a silicon oxide film or a silicon nitride film with a larger band gap is provided at the interface between the underlying silicon and tantalum oxide.

However, given the limitations on film thickness, interposing silicon oxide or silicon nitride, which have a low dielectric constant, leads to a corresponding decrease in capacitance.

As described above, it is extremely difficult to suppress leakage current while ensuring sufficient capacitor capacity.

(Problems to be Solved by the Invention) As described above, in conventional capacitors, it is extremely difficult to suppress leakage current while ensuring sufficient capacitance.

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a highly reliable capacitor that can secure sufficient capacitor capacity despite the reduction in the area occupied by memory cells. do.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, a tantalum oxide film is used as a capacitor insulating film, and the arithmetic average of the work function values of at least the regions in contact with the capacitor insulating film as the upper and lower electrodes is 4.5 eV or more. It is made of a material that provides a voltage of 4.9 eV or less.

Preferably, at least a region of the upper electrode in contact with the capacitor insulating film is made of tungsten, and at least a region of the lower electrode in contact with the capacitor insulating film has an arithmetic average work function with tungsten of 4°5 eV or more and 4.9 eV or less. It is made of materials selected as such.

Preferably, the lower electrode is made of n0 type polycrystalline silicon or tungsten, and the upper electrode is made of:
I try to use nickel or palladium.

(Function) First, let's consider the band diagram of the tantalum oxide film and the upper and lower electrodes.

Letting the work functions of the upper electrode and the lower electrode be φφ2, the respective barrier heights V, , V2 and the potential difference ΔV generated in the membrane are expressed as shown in the figure.

Conduction in tantalum oxide films is based on the Pool-Frencke
It is said to be type l, and the current is determined by the barrier height and the voltage applied to the membrane. Therefore, the width of the forbidden band in the insulating film can be used as an approximate guide for estimating the amount of current flowing.

And if both barrier heights V, V2 are small,
The forbidden band above the Fermi level becomes smaller, making it easier for electron current to flow.

On the other hand, if both barrier heights V, V2 are large,
Since the width of the forbidden band below the Fermi level becomes smaller, hole current flows more easily. Since these currents increase exponentially as the width of the forbidden band becomes smaller, it can be seen that the leakage current is the smallest even when the width of the forbidden bands located above and below the Fermi level is equal. As is clear from the figure, such conditions apply to φ7. This is a case where the average value of φ2 is 4.7 eV.

Furthermore, leakage current was measured using tungsten as one electrode and variously selected materials for the other electrode. The horizontal axis is the average of the work function, and the electric field strength at that time is 6 MV.
FIG. 5 shows a diagram in which the value of leakage current is plotted on the vertical axis.

From this result, the average value of the work function of the upper and lower electrodes is 4.
．． It can be seen that by selecting a value within 7 eV±0.2 eV, the leakage current can be suppressed to within one order of magnitude. By suppressing the leakage current to this level, a highly reliable upper capacitor suitable for LSI can be provided.

The work functions of materials used as electrode materials are shown in the table below.

From this table, for example, when the lower electrode is made of n-grown polycrystalline silicon or tungsten, the upper electrode may be selected from nickel, palladium, or p-grown crystalline silicon.

As described above, according to the present invention, it is possible to provide a capacitor that has low leakage current, sufficient capacitance, and excellent charge retention ability.

Note that the upper and lower electrodes are set at the average value of their work functions, or 4°7 eV.
Ideally, it should be selected so that ±0.2e
It suffices if it falls within about V.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

1(a) to 1(d) show the manufacturing process of a DRAM with a stacked memory cell structure according to an embodiment of the present invention, using tungsten as the lower electrode, tantalum oxide as the capacitor insulating film, and palladium as the upper electrode. It is a diagram.

First, as shown in FIG. 1(a), the impurity concentration is 1015.
Within 1°1 of a p-type silicon substrate of ~1016c-,
An element isolation insulating film 102 is formed by a normal LOCOS method. Then, a silicon oxide layer 103 with a thickness of 200nI and a polycrystalline silicon layer 104 with a thickness of 300nI are deposited by a thermal oxidation method, and patterned by a photolithography method and a reactive ion etching method to form a gate insulating film 103 and a gate electrode 104. Form. Furthermore, using this gate electrode 104 as a mask, As ions are implanted to form source/drain regions consisting of an n-type wave dispersion layer 105, thereby forming a MOSFET as a switching transistor.

Furthermore, as shown in FIG. 1(b), in this upper layer, CV
A silicon oxide film 10 with a thickness of about 1500A is formed by the D method.
6, the storage node contact 1 is formed by photolithography, reactive etching, and ion etching.
07 is formed.

After this, as shown in FIG. 1(C), a film thickness of 80 mm is applied to the entire surface.
After depositing and doping a 0A polycrystalline silicon film 108, it is patterned by photolithography and chemical dry etching (isotropic etching), and then a tungsten film 10 is formed on top of this by sputtering.
9 is formed and patterned to form a capacitor lower electrode 109.
form. Thereafter, a tantalum oxide film that will become the capacitor insulating film 110 is formed by CVD.

Finally, as shown in FIG. 1(d), after forming a platinum film on the entire surface as the capacitor upper electrode 11,
Patterning is performed using conventional photolithography to form memory cells.

The leakage current characteristics of the DRAM thus formed are shown in curves C and d in FIG. Here, the curve C is
When the lower electrode is negative and the upper electrode is positive, curve d shows the leakage characteristics when the lower electrode is positive and the upper electrode is negative. For comparison, leakage characteristics when Al and n-grown crystalline silicon are used as upper and lower electrodes are similarly shown in curves a and 2.

From these comparisons, it can be seen that the DRAM of the embodiment of the present invention has significantly reduced leakage.

According to the DRAM formed in this manner, since the tantalum oxide film serving as the capacitor insulating film is sandwiched between the 10 lower electrodes made of the capacitor or tungsten film and the upper electrode made of nickel, leakage current is small and the capacitor is Since it is constructed with a large capacitor and a large charge retention capacity, it is highly reliable with fewer malfunctions.
RA hi can be obtained.

Example 2 Next, a second example of the present invention will be described in detail with reference to the drawings.

FIGS. 2(a) to 2(d) show a stacked memory cell according to an embodiment of the present invention using n-grown crystalline silicon as the lower electrode, tantalum oxide as the capacitor insulating film, and p-grown crystalline silicon as the upper electrode. 3 is a manufacturing process diagram of a DRAM of this structure.

First, as in Example 1, as shown in FIG. 2(a),
An element isolation insulating film 202 is formed in a p-type silicon substrate 201 with an impurity concentration of about 1015 to 1016C11-3 by the usual LOCO3 method. Then, a silicon oxide layer 203 with a thickness of 20 Or+s+ and a polycrystalline silicon layer 204 with a thickness of 300 nIm are deposited by a thermal oxidation method, and patterned by a photolithography method and a reactive ion etching method to form a gate insulating film 203 and a gate electrode. 204 is formed.

Furthermore, using this gate electrode 204 as a mask, AS ions are implanted to form a source/train region consisting of an n-type wave dispersion layer 205, thereby forming a MOSFET as a switching transistor.

Furthermore, as shown in FIG. 2(b), in this upper layer, CV
A silicon oxide film 20 with a thickness of about 150 OA is formed by the D method.
6, the storage node contact 20 is formed by photolithography and reactive ion etching.
form 7.

After this, as shown in FIG. 2(C), a film thickness of 80 mm is applied to the entire surface.
A polycrystalline silicon film 208 is deposited and doped with n-grown crystalline silicon Ii! 208, patterning is performed by photolithography and chemical dry etching (isotropic etching), and furthermore, CV
A tantalum oxide film that will become the capacitor insulating film 210 is formed by method D.

Finally, as shown in FIG. 2(d), after forming a polycrystalline silicon film on the entire surface as the capacitor upper electrode 211, boron ions are implanted and annealing is performed in a nitrogen atmosphere at 800°C. Patterning is performed using photolithography to form memory cells.

The leakage current characteristics of the DRAM thus formed are shown in FIG. 3 as curves e and f. Here, the curve e is
When the lower electrode is positive and the upper electrode is negative, the curve f shows the leakage characteristics when the lower electrode is negative and the upper electrode is positive.

According to the DRAM thus formed, the capacitor has a lower electrode 109 made of an n-grown crystalline silicon film and a p-type crystal silicon film.
Since the tantalum oxide film as the capacitor insulating film is sandwiched between the upper electrode made of a grown crystalline silicon film, there is little leakage current, the capacitor has a large capacitance, and the capacitor is made of a material with a large charge retention capacity, which prevents malfunctions. Therefore, a highly reliable DRAM can be obtained.

Furthermore, here, the leak characteristics when the lower electrode is changed to nickel and the other parts are formed in the same manner are shown as curve g and curved line. Here, the curve g shows the leakage characteristics when the lower electrode is set as positive and the upper electrode is set as negative, and the curved line represents the leakage characteristic when the lower electrode is set as negative and the upper electrode is set as positive.

It can be seen that the leakage current is reduced in this case as well.

In addition, as the upper and lower electrodes of the capacitor,
Although a polycrystalline silicon film or the like is used, it is not necessarily limited to these, and metals, metal alloys, etc. can be suitably changed within the range that satisfies the conditions of the present invention.

Furthermore, the same effect can be obtained even if the upper and lower electrodes have a multilayer structure and the constituent materials of the regions in contact with the capacitor insulating film are selected so that the arithmetic average is 4.7 eV or more.

In these embodiments, a DRAM having a stacked capacitor structure has been described, but the present invention is also applicable to a DRAM having a trench structure.

〔Effect of the invention〕

As explained above, according to the capacitor of the present invention, a tantalum oxide film is used as the capacitor insulating film, and the arithmetic average of the work function values of the upper and lower electrodes is 4.7.
Since a material that provides eV±0.2'eV is used, even when increasing integration, leakage current can be reduced, sufficient capacitance can be maintained, and charge retention ability can be increased.

[Brief explanation of the drawing]

1(a) to 1(d) are manufacturing process diagrams of a DRAM having a stacked memory cell structure according to a first embodiment of the present invention, and FIG.
2(a) to 2(d) are manufacturing process diagrams of a DRAM with a stacked memory cell structure according to a second embodiment of the present invention, and FIG. 3 is a diagram showing a DRAM capacitor according to the present embodiment and a conventional DRAM
FIG. 4 is a diagram showing the band structure of the capacitor, and FIG. 5 is a diagram showing the relationship between the arithmetic average of the work functions of the materials forming the upper and lower electrodes and the Lini-multiple current. 101... P-type silicon substrate, 102... Element isolation insulating film, 103... Gate insulating film, 104... Gate electrode, 105... N-type diffusion layer, 106... Interlayer insulating film , 107 --- Storage node contact,]
08... n-type polycrystalline silicon layer, 109... tungsten film, 110... tantalum oxide film (capacitor insulating film), 111'... n-type polycrystalline silicon layer, 2
゜1... P-type silicon substrate, 202... Element isolation insulating film, 203... Gate insulating film, 204... Gate electrode, 205... N-type diffusion layer, 206... Interlayer insulation Membrane, 2゜7...Storage node contact, 20
8...n+ type polycrystalline silicon layer, 210... tantalum oxide film (capacitor insulating film), 211...p small polycrystalline silicon layer.

Claims (3)

[Claims] (1) In a capacitor in which a tantalum oxide film is used as a capacitor insulating film, and this capacitor insulating film is sandwiched between an upper electrode and a lower electrode, the material of the upper electrode and the lower electrode that constitutes at least the region in contact with the capacitor insulating film is A semiconductor device characterized in that the arithmetic mean of work function values is selected to be 4.5 eV or more and 4.9 eV or less. (2) In a capacitor in which a tantalum oxide film is used as a capacitor insulating film, and this capacitor insulating film is sandwiched between an upper electrode and a lower electrode, at least a region of one of the two electrodes in contact with the capacitor insulating film is made of tungsten, A semiconductor characterized in that at least the region of the other electrode in contact with the capacitor insulating film is made of a material selected so that the arithmetic mean of the work function with tungsten is 4.5 eV or more and 4.9 eV or less. Device. (3) In a capacitor in which a tantalum oxide film is used as a capacitor insulating film and this capacitor insulating film is sandwiched between an upper electrode and a lower electrode, at least one of the upper and lower two regions of the upper electrode and the lower electrode that is in contact with the capacitor insulating film is A semiconductor device characterized in that the other layer is made of n^+ polycrystalline silicon and the other layer is made of nickel or palladium.