KR940007460B1 - Field effect transistor, semiconductor memory device and manufacturing method of field effect transistor using same - Google Patents

Abstract

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Description

Field effect transistor, semiconductor memory device and manufacturing method of field effect transistor using same

1 is a plan view showing one embodiment of the present invention.

2 is a sectional view taken along the line II-II of FIG.

3 is a cross-sectional view taken along the line III-III of FIG.

4A to 4G are cross-sectional views sequentially showing a manufacturing process of the one shown in FIG.

5 is a plan view showing a conventional memory cell.

6 is an equivalent circuit diagram of what is shown in FIG.

FIG. 7 is a cross sectional view along line VII-VII of FIG. 5;

* Explanation of symbols for main parts of the drawings

1: P-type silicon semiconductor substrate 2: Field oxide film

3: n ⁺ type drain area 4: n type source region

5 channel region 6 gate oxide film

7: bit line BL ₀ 8: conductive layer D ₀

9: bit line 10: bit line

11: interlayer oxide film 12, 13: oxide film side wall

14 gate electrode 15 interlayer oxide film

16: titanium silicide film 17: contact hole (CH ₁ )

18: interlayer oxide film 19: oxide film side wall

20: capacitor lower electrode (E ₀ ) 21: dielectric film

22: capacitor upper electrode (E ₁ ) 23: BPSG film

24: memory cell C ₁ 25: memory cell C ₂

26: contact hole (CH ₀ ) 27: word line (WL ₁ )

(The same reference numerals in each drawing indicate the same or equivalent parts.)

The present invention relates to a semiconductor memory device and a manufacturing method thereof. Dynamic, random, access, and memory (hereinafter referred to as DMAM) have achieved four times higher integration almost every three years over the past decade.

This trend is not weak, even in the current 4M bit level, and is expected to continue in the future. However, high integration is highly dependent on miniaturization of memory cells, and problems such as soft errors are caused due to the reduction in capacity accompanying miniaturization.

Therefore, memory cells having new structures, such as groove type (transistor type) capacitors in which semiconductor substrates are etched into grooves or stacked type (stack type) capacitors stacked on semiconductor substrates, have been developed so as to secure a predetermined value or more.

FIG. 5 is a plan view showing a memory cell of a DRAM having a stacked capacitor, for example, disclosed in Japanese Patent Application Laid-Open No. 60-2784, and FIG. 6 is an equivalent circuit diagram of that shown in FIG.

In FIG. 5, memory cells C ₀ and C ₁ are provided at intersections of word lines WL ₀ and WL ₁ and bit lines BL ₀ , and word lines WL ₂ and WL ₃ and bit lines. Memory cells C ₂ and C ₃ are installed at the intersection with each other. The capacitor of each memory cell is composed of an oxide film (not shown in Fig. 5) between the lower electrode E ₀ and the upper electrode E ₁ and these electrodes.

In addition, CH is a bit line (BL ₀ , ) Is a contact hole for connecting the impurity diffusion region of the semiconductor substrate.

In Fig. 6, SA is a sense amplifier that detects and amplifies a signal from each memory cell.

7 is a cross-sectional view taken along the line VII-VII of FIG.

In the figure, reference numeral 31 denotes a p-type silicon semiconductor substrate, 32 denotes a field oxide film as an element isolation region formed on one main surface of the p-type silicon semiconductor substrate 31, and 33 is separated by this field oxide film 32. N ⁺ type drain region formed of island-like islands, 34, n ⁺ type source region formed in island regions separated by field oxide film 32, similarly to n ⁺ type drain region 33, (35 Is a channel region formed between the n ⁺ type drain region 33 and the n ⁺ type source region 34, 36 is a gate oxide film formed on the channel region 35, and 37 is The gate electrodes (word lines WL ₁ ) and 38 formed of polysilicon layers formed on the gate oxide film 36 in the orthogonal direction to the channel region 35 are formed of interlayer oxide films formed on the surface of the gate electrode 37. 39 is a word line WL ₂ made of a polysilicon layer formed on the field oxide film 32, and 40 is a word line WL. ₂ ) an interlayer oxide film formed on the surface of 39, 41 is in contact with the n ⁺ type source region 34 and the field oxide film 32, and between the interlayer oxide film 38 on the surface of the gate electrode 37 Capacitor bottom electrodes E ₀ and 42 formed opposite to each other and formed opposite to each other with the interlayer oxide film 40 interposed therebetween on the surface of the word line WL ₂ 39 are formed. formed on the surface of the capacitor lower electrode (E ₀₎ (41) inter-layer oxide film, 43 is a poly formed in opposition sandwiching the interlayer oxide film 42 on the surface of the capacitor lower electrode (E ₀₎ (41) Capacitor upper electrodes (plate electrodes) E ₁ and 44 made of a silicon layer are PSG films formed on the entire surface of one main surface of the p-type silicon semiconductor substrate 31, and 45 are n ⁺ type drain regions 33. ), the contact holes (CH) opening to the surface of, 46 is a contact hole (CH) (45) interposed between the n ⁺ type drain Station 33 and the connection and the channel region (35) and made of aluminum metal is formed in parallel direction, the bit lines (BL _0), (47) is the p-type silicon semiconductor substrate (31) to said bit line (BL ₀₎ It is a memory cell C ₁ constituted by 46.

The conventional memory cell (C ₁ ) 47 is configured as described above, and a part of the capacitor lower electrode (E ₀ ) 41 and the capacitor upper electrode (E ₁ ) 43 is formed on the gate electrode 37 and the word line. Since it is curved and extended to (WL ₂ ) (39), the area of the capacitor can be increased to ensure the capacity.

In the conventional memory cell (C ₁ ) 47 as described above, the capacitor lower electrode (E ₀ ) 41 and the capacitor upper electrode (E ₁ ) 43 are stacked on one circumferential surface of the p-type silicon semiconductor substrate 31. As a result, the step from the one circumferential surface of the p-type silicon semiconductor substrate 31 becomes severe and the aspect ratio (aspect ratio) of the contact hole (CH) 45 increases.

Increasing this aspect ratio has a problem that the coverage of the bit lines BL ₀ 46 is deteriorated, leading to disconnection inside the contact holes CH 45 and lowering reliability.

In addition, in order to form the contact hole (CH) 45 having a high aspect ratio, a photolithography process with high precision is required and there is a problem involving technical difficulties in manufacturing.

Again, in the conventional memory cell C ₁ 47 as described above, the gate (word line WL ₁ ) 37 is also miniaturized toward high integration, so that the resistance of the gate electrode (word line WL ₁ ) 37 is reduced. This increases and the delay of the signal must be taken into account. Therefore, it was necessary to further speed up without delaying the signal.

Again, it was necessary to further secure the capacity from the point of miniaturization.

The present invention has been made to solve the above-mentioned problems, and a field effect transistor capable of realizing high-speed operation, a memory cell capable of sufficiently securing the capacitance of the capacitor, and a reduction in reliability caused by disconnection of the bit line are again prevented. It is an object to obtain a semiconductor memory device that can be suppressed.

The field effect transistor according to the present invention is connected to one of a set of impurity diffusion regions connected to one side of a set of impurity diffusion regions provided on one main surface of a silicon semiconductor substrate with a channel region interposed therebetween, and to the other side of the set of impurity diffusion regions. And a gate electrode formed between the formed second conductive layer, the insulating film on the channel region, the insulating film on the first conductive layer, and the insulating film on the second conductive layer.

The memory cell according to the second aspect of the present invention is a gate electrode and a set of impurity diffusions formed with a set of impurity diffusion regions provided with a channel region on one surface of a silicon semiconductor substrate and an insulating film on the channel region. A first conductive layer formed by connecting to one of the regions, one electrode of the capacitor formed by being electrically connected to the first conductive layer, and the other electrode of the capacitor formed with the dielectric film on the electrode interposed therebetween; And a second conductive layer formed by being electrically connected to the gate electrode and formed with an insulating film on the other electrode of the capacitor interposed therebetween.

Again, the semiconductor memory device according to the third aspect of the present invention comprises an insulating film formed by separating element formation regions on one main surface of a silicon semiconductor substrate, and a set of impurity diffusion regions provided with a channel region interposed therebetween. A first conductive layer formed on an insulating film in contact with one set of impurity diffusion regions and connected to the other side of a set of impurity diffusion regions and in contact with the other of the impurity diffusion regions. And a second conductive layer formed on the insulating film.

Again, the method of manufacturing a field effect transistor according to the fourth aspect of the present invention separates the element formation region from one main surface of the silicon semiconductor substrate so that the first insulating film is in contact with the region and a part of the region in the element formation region. The first conductive layer is formed on the first insulating layer, and the second conductive layer is formed on a part of the region facing the first conductive layer in the element formation region and on the first insulating layer in contact with the region. The second insulating film on the side of the layer, the third insulating film on the side of the second conductive layer, the insulating film on the element formation region between the second insulating film and the third insulating film and on the first conductive layer The gate electrode is used on the insulating film and the insulating film on the second conductive layer, and the impurity diffusion region is formed by ion implanting impurities of a silicon semiconductor substrate and a reverse conductive type using this gate electrode as part of a mask.

In the field effect transistor configured as described above, both ends of the gate electrode in the parallel direction with the channel region are formed on the first conductive layer and the second conductive layer to suppress the resistance of the gate electrode.

In the memory cell constructed as described above, a capacitor located above the bit line and below the word line is formed to extend on the bit line through the gate electrode, thereby increasing the capacitor area.

In the semiconductor memory device configured as described above, the bit lines are formed by connecting the impurity regions without interposing the contact holes to prevent disconnection of the bit lines due to the increase in the aspect ratio.

In addition, in the method of manufacturing the field effect transistor configured as described above, since the gate electrode is formed after the first conductive layer and the second conductive layer are formed without interposing a contact hole, a highly accurate photolithography process is performed. The first conductive layer and the second conductive layer are connected to the impurity diffusion region without any problem.

EXAMPLE

1 is a plan view showing one embodiment of the present invention.

In the drawing, the word line WL ₁ and the bit line ( The memory cells C ₀ and C ₁ are provided at the intersections of BL ₀ and the word lines WL ₂ and the bit lines BL ₀ , ) C _2, to the memory cell junction (in the C ₃₎ have been installed and the word line (WL ₀₎ and a bit line (memory cell (C ₄₎ to the junction and BL ₁₎ is provided a word line (WL ₃₎ and Bit line ( ) Is installed at the intersection with the memory cell (C ₅ ). The capacitor of each memory cell is composed of an oxide film (not shown in FIG. ₁ ) between the lower electrode E ₀ and the upper electrode E ₁ and these electrodes.

CH ₀ is a contact hole for connecting the word lines WL ₀ -WL ₃ to the gate electrode, and CH ₁ is a contact hole for connecting the lower electrode E ₀ to the conductive layer D ₀ .

2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line III-III of FIG.

In Fig. 2, reference numeral 1 denotes a p-type silicon semiconductor substrate having a resistivity of 10 Ω · cm at a concentration of 1 × 10 ¹⁵ cm ^-3 , and (2) represents an element isolation region formed on one main surface of the p-type silicon semiconductor substrate 1. The field oxide film (3) has a concentration of 1 × 10 ²⁰ cm ⁻ formed by ion implantation of arsenic in an island region separated by the field oxide film 2 under an acceleration voltage of 50 KeV and a dose of 4 × 10 ¹⁵ cm ^-2 . ³ n ⁺ type drain region, 4 is an n ⁺ type drain region 3 amount and, like the field to accelerate the non-small voltage to the island region isolated by an oxide film (2) 50KeV, dose 4 × 10 ¹⁵ ㎝ ^- N ⁺ type source region having a concentration of 1 × 10 ²⁰ cm ⁻³ formed by ion implantation under the condition of ² , (5) between the n ⁺ type drain region 3 and the n ⁺ type source region 4 A channel region formed in the channel region (6) is a gate oxide film formed on the channel region (5), and (7) is electrically connected in part to the n ⁺ type drain region (3) Further, conductive layers (bit lines BL ₀ ) formed on the surface of the field oxide film 2 and formed in a direction orthogonal to the channel region 5 (bit line BL ₀ ), 8 denote the n ⁺ type source region. The conductive layers D ₀ and 9 made of a polysilicon layer which is electrically connected to one end in contact with (4) and formed to face the surface of the field oxide film 2 are opposite to the surface of the field oxide film 2. A conductive layer made of a polysilicon layer orthogonal to the channel region 5 (bit line ( ), 10 is the bit line ( (9) and a conductive layer made of a polysilicon layer facing the surface of the field oxide film (2) and formed in a direction orthogonal to the channel region (5). ) And 11 denote the conductive layer D ₀ on the n ⁺ type drain region 3 with the bit lines BL ₀ and 7 interposed therebetween or on the n ⁺ type source region 4. An interlayer oxide film formed between the channel region 5 and opposite to the surface of the field oxide film 2 in a direction orthogonal to the channel region 5, and the interfacial oxide film 12 is in contact with the n ⁺ type drain region 3 The conductive layer (D ₀ ) 8 and the interlayer oxide film 11 formed on side surfaces of the bit line BL ₀ and the interlayer oxide film 11, or in contact with the n ⁺ type source region 4. (13) is an oxide film side wall formed on the side surface, and (13) is in contact with the field oxide film (2) and the conductive layer (D ₀ ) (8), (9) or the bit line ( The side wall of the oxide film formed on the side of the (10), (14) is formed in the island-like region separated by the field oxide film (2), the bottom surface is in contact with the gate oxide film (6) and parallel to the channel region (5) The side surface in the direction is formed in contact with the interlayer oxide film 11 and the oxide side wall 12 and the bottom surface of the field oxide film 2 in the direction orthogonal to the channel region 5 faces the interlayer oxide film 11. A gate electrode made of a polysilicon layer added with phosphorus (P) formed in contact with each other, (15) is an interlayer oxide film formed to face the surface of the gate electrode (14), and (16) the bit lines (BL ₀ ) (7). , The conductive layer (D ₀ ) 8, the bit line ( 9 and the bit line ( Titanium silicide film formed on the surface of (10), (17) is a contact hole (CH ₁ ), (18) opened on the surface of the titanium silicide film 16 formed on the surface of the conductive layer (D ₀ ) (8) ) Is an interlayer oxide film formed on the entire surface on one circumferential surface of the p-type silicon semiconductor substrate 1 except a portion on the conductive layer D ₀ and 8 and a portion on the gate electrode 14, and 19 is the conductive layer. (D ₀ ) an oxide film side wall formed in contact with the titanium silicide film 16 on (8) and on the side surfaces of the interlayer oxide film 11, the gate electrode 14, and the interlayer oxide film 15, 20 is the contact The capacitor lower electrode E ₀ made of a polysilicon layer formed by being connected to the titanium silicide film 16 with the holes CH ₁ 17 interposed therebetween and extending up to the bit lines BL ₀ 7. ), 21 dielectric layer formed on the surface of the capacitor lower electrode _{(E 0) (20),} (22) is in the surface of the capacitor lower electrode (E ₀₎ (20) A capacitor upper electrode formed of a polysilicon layer formed toward left for between the dielectric layer 21 (plate electrode) (E _1), (23) is a BPSG film formed in a week planar front surface of the p-type silicon semiconductor substrate 1, 24 denotes the p-type silicon semiconductor substrate 1 to the bit line ( (9) and the memory cells C ₁ and 25 composed of the interlayer oxide films 11 to BPSG films 23 are p-type silicon semiconductor substrates 1 to conductive layers D ₀ . And the bit line ( (10) to the memory cell C ₂ composed of the BPSG film 23.

In FIG. 3, reference numeral 26 denotes contact holes CH ₀ opened on the surface of the gate electrode 14 and reference numeral 27 denotes the gate electrode 14 with contact holes CH ₀ 26 interposed therebetween. Is a word line WL ₁ made of aluminum metal formed in parallel with the channel region 5.

Next, the manufacturing process of the memory cells C ₁ 24 and C ₂ 25 configured as described above will be described with reference to FIGS.

First, as shown in FIG. 4A, oxidation is selectively performed on one main surface of the p-type silicon semiconductor substrate 1 having a concentration of 1 x 10 ¹⁵ cm ^-3 and a specific resistance of 10 Ω · cm, to form a field oxide film 2.

Subsequently, a polysilicon layer is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by the CVD method, and a part of the region on the field oxide film 2 is etched.

Next, as shown in FIG. 4B, an interlayer oxide film 11 is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by the CVD method, and the island-like region separated by the field oxide film 2 is formed. A portion of the region is etched including the polysilicon layer to form the bit lines BL ₀ (7) and ( (9), ( 10 and the conductive layer D ₀ (8) are formed.

Subsequently, when an oxide film is formed on the entire surface of the main surface of the p-type silicon semiconductor substrate 1 by CVD, and reactive ion etching (anisotropy) is used to remove the oxide film, the island-like region separated by the field oxide film 2 is formed. An oxide film side wall 12 is formed on the side surfaces of the bit lines BL ₀ , 7, conductive layers D ₀ , 8, and the interlayer oxide film 11.

Next, as shown in FIG. 4C, a gate oxide film 6 is formed on one main surface of the exposed p-type silicon semiconductor substrate 1.

Subsequently, a polysilicon layer added with phosphorus (P) and an interlayer oxide film 15 are sequentially stacked on the entire main surface of the p-type silicon semiconductor substrate 1 by CVD, and a part of them is deposited on the field oxide film 2. The gate electrode 14 is formed by etching so as to remain on the island-like region separated by the above-mentioned region and the field oxide film 2 adjacent to the island-like region.

At this time, the interlayer oxide film 11 except for the region formed under the gate electrode 14 is etched and the bit lines BL ₀ (7), ( (9), ( ) 10 and the surface of conductive layer D ₀ (8) are exposed.

Again, the bit line on the field oxide film 2 ( (9), ( An oxide film side wall 13 is formed on the side surface of the () 10 and the conductive layer (D ₀ ) 8.

Thereafter, the gate electrode 14 interlayer oxide film 15 is used as a mask from one side of the bit line BL ₀ (7) and the conductive layer D ₀ (8) to one peripheral surface of the p-type silicon semiconductor substrate 1. Arsenic ion implantation under accelerated voltage 50KeV and dose amount 4 × 10 ¹⁵ cm ^-2 , followed by annealing at 900 ° C. results in n ⁺ type drain region 3 and n ⁺ type with a concentration of 1 × 10 ²⁰ cm ^-3 . The source region 4 is formed. A channel region 5 is formed between the n ⁺ type drain region 3 and the n ⁺ type source region 4.

Next, as shown in FIG. 4D, a titanium film is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by the sputtering method and subjected to heat treatment at 600 to 700 ° C. by the lamp annealing method to form a bit line (BL). ₀ ) (7), ( (9), ( Polysilicon and titanium forming the (10) and the conductive layer (8) cause a silicide reaction.

Subsequently, the titanium film on the field oxide film 2, the oxide film side wall 13 and the interlayer oxide film 15 was etched away with a solution of ammonium hydroxide / hydrogen peroxide (NH ₃ , H ₂ O / H ₂ O ₂ ), and a lamp annealing method was performed. The titanium silicide film 16 is formed when the heat treatment is performed at 800 ° C. or higher.

Next, as shown in FIG. 4E, an oxide film is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by CVD.

Subsequently, reactive ion etching (anisotropy) is used to remove a portion of the oxide film on the conductive layer D ₀ and 8 and a portion of the oxide film on the gate electrode 14 to the surface of the conductive layer D ₀ . When the surface of the formed titanium silicide layer 16 is exposed, a contact hole (CH ₁ ) 17 is formed.

At this time, the oxide film left without being removed forms an interlayer oxide film 18 and an oxide film side wall 19 is formed on the side surfaces of the interlayer oxide films 11 and 15 and the gate electrode 14.

Next, as shown in FIG. 4F, a polysilicon layer is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by the CVD method, and a part of the polysilicon layer is interposed between the contact holes (CH ₁ ) 17. It is connected to the titanium silicide film 16 and is etched so as to remain on the bit lines BL ₀ and 7 to form a capacitor lower electrode E ₀ 20.

Next, as shown in FIG. 4G, when a nitride film is formed on the surface of the capacitor lower electrode (E ₀ ) 20 by CVD and heat-treated in an oxidizing atmosphere, an oxide film is formed on the nitride film and the dielectric film 21 is formed. Get

Subsequently, a polysilicon layer is formed on the entire surface of the p-type silicon semiconductor substrate 1 except for a part of the region of the gate electrode 14 on the field oxide film 2 by CVD to form a lower portion of the capacitor. The capacitor upper electrode (plate electrode) E ₁ (22) facing each other with the dielectric film 21 interposed on the surface of the electrode (E ₀ ) 20 is used.

After that, the BPSG film 23 is formed on the entire surface of the p-type silicon semiconductor substrate 1 by the CVD method, and a part of the region where the capacitor upper electrode E ₁ 22 is not formed is formed in the interlayer oxide film (11). In addition, the contact hole (CH ₀ ) 26 (not shown in FIG. 2) is formed when the surface of the gate electrode 14 is exposed by etching (18).

Again, an aluminum metal is formed on the entire surface of the p-type silicon semiconductor substrate 1 by sputtering, a part of which is connected to the gate electrode 14 with the contact holes (CH ₀ ) 26 interposed therebetween, and the channel region ( When etching is performed to remain in the parallel direction with 5), and the word lines WL ₁ 27 (not shown in FIG. 2) are formed, the memory cells C ₁ 24 and C ₂ 25 are formed. ) Is completed.

In the semiconductor memory device configured as described above, both ends of the gate electrode 14 in the parallel direction with the channel region 5 are formed on the interlayer oxide film 11 or the conductive layer D ₀ on the bit lines BL ₀ and 7, respectively. (8) is enlarged on the interlayer oxide film 11, so that the cross-sectional area of the gate electrode 14 in the direction orthogonal to the channel region 5 is increased to suppress the resistance of the current flowing through the gate electrode 14; do.

Therefore, the delay of the signal can be suppressed to improve the operation speed and obtain a semiconductor memory device suitable for high speed.

In addition, since the capacitor is located above the bit lines BL ₀ and the conductive layers D ₀ and 8, and below the word lines WL ₁ 27, the degree of freedom of the region in which the capacitor is formed is wide. It can be formed by extending to the bit line (BL ₀ ) (7) via the gate electrode (14).

Therefore, a semiconductor memory device capable of ensuring sufficient capacity can be obtained in terms of increasing the capacitor area and miniaturization.

Again, the bit lines BL ₀ 7 are connected to the n ⁺ type drain region 3 and the conductive layer D ₀ 8 is connected to the n ⁺ type source region 4 without interposing contact holes therebetween. Therefore, the aspect ratio can be ignored.

Therefore, disconnection of the bit lines BL ₀ and 7 can be prevented and a highly reliable semiconductor memory device can be obtained.

In the above method of manufacturing a semiconductor memory device, the bit line BL ₀ 7 is formed by connecting the n ⁺ type drain region 3 without interposing a contact hole, and then a capacitor is formed. The process for forming a contact hole becomes unnecessary.

On the other hand, both ends of the gate electrode 14 in the parallel direction with the channel region 5 are formed on the interlayer oxide film 11 on the bit lines BL ₀ and 7 or on the conductive layer D ₀ and 8, respectively. It is formed to extend up to (11), and the interlayer oxide films 15 and 18 and the BPSG film 23 on the upper end of the gate electrode 14 are etched and the contact holes CH ₀ 26 are formed. Rain is suppressed low.

Therefore, the bit lines BL ₀ and 7 can be connected to the n ⁺ type drain region 3 and the word lines WL ₁ and 27 to the gate electrode 14 without performing a highly accurate photolithography process. The semiconductor memory device can be easily formed and manufactured.

In the above embodiment, the gate electrode 14 is formed from a polysilicon layer containing phosphorus (P), but the high melting point metal film, the high melting point metal silicide film, or the high melting point metal silicide film and the polysilicon layer are shown. Even if it is formed in a laminated structure, the same effects as in the above embodiment can be obtained.

In the above embodiment, after the titanium film is formed on the entire main surface of the p-type silicon semiconductor substrate 1 by the sputtering method, the bit lines BL ₀ (7), ( (9), ( 10 shows the formation of the titanium silicide film 16 by silicide reacting polysilicon and titanium forming the conductive layer (D ₀ ) and (8), but the bit lines BL ₀ (7) and ( (9), ( The titanium silicide film 16 was formed by silicide reacting polysilicon and titanium after forming a titanium film only on the surfaces of the (10) and the conductive layers (D ₀ ) (8) by selective CVD. The same effect will be obtained.

Again, in the above embodiment, the bit lines BL ₀ (7), ( (9), ( Although the titanium silicide film 16 is formed on the surfaces of the (10) and the conductive layers (D ₀ ) and (8), the above-described embodiment is performed even if a molybdenum silicide film, a tungsten silicide film, or a tantalum silicide film is formed. You will get the same effect.

Again, in the above embodiment, the memory cells C ₁ , 24, and C ₂ 25 are formed in the p-type silicon semiconductor substrate 1, but the polarities of the p-type and n-type are reversed. Even if the memory cell is formed on the n-type silicon semiconductor substrate 1, the same effect as in the above embodiment is obtained.

As described above, the present invention is connected to one of a set of impurity diffusion regions formed by connecting one channel of impurity diffusion regions provided on one surface of a semiconductor substrate with a channel region interposed therebetween, and connected to the other of the set of impurity diffusion regions. The gate electrode formed with the formed second conductive layer, the insulating film on the channel region, the insulating film on the first conductive layer and the insulating film on the second conductive layer interposed therebetween, so that the resistance of the gate electrode can be suppressed and the speed is increased. This has the effect of obtaining a field effect transistor suitable for.

As described above, the second aspect of the present invention is a gate electrode and a set of impurity diffusions formed with a set of impurity diffusion regions provided with a channel region interposed therebetween and an insulating film on the channel region interposed therebetween. The first conductive layer formed by connecting to one of the regions, the one electrode of the capacitor formed by being electrically connected to the first conductive layer, and the other of the capacitor formed with the dielectric film on the electrode therebetween. And a second conductive layer formed by electrically connecting the electrode with the gate electrode and having an insulating film on the other electrode of the capacitor interposed therebetween, so that the capacitor area can be increased and the capacitance can be miniaturized. This has the effect of obtaining a memory cell capable of ensuring a sufficient amount.

Again, in the third aspect of the present invention, as described above, an insulating film formed by separating element formation regions on a main surface of a semiconductor substrate, and a set of impurity diffusion regions provided with a channel region interposed therebetween, A first conductive layer formed on one side of the impurity diffusion region and contacting the other side of the set of impurity diffusion regions and on the other side of the impurity diffusion region. Since it is provided with the 2nd conductive layer formed on the insulating film, the disconnection of a bit line by the increase of aspect ratio can be prevented, and it has the effect of obtaining a highly reliable semiconductor memory device.

Again, according to the fourth aspect of the present invention, as described above, the first insulating film is formed by separating the element formation region on one main surface of the semiconductor substrate and contacting the region on and in part of the region in the element formation region. A second conductive layer is formed on the side of the first conductive layer on a portion of the region where the first conductive layer is opposed to the first conductive layer of the element formation region and on the first insulating layer that is in contact with the region. The second insulating film, the third insulating film on the side of the second conductive layer, the insulating film on the element formation region between the second insulating film and the third insulating film, the insulating film on the first conductive layer and the second conductive film Since the impurity diffusion region is formed by ion implanting impurity of semiconductor substrate and reverse conductivity using the gate electrode as a part of the mask with a layered insulating film interposed therebetween, a high precision photolithography process is started. One will have the effect that the access to the conductive layer and the second conductive layer of the first impurity diffusion region can be easily formed in the field effect transistor is for preparing the that without.

Claims (3)

A pair of second conductivity type impurity diffusion regions 3 and 4 formed on one circumferential surface of the first conductivity type semiconductor substrate 1 with the channel region 5 interposed therebetween, and formed by connecting to one of the impurity diffusion regions. A first conductive layer 8, a second conductive layer 7 formed by connecting to the other side of the impurity diffusion region, a first portion formed with an insulating film on the channel region, and the first portion A second portion extending from the first conductive layer so as to face the insulating film on the surface of the first conductive layer, and having an insulating film on the surface of the second conductive layer extending from the first portion. A field effect transistor having a gate electrode (14) having a third portion formed to face each other. An insulating film 2 formed by separating element formation regions on one circumferential surface of the first conductive semiconductor substrate 1, and a set of impurity diffusion regions of a second type of conductivity type formed with a channel region interposed therebetween. 4) a first portion formed by connecting to one of the impurity diffusion regions, and a second portion formed opposite to the insulating film extending from the first portion and in contact with one side of the impurity diffusion region; The conductive layer 7 of FIG. 1 constituting part of the bit line, the first portion formed by connecting to the other side of the impurity diffusion region, and the insulating film extending from the first portion and contacting the other side of the impurity diffusion region. And a second conductive layer (8) having a second portion formed opposite to and electrically connected to an electrode constituting the capacitor. Forming a first insulating film 2 by separating the element forming region on one circumferential surface of the first conductive semiconductor substrate, on a part of the region in the element forming region and on the first insulating layer in contact with the region Forming a first conductive layer (7), a second conductive layer (8) on a portion of the element formation region facing the first conductive layer, and on the first insulating film in contact with the region; ), Forming a second insulating film 12 on the side of the first conductive layer, forming a third insulating film 12 on the side of the second conductive layer, Forming a gate electrode 14 on the insulating film on the element formation region between the second insulating film and the third insulating film, on the insulating film on the first conductive layer and the insulating film on the second conductive layer, The second electrode as part of the mask as the gate electrode The method of ion implantation and the production of a field effect transistor having a step of forming an impurity diffusion region of a second conductivity type impurity.