JPH0455548B2 - - Google Patents
Info
- Publication number
- JPH0455548B2 JPH0455548B2 JP62067077A JP6707787A JPH0455548B2 JP H0455548 B2 JPH0455548 B2 JP H0455548B2 JP 62067077 A JP62067077 A JP 62067077A JP 6707787 A JP6707787 A JP 6707787A JP H0455548 B2 JPH0455548 B2 JP H0455548B2
- Authority
- JP
- Japan
- Prior art keywords
- etching resist
- hole
- substrate
- holes
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 description 29
- 238000004070 electrodeposition Methods 0.000 description 9
- 238000000576 coating method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
(a) 産業上の利用分野
この発明は、感光性のエツチングレジストを使
用して、非回路部の導体部をエツチングする工程
を含むスルーホール配線基板の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method for manufacturing a through-hole wiring board, which includes a step of etching conductor parts in non-circuit parts using a photosensitive etching resist.
(b) 従来の技術
スルーホール配線基板の従来の製造方法には、
穴埋め法や半田剥離法などがあるが、これらの方
法はスルーホール欠けを発生したり薬品コストが
高くなるなどの不都合がある。そこで最近、感光
性のエツチングレジストを電着塗装方式によつて
スルーホールを含む回路部に形成し、上記の方法
の欠点を解消し且つ高密度な配線パターンを形成
する方法が提案されている。この電着塗装方式で
は、スルーホールの内面に感光性のエツチングレ
ジストが確実に付着し、しかもそのレジスト被膜
の膜厚も容易にコントロールすることができるた
めに、解像度を40ミクロン以下のフアインパター
ン、たとえばICのピン間に20〜30本の配線ライ
ンを形成することが可能となる。この方式ではス
ルーホールを含む回路部に感光性のエツチングレ
ジストを露出させた状態で基板全面を露光し、上
記回路部に載せてあるエツチングレジストを光硬
化させる。その後不要な被膜を除去してエツチン
グを行うことにより非回路部の導体部(銅等)を
取り除くことになる。(b) Conventional technology The conventional manufacturing method for through-hole wiring boards includes:
There are hole-filling methods and solder stripping methods, but these methods have disadvantages such as through-hole chipping and increased chemical costs. Recently, a method has been proposed in which a photosensitive etching resist is formed on a circuit portion including through holes by an electrodeposition coating method, thereby eliminating the drawbacks of the above method and forming a high-density wiring pattern. With this electrodeposition coating method, the photosensitive etching resist reliably adheres to the inner surface of the through hole, and the thickness of the resist film can also be easily controlled. For example, it becomes possible to form 20 to 30 wiring lines between the pins of an IC. In this method, the entire surface of the substrate is exposed to light with a photosensitive etching resist exposed on circuit parts including through holes, and the etching resist placed on the circuit parts is photocured. Thereafter, unnecessary coatings are removed and etching is performed to remove non-circuit conductor parts (copper, etc.).
(c) 発明が解決しようとする問題点
しかしながら感光性エツチングレジストを使用
する上記の従来の方法では、基板全面を露光する
ときに、スルーホール内壁に十分な光が照射され
ない場合がある。第5図はこの様子を示してい
る。基板1の全面およびスルーホール内壁には銅
等の材料からなる導体部2が形成され、さらにス
ルーホール内壁を含む回路部に感光性のエツチン
グレジスト3が電着塗装方式によつて形成された
のち、紫外線ランプ5によつて基板全面が露光さ
れる。このとき基板1表面の回路部は紫外線5a
の十分な照射を受けるが、スルーホール4の内壁
は十分に照射されない。このためスルーホール内
壁のエツチングレジスト3が十分に硬化されず、
基板洗浄時にその未硬化状態のエツチングレジス
トがスルーホール内壁から剥離してしまう可能性
があつた。(c) Problems to be Solved by the Invention However, in the above conventional method using a photosensitive etching resist, when the entire surface of the substrate is exposed, the inner wall of the through hole may not be irradiated with sufficient light. FIG. 5 shows this situation. A conductor portion 2 made of a material such as copper is formed on the entire surface of the substrate 1 and the inner wall of the through hole, and a photosensitive etching resist 3 is further formed on the circuit portion including the inner wall of the through hole by an electrodeposition coating method. , the entire surface of the substrate is exposed to light by the ultraviolet lamp 5. At this time, the circuit section on the surface of the board 1 is exposed to ultraviolet light 5a.
However, the inner wall of the through hole 4 is not sufficiently irradiated. For this reason, the etching resist 3 on the inner wall of the through hole is not sufficiently hardened.
When cleaning the substrate, there was a possibility that the uncured etching resist would peel off from the inner wall of the through hole.
この発明の目的は、露光時においてスルーホー
ル内壁に対しても十分な露光が行われ、スルーホ
ール部の信頼性を高くすることのできるスルーホ
ール配線基板の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a through-hole wiring board in which the inner walls of the through-holes are sufficiently exposed during exposure and the reliability of the through-hole portions can be increased.
(d) 問題点を解決するための手段
この発明は、スルーホールを含む基板全面に導
体部を形成したのち、スルーホールを含む回路部
にのみ感光性エツチングレジストを露出させ、つ
いで基板の一方の面の側に乱反射板をおき他方の
面の側を全面露光する工程を基板上下両面各々に
おいて行い、光硬化したエツチングレジスト以外
の領域の導体部をエツチングで取り除いて回路パ
ターンを形成することを特徴とする。(d) Means for solving the problem In this invention, after forming a conductor part on the entire surface of a board including through holes, a photosensitive etching resist is exposed only in the circuit part including through holes, and then a photosensitive etching resist is etched on one side of the board. A process of placing a diffused reflection plate on one side and fully exposing the other side to light is performed on both the upper and lower surfaces of the substrate, and the conductor portions in areas other than the photo-cured etching resist are removed by etching to form a circuit pattern. shall be.
(e) 作用 この発明の作用を第1図を参照して説明する。(e) Effect The operation of this invention will be explained with reference to FIG.
第1図はこの発明の露光工程を示している。こ
の露光工程では、第5図に示す従来の露光工程は
比較して、紫外線ランプ5の配置位置の反対側の
基板面に乱反射板6を配置している点が異なる。
紫外線ランプ5から基板1に対して照射された紫
外線5aは、スルーホール4を通過するとき第5
図に示す従来と同様にスルーホール内壁を十分に
照射しない。しかし乱反射面6aで乱反射してス
ルーホール内壁に到達する。したがつて図示する
ようにスルーホール内壁は乱反射光の十分な照射
を受け、その照射量は実質的に基板1表面の回路
部に対する照射量とほとんど同一となる。この後
の工程は従来の製造方法と全く同一である。すな
わちスルーホールを含む回路部以外の導体部をエ
ツチングで取除いて回路パターンを形成し、さら
に回路部を覆つているエツチングレジスト3を除
去する。 FIG. 1 shows the exposure process of this invention. This exposure process differs from the conventional exposure process shown in FIG. 5 in that a diffused reflection plate 6 is disposed on the substrate surface opposite to the position where the ultraviolet lamp 5 is disposed.
When the ultraviolet light 5a irradiated from the ultraviolet lamp 5 to the substrate 1 passes through the through hole 4, the ultraviolet light 5a
As in the conventional case shown in the figure, the inner wall of the through hole is not sufficiently irradiated. However, it is diffusely reflected by the diffused reflection surface 6a and reaches the inner wall of the through hole. Therefore, as shown in the figure, the inner wall of the through hole is sufficiently irradiated with the diffusely reflected light, and the amount of irradiation is substantially the same as the amount of irradiation to the circuit portion on the surface of the substrate 1. The subsequent steps are exactly the same as the conventional manufacturing method. That is, the conductor portions other than the circuit portion including through holes are removed by etching to form a circuit pattern, and furthermore, the etching resist 3 covering the circuit portion is removed.
(f) 実施例
第2図はこの発明に係るスルーホール配線基板
の製造方法を工程順に示している。以下各工程の
説明を行う。(f) Embodiment FIG. 2 shows a method for manufacturing a through-hole wiring board according to the present invention in the order of steps. Each step will be explained below.
A …ガラスエポキシ、紙エポキシ、紙フエノー
ルなどの素材を用意して基板1を形成する。A...Materials such as glass epoxy, paper epoxy, paper phenol, etc. are prepared to form the substrate 1.
B …基板1の所定の個所に穴明け加工を行う。B...Drill holes at predetermined locations on the board 1.
C …穴部の内壁および基板1の表裏面全体に公
知の化学メツキを行いメツキ膜7を施す。C: The inner wall of the hole and the entire front and back surfaces of the substrate 1 are subjected to known chemical plating to form a plating film 7.
D …さらに上記化学メツキによつて析出したメ
ツキ膜上に電気メツキ層8を形成する。D...Furthermore, an electroplated layer 8 is formed on the plating film deposited by the above chemical plating.
E …さらに上記電気メツキ層8上に回路部以外
となる領域を適当な絶縁膜9で覆う。この絶縁
膜9はスクリーン印刷法などによつて形成され
る。E...Furthermore, the area other than the circuit portion on the electroplated layer 8 is covered with a suitable insulating film 9. This insulating film 9 is formed by a screen printing method or the like.
F …続いて上記の基板を電着液内に浸漬し、電
気メツキ層8を一方の電極にして電着塗装を行
う。電着液には公知のものを使用することがで
きるが、本発明においては紫外線照射によつて
硬化する感光剤の混在したものを使用する。こ
の工程によつてスルーホールを含む回路部に感
光性エツチングレジスト10が形成される。F...Subsequently, the above substrate is immersed in an electrodeposition liquid, and electrodeposition is performed using the electroplating layer 8 as one electrode. Although any known electrodeposition solution can be used, in the present invention, one containing a photosensitizer that is hardened by ultraviolet irradiation is used. Through this step, a photosensitive etching resist 10 is formed in the circuit portion including the through holes.
G …次に乱反射板6の上に上記の基板を置き、
上方に紫外線ランプ5を配置して紫外線5aを
照射する。これによつて基板表面の感光性エツ
チングレジスト10が硬化するとともにスルー
ホールを透過した紫外線5aは乱反射板6aの
乱反射面6aで乱反射し、スルーホール4の内
壁を一様に照射して硬化させる。G...Next, place the above board on the diffuse reflection plate 6,
An ultraviolet lamp 5 is placed above and irradiates ultraviolet rays 5a. As a result, the photosensitive etching resist 10 on the surface of the substrate is cured, and the ultraviolet rays 5a transmitted through the through-holes are diffusely reflected by the diffusely reflecting surface 6a of the diffusely reflecting plate 6a, and the inner walls of the through-holes 4 are uniformly irradiated and hardened.
H …乱反射板6を基板の上面に置き且つ紫外線
ランプ5を基板1の下側において基板裏面に対
して紫外線5aを照射する。これによつて基板
裏面の感光性エツチングレジスト10が硬化す
るとともにスルーホール4を透過した紫外線は
乱反射板6の乱反射面6aで乱反射しスルーホ
ールの内壁を照射する。上記Gの工程でスルー
ホール内壁のエツチングレジスト10は硬化状
態にあるが、このHの工程でスルーホール内の
エツチングレジスト10の硬化状態がさらに完
全なものとなる。H...The diffused reflection plate 6 is placed on the top surface of the substrate, and the ultraviolet lamp 5 is placed below the substrate 1 to irradiate the back surface of the substrate with ultraviolet rays 5a. As a result, the photosensitive etching resist 10 on the back surface of the substrate is cured, and the ultraviolet rays transmitted through the through holes 4 are diffusely reflected by the diffuse reflection surface 6a of the diffuse reflection plate 6 and irradiate the inner walls of the through holes. In step G, the etching resist 10 on the inner wall of the through hole is in a hardened state, but in step H, the etching resist 10 inside the through hole is further completely hardened.
I …乱反射板6および紫外線ランプ5を取り払
い、弱アルカリ液で絶縁膜9を除去するととも
に、エツチング工程で非回路部の導体部8を取
り除く。I...Remove the diffused reflection plate 6 and the ultraviolet lamp 5, remove the insulating film 9 with a weak alkaline solution, and remove the conductor part 8 in the non-circuit part by an etching process.
J …さらに回路部のエツチングレジスト10を
除去して回路パターンの形成を完了し、図示し
ないソルダーレジストなどの処理を行つて基板
の製造を完了する。J...Furthermore, the etching resist 10 of the circuit portion is removed to complete the formation of the circuit pattern, and processing such as solder resist (not shown) is performed to complete the manufacture of the board.
以上の製造方向の内、Fの工程で電着塗装方式
で感光性エツチングレジスト10を形成している
ために、スルーホールを含むすべての回路表面に
膜厚の均一なレジスト膜を確実に形成することが
できる。上記GおよびHの工程で乱反射板6を使
用して露光を行うようにしているためにスルーホ
ール内壁のエツチングレジスト膜に対して十分な
紫外線の照射を行うことができる。 Among the above manufacturing directions, since the photosensitive etching resist 10 is formed by the electrodeposition coating method in step F, a resist film with a uniform thickness is reliably formed on all circuit surfaces including through holes. be able to. Since the diffused reflection plate 6 is used for exposure in the steps G and H, the etching resist film on the inner wall of the through hole can be irradiated with sufficient ultraviolet rays.
第3図は写真法を利用した本発明の製造方法の
一部を示す。上記の第2図に示す製造方法では、
Eの工程において印刷によつて絶縁膜9を形成し
て、Fの工程で回路部にのみエツチングレジスト
10を形成するようにしているが、第3図に示す
製造方法では上記Eの工程に代えて基板全面に対
してエツチングレジスト10を形成する(E′)。
そして上記F工程に代えて、非回路部を覆うネガ
フイルム19を基板上に置いて上記G以下の工程
へと移る。このような方法によつても上記第2図
に示す方法と同様に均一な膜厚のエツチングレジ
ストを確実に形成することができるとともに、ス
ルーホール内壁のエツチングレジストを確実に硬
化させることができる。 FIG. 3 shows a part of the manufacturing method of the present invention using a photographic method. In the manufacturing method shown in FIG. 2 above,
In the step E, the insulating film 9 is formed by printing, and in the step F, the etching resist 10 is formed only on the circuit area, but in the manufacturing method shown in FIG. 3, the above step E is replaced. Then, an etching resist 10 is formed over the entire surface of the substrate (E').
Then, in place of the step F, a negative film 19 covering the non-circuit portion is placed on the substrate, and the process proceeds to the steps G and subsequent steps. With this method as well, it is possible to reliably form an etching resist having a uniform thickness, as in the method shown in FIG. 2, and it is also possible to reliably harden the etching resist on the inner wall of the through hole.
第4図は本発明に係る製造方法の応用例を示し
ている。第1の基板1と第2の基板1′とで図示
するように乱反射板6を挟み、上下両方から紫外
線を基板に対して照射する。乱反射板6の上下両
面はともに乱反射面で構成されている。第2図の
GおよびHの工程で、このように二つの基板を乱
反射板6を介してサンドイツチ構造で上下両方か
ら露光を行うことによつて一回の露光工程で二つ
の基板の同時処理が可能となる。したがつてこの
工程を終えたのち二つの基板1,1′をそれぞれ
上下入れ換えて再び露光を行えば、二回の露光工
程で二枚の基板の露光処理を終了する。すなわち
実質的に一回の露光工程で一枚の基板に対する露
光が終了したものとみなせ、効率を良くすること
ができる。 FIG. 4 shows an example of application of the manufacturing method according to the present invention. A diffuse reflection plate 6 is sandwiched between the first substrate 1 and the second substrate 1' as shown in the figure, and the substrates are irradiated with ultraviolet rays from both above and below. Both the upper and lower surfaces of the diffused reflection plate 6 are constituted by diffused reflection surfaces. In the steps G and H in FIG. 2, by exposing the two substrates from both the top and bottom through the diffuse reflection plate 6 in a sandwich structure, the two substrates can be processed simultaneously in one exposure process. It becomes possible. Therefore, after completing this process, if the two substrates 1 and 1' are reversed upside down and exposed again, the exposure process for the two substrates will be completed in two exposure steps. In other words, it can be considered that the exposure of one substrate is substantially completed in one exposure process, and the efficiency can be improved.
なお以上の実施例では、電着塗装方式によつて
スルーホールを含む回路部に感光性のエツチング
レジストを形成するようにしたが、本発明ではス
ルーホールを含む回路部に感光性エツチングレジ
ストを露出した状態で形成すればよいのであつ
て、このエツチングレジストを形成するのに電着
塗装方式を必ず使用しなければならないというも
のではない。他の方法で上記エツチングレジスト
を形成することも勿論可能である。 In the above embodiments, the photosensitive etching resist was formed on the circuit portion including the through holes using an electrodeposition coating method, but in the present invention, the photosensitive etching resist was formed on the circuit portion including the through holes. It is not necessary to necessarily use an electrodeposition coating method to form this etching resist. Of course, it is also possible to form the etching resist using other methods.
(g) 発明の効果
以上のようにこの発明によれば、スルーホール
を含む回路部に露出形成された感光性のエツチン
グレジストに対して露光を行う時に、基板の一方
の面の側に乱反射板を置いて露光するようにして
いるために、光は乱反射板で乱反射してスルーホ
ール内の感光性エツチングレジストに到達するた
めにそのレジストが十分に光の照射を受けること
ができる。このため感光が十分でないことによる
スルーホール内壁のレジストの剥離などを簡単に
防止することができる、スルーホールの信頼性を
確実に向上できる利点がある。(g) Effects of the Invention As described above, according to the present invention, when exposing a photosensitive etching resist formed exposed on a circuit portion including through holes, a diffused reflection plate is placed on one side of the substrate. Since the light is diffusely reflected by the diffused reflection plate and reaches the photosensitive etching resist in the through hole, the resist can be sufficiently irradiated with light. Therefore, it is possible to easily prevent peeling of the resist on the inner wall of the through hole due to insufficient exposure to light, and there is an advantage that the reliability of the through hole can be reliably improved.
第1図は本発明の製造方法を説明するための図
である。第2図は本発明に係る製造方法を工程順
に説明する図、第3図はその変形例を示す図、第
4図は本発明の製造方法をさらに効率的に行うた
めの方法を説明するための図である。第5図は従
来の製造方法を説明するための図である。
1……基板、2……導体部、3……エツチング
レジスト、4……スルーホール、6……乱反射
板。
FIG. 1 is a diagram for explaining the manufacturing method of the present invention. Fig. 2 is a diagram for explaining the manufacturing method according to the present invention step by step, Fig. 3 is a diagram showing a modification thereof, and Fig. 4 is a diagram for explaining a method for performing the manufacturing method of the present invention more efficiently. This is a diagram. FIG. 5 is a diagram for explaining a conventional manufacturing method. 1...Substrate, 2...Conductor portion, 3...Etching resist, 4...Through hole, 6...Diffuse reflection plate.
Claims (1)
したのち、スルーホールを含む回路部にのみ感光
性エツチングレジストを露出させ、ついで基板の
一方の面の側に乱反射板を置き、他方の面の側を
全面露光する工程を基板上下両面各々において行
い、光硬化したエツチングレジスト領域以外の領
域の導体部をエツチングで取り除いて回路パター
ンを形成することを特徴とするスルーホール配線
基板の製造方法。1 After forming a conductor part on the entire surface of the board including through holes, expose the photosensitive etching resist only on the circuit part including through holes, then place a diffused reflection plate on one side of the board, and A method for manufacturing a through-hole wiring board, characterized in that a step of exposing the entire surface of the board to light is carried out on both the upper and lower surfaces of the board, and conductor parts in areas other than the photo-cured etching resist area are removed by etching to form a circuit pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62067077A JPS63232390A (en) | 1987-03-19 | 1987-03-19 | Manufacture of through-hole wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62067077A JPS63232390A (en) | 1987-03-19 | 1987-03-19 | Manufacture of through-hole wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63232390A JPS63232390A (en) | 1988-09-28 |
JPH0455548B2 true JPH0455548B2 (en) | 1992-09-03 |
Family
ID=13334443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62067077A Granted JPS63232390A (en) | 1987-03-19 | 1987-03-19 | Manufacture of through-hole wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63232390A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0335587A (en) * | 1989-06-30 | 1991-02-15 | Ibiden Co Ltd | Manufacture of printed wiring board |
-
1987
- 1987-03-19 JP JP62067077A patent/JPS63232390A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS63232390A (en) | 1988-09-28 |
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R250 | Receipt of annual fees |
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LAPS | Cancellation because of no payment of annual fees |