CN107666771A - Circuit board structure - Google Patents

Abstract

The invention provides a circuit board structure, which comprises a substrate, a plurality of metallizable photosensitive and developable substrates, an electroless plating seed layer and a second patterned circuit layer. The substrate includes an upper surface, a lower surface opposite to the upper surface, and a first patterned circuit layer. The metallizable photosensitive and developable base material is respectively arranged on the upper surface and the lower surface. Each metallizable photosensitive and developable substrate includes a plurality of blind holes, which respectively expose at least part of the first patterned circuit layer, and the material of each metallizable photosensitive and developable substrate includes a photosensitive material. The electroless plating seed layer is arranged on the metallizable photosensitive and developable base material and covers the inner wall of each blind hole. The second patterned circuit layer is respectively disposed on the first electroless plating seed layer and filled in the blind hole so as to be electrically connected with the first patterned circuit layer. The invention effectively simplifies the process steps of the circuit board structure and improves the process efficiency.

Description

circuit board structure

technical field

The invention relates to a circuit board structure, in particular to a circuit board structure with a metallizable photosensitive and developable base material.

Background technique

In the current semiconductor packaging manufacturing process, the circuit board has become one of the frequently used structural components due to the advantages of fine wiring, compact assembly and good performance. The circuit board can be assembled with a plurality of electronic components, such as chips and passive components. Through the circuit board, these electronic components are electrically connected to each other, and signals can be transmitted between these electronic components.

Generally speaking, a circuit board is mainly composed of multiple patterned circuit layers and multiple insulating layers laminated alternately, and the patterned circuit layers are electrically connected to each other through conductive vias. The traditional method of forming a conductive blind hole is usually to form a blind hole through the insulating layer by means of laser drilling, and make the blind hole expose the underlying circuit layer. After that, a desmear process is performed to remove the smear generated by the laser drilling. Then, a conductive layer is formed in the blind hole to electrically connect the circuit layer below.

It is worth noting that during the above-mentioned laser drilling process, the smear that has not been completely removed by the laser will remain on the hole wall of the blind hole, so it is still necessary to remove the smear with an alkaline chemical solution. Therefore, currently The blind hole process steps are still quite complicated. Moreover, in the process of desmearing, the copper layer under the blind hole is easy to peel off in the alkaline chemical solution, thus affecting the yield of the process.

Contents of the invention

The invention provides a circuit board structure with high process efficiency and process yield.

The circuit board structure of the present invention includes a substrate, a plurality of first metallizable photosensitive and developable substrates, a first electroless plating seed layer, a second patterned circuit layer, a second metallizable photosensitive and developable substrate, and a second electroless plating seed layer and the third patterned circuit layer. The substrate includes an upper surface, a lower surface opposite to the upper surface, and a first patterned circuit layer. The first metallizable photosensitive and developable substrate is respectively arranged on the upper surface and the lower surface. Each first metallizable photosensitive and developable substrate includes a plurality of first blind holes, which respectively expose at least part of the first patterned circuit layer, and the material of each first metallizable photosensitive and developable substrate includes a photosensitive material. The first electroless plating seed layer is disposed on the first metallizable photosensitive and developable substrate and covers the inner wall of each first blind hole. The second patterned circuit layer is respectively disposed on the first electroless plating seed layer and filled in the first blind hole so as to be electrically connected with the first patterned circuit layer. A second metallizable photo-developable substrate is disposed on one of the first metallizable photo-developable substrates, the second metallizable photo-developable substrate includes a plurality of second blind holes exposing at least part of the The second patterned circuit layer, and the material of the second metallizable photosensitive developable substrate includes a photosensitive material. The second electroless plating seed layer is disposed on the second metallizable photosensitive and developable substrate and covers the inner wall of the second blind hole. The third patterned circuit layer is disposed on the second electroless plating seed layer and filled in the second blind hole so as to be electrically connected with the second patterned circuit layer.

In an embodiment of the present invention, the above-mentioned substrate further includes an insulating base material, and the first patterned circuit layer is disposed on the insulating base material.

In an embodiment of the present invention, the above-mentioned substrate further includes a through hole penetrating through the insulating substrate, and the first patterned circuit layer covers the inner wall of the through hole.

In an embodiment of the present invention, the above-mentioned substrate further includes a filling material filled in the through hole.

In an embodiment of the present invention, the materials of the first metallizable photosensitive and developable substrate and the second metallizable photosensitive and developable substrate include polyimide (PI).

In an embodiment of the present invention, the above-mentioned first electroless plating seed layer and the second electroless plating seed layer are made of nickel.

In an embodiment of the present invention, the material of the second patterned circuit layer and the third patterned circuit layer includes copper.

In an embodiment of the present invention, the above-mentioned step of providing the substrate further includes the following step: providing an insulating base material. A through hole is formed on the insulating base material, wherein the through hole penetrates through the insulating base material. A first patterned circuit layer is formed on the insulating substrate, and the first patterned circuit layer covers the inner wall of the through hole.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit board structure further includes the following step: disposing a filling material in the through hole to fill the through hole.

In an embodiment of the present invention, the step of forming the blind hole includes: forming a patterned dry film layer on a plurality of removal regions of the metallizable photosensitive and developable substrate, wherein the positions of the removal regions correspond to the blind holes respectively . An exposure process is performed to expose a portion of the metallizable photodevelopable substrate not covered by each patterned dry film layer. A development process is performed to remove the unexposed removal area to form the blind hole. Remove the patterned dry film layer.

In an embodiment of the present invention, the step of forming a blind hole includes: forming a patterned dry film layer on a metallizable photosensitive developable substrate, wherein the patterned dry film layer exposes a plurality of removal regions, and the removal The positions of the removal areas correspond to the blind holes respectively. An exposure process is performed to expose the exposed removal area. A development process is performed to remove the exposed removal area to form a blind hole. Remove the patterned dry film layer.

In an embodiment of the present invention, the step of forming the second patterned circuit layer includes: forming a metal layer on the electroless plating seed layer. A patterned dry film layer is formed on the metal layer, and the patterned dry film layer covers at least part of the metal layer filled in the blind holes. An etching process is performed to remove a part of the metal layer not covered by the patterned dry film layer to form a second patterned circuit layer. Remove the patterned dry film layer.

In an embodiment of the present invention, the step of forming the second patterned circuit layer includes: forming a patterned dry film layer on the electroless plating seed layer, and the patterned dry film layer at least exposes the blind holes. An electroplating process is performed using the patterned dry film layer as a mask to form a second patterned circuit layer. The patterned dry film layer is removed to expose a portion of the underlying electroless seed layer. An etching process is performed to remove the exposed part of the electroless plating seed layer.

Based on the above, the present invention utilizes the photosensitive properties of the metallizable photosensitive and developable substrate to perform an exposure and development process to form a plurality of blind holes on the metallizable photosensitive and developable substrate. Moreover, the present invention forms an electroless plating seed layer on the surface of the metallizable photosensitive development substrate through an electroless plating process, so that the subsequent electroplating process using the electroless plating seed layer as a conductive path forms a patterned circuit layer, and the patterned circuit layer Filling in the blind holes to electrically connect the patterned lines between the stacked structures through the blind holes. Therefore, the present invention effectively simplifies the process steps of the circuit board structure and improves the efficiency of the manufacturing process. In addition, the present invention can also avoid the problem that glue slag generated by laser drilling remains in the blind hole in the existing blind hole process, thereby improving the yield rate of the circuit board structure process.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1I are schematic cross-sectional flow diagrams of a method for manufacturing a circuit board structure according to an embodiment of the present invention;

2 is a schematic cross-sectional view of part of the process of a method for manufacturing a circuit board structure according to another embodiment of the present invention;

3A to 3C are schematic cross-sectional views of part of the process of a method for fabricating a circuit board structure according to another embodiment of the present invention.

Explanation of reference numbers:

100: circuit board structure;

110: substrate;

111: insulating substrate;

112: upper surface;

114: lower surface;

116: the first patterned circuit layer;

118: through hole;

119: filling material;

120: the first metallizable photosensitive and developable substrate;

122: the first blind hole;

125: the second metallizable photosensitive developable substrate;

126: the second blind hole;

130: the first electroless plating seed layer;

135: the second electroless plating seed layer;

140: metal layer;

142: the second patterned circuit layer;

145: a third patterned circuit layer;

150, 160, 170, 180: patterned dry film layer;

R1: Removal zone.

Detailed ways

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed descriptions of the embodiments with accompanying drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Accordingly, the directional terms used are illustrative, not limiting, of the invention. Also, in the following embodiments, the same or similar components will use the same or similar symbols.

1A to 1I are schematic cross-sectional flow diagrams of a manufacturing method of a circuit board structure according to an embodiment of the present invention. The manufacturing method of the circuit board structure in this embodiment includes the following steps. First, a substrate 110 as shown in FIG. 1A is provided, wherein the substrate 110 includes an upper surface 112 , a lower surface 114 opposite to the upper surface 112 , and a first patterned circuit layer 116 . In detail, the method for forming the above-mentioned substrate 110 may, for example, firstly provide the insulating base material 111 . Next, a through hole 118 is formed on the insulating base material 111 , wherein the through hole 118 penetrates through the insulating base material 111 . Then form the first patterned circuit layer 116 on the insulating substrate 111, and the first patterned circuit layer 116 covers the inner wall of the through hole 118, and arrange the filling material 119 in the through hole 118 to fill the through hole 118, that is A substrate 110 as shown in FIG. 1A may be formed. Certainly, this embodiment is only used for illustration, and the present invention does not limit the method of forming the substrate 110 and the form of the substrate 110 .

Next, referring to FIG. 1B , a first metallizable photosensitive and developable substrate 120 is disposed on the upper surface 112 and the lower surface 114 of the substrate 110, wherein the material of the first metallizable photosensitive and developable substrate 120 includes a photosensitive material and Polyimide (polyimide, PI). In this embodiment, the first metallizable photosensitive and developable substrate 120 can be a positive photoresist or a negative photoresist, so as to directly perform an exposure and development process on the first metallizable photosensitive and developable substrate 120 subsequently. If the first metallizable photosensitive and developable substrate 120 is a negative photoresist, the first metallizable photosensitive and developable substrate 120 will be cured after exposure and cannot be dissolved in the developing solution. On the contrary, if the first metallizable photosensitive and developable substrate 120 The developing substrate 120 is a positive photoresist, and the first metallizable photosensitive developing substrate 120 will be cracked after being exposed and is easily soluble in the developing solution. Moreover, the first metallizable photosensitive and developable substrate 120 may be, for example, a substrate that has undergone a special activation and sensitization treatment, so as to directly perform an electroless plating process thereon.

Next, referring to FIG. 1C and FIG. 1D , an exposure and development process is performed on the first metallizable photosensitive and developable substrate 120 to form a plurality of first metallizable photosensitive and developable substrates 120 as shown in FIG. 1D . A blind hole 122 , and the first blind hole 122 exposes part of the first patterned circuit layer 116 . In this embodiment, the first blind hole 122 can be a via hole for electrically connecting any two adjacent patterned circuit layers in the circuit board structure. It should be noted here that, in the embodiment shown in FIG. 1C , the first metallizable photosensitive and developable substrate 120 is a negative photoresist, that is, after the first metallizable photosensitive and developable substrate 120 is exposed It will solidify and become insoluble in the developer. In this way, the aforementioned exposure and development process may include the following steps: First, each patterned dry film layer 150 is formed on the first metallizable photosensitive and developable substrate 120 as shown in FIG. 1C , wherein each patterned dry film layer 150 A plurality of removal regions covering the first metallizable photodevelopable substrate 120 . In this embodiment, the positions of the removal regions respectively correspond to the first blind holes 122 as shown in FIG. 1D . After that, an exposure process is performed to expose the part of the first metallizable photosensitive and developable substrate 120 not covered by the patterned dry film layer 150 . That is to say, the region of the first metallizable photosensitive and developable substrate 120 except the removed region will undergo qualitative change due to the irradiation of ultraviolet light, so that the regions of the first metallizable photosensitive and developable substrate 120 except the removed region Areas solidify and become insoluble in developer solutions. After that, the developing process is carried out again. Since the removed area is covered by the patterned dry film layer 150 and is not irradiated by ultraviolet light, the removed area corresponding to the first blind hole 122 will be dissolved in the developing solution of the developing process, so it can be The unexposed removal area covered by the patterned dry film layer 150 is removed to form a plurality of first blind holes 122 as shown in FIG. 1D , and then the patterned dry film layer 160 is removed.

Of course, in other embodiments, the first metallizable photosensitive and developable substrate 120 can also be a positive photoresist, that is, the first metallizable photosensitive and developable substrate 120 will be cracked after being exposed and become easily soluble in in the developer solution. In this case, the formation method of the first blind hole 122 can refer to the formation of the patterned dry film layer 160 on the first metallizable photosensitive and developable substrate 120 shown in FIG. As shown in FIG. 2 , a plurality of removal regions R1 of the first metallizable photosensitive and developable substrate 120 are exposed. Afterwards, an exposure process such as ultraviolet light is performed to expose the removed region R1 of the first metallizable photosensitive and developable substrate 120 . That is to say, the removal region R1 of the first metallizable photosensitive and developable substrate 120 will be irradiated by ultraviolet light and undergo a qualitative change, so that the removal region R1 of the first metallizable photosensitive and developable substrate 120 will be cracked and become Easily soluble in developer solution. Afterwards, the developing process is carried out again. Since the removed region R1 undergoes a qualitative change due to the irradiation of ultraviolet light, the removed region R1 will dissolve in the developing solution in the developing process, so that the exposed patterned dry film layer 160 can be removed. The exposed removal region R1 is used to form a plurality of first blind holes 122 as shown in FIG. 1D . After that, the patterned dry film layer 160 can be removed. The present invention does not limit the type of photoresist of the first metallizable photosensitive and developable substrate 120 , as long as it has a photosensitive property and can be directly patterned through an exposure and development process.

Next, referring to FIG. 1E , an electroless plating process is performed to form a first electroless plating seed layer 130 on the first metallizable photosensitive and developable substrate 120, and the first electroless plating seed layer 130 covers each of the first blind holes 122. inner wall. Specifically, the first electroless plating seed layer 130 completely covers the surface of the first metallizable photosensitive and developable substrate 120 , and extends into each of the first blind holes 122 .

Based on the above, the electroless plating process utilizes chemical oxidation-reduction reactions to deposit a coating on the surface of the first metallizable photosensitive and developable substrate 120 . In this embodiment, the material of the first electroless plating seed layer 130 includes nickel, that is to say, the first electroless plating seed layer 130 in this embodiment may be an electroless nickel plating layer. Specifically, electroless nickel plating uses a reducing agent to reduce and deposit nickel ions in solution on a catalytically active surface. For example, in this embodiment, the first metallizable photosensitive and developable substrate 120 of this embodiment can be formed by subjecting the photosensitive and developable substrate to a special activation and sensitization treatment. In this way, the electroless plating process step may include immersing the first metallizable photosensitive and developable substrate 120 in a mixed solution such as nickel sulfate, sodium dihydrogen hypophosphite, sodium acetate and boric acid, etc. The temperature changes, allowing the nickel ions in the solution to be reduced to atoms by sodium dihydrogen hypophosphite and deposited on the surface of the first metallizable photosensitive development substrate 120 to form the first chemical plating seed layer as shown in Figure 1E 130.

Next, a second patterned circuit layer 142 as shown in FIG. 1H is formed, wherein the second patterned circuit layer 142 is disposed on the first electroless plating seed layer 130 and filled in the first blind hole 122 so as to communicate with the bottom The first patterned circuit layer 116 is electrically connected. In this embodiment, the material of the second patterned circuit layer 142 includes copper. In this embodiment, the second patterned circuit layer 142 may be formed, for example, by a subtractive method. Specifically, the step of forming the second patterned circuit layer 142 can be, for example, firstly use the first electroless plating seed layer 130 as a conductive path to perform an electroplating process to form the metal layer 140 as shown in FIG. 1F on the first electroless plating seed layer 130. Layer 130. Next, a patterned dry film layer 170 as shown in FIG. 1G is formed on the metal layer 140 , and the patterned dry film layer 170 covers at least part of the metal layer 140 filled in the first blind hole 122 . Next, an etching process is performed to remove a portion of the metal layer 140 not covered by the patterned dry film layer 170 to form a second patterned circuit layer 142 as shown in FIG. 1H , and then the patterned dry film layer is removed. 170, the fabrication of the second patterned circuit layer 142 can be completed.

Certainly, in other embodiments of the present invention, the second patterned circuit layer 142 may also be formed by a semi-additive method. Specifically, the step of forming the second patterned wiring layer 142 may be formed after forming the first electroless plating seed layer 130 as shown in FIG. 1E , followed by the process shown in FIGS. 3A to 3C . First, a patterned dry film layer 180 as shown in FIG. 3A is formed on the first electroless plating seed layer 130 , and the patterned dry film layer 180 at least exposes the first blind holes 122 . Next, referring to FIG. 3B again, the electroplating process is performed using the patterned dry film layer 180 as a mask to form the second pattern circuit layer 142 on the exposed portion of the patterned dry film layer 180 . Next, as shown in FIG. 3C , the patterned dry film layer 180 is removed to expose a portion of the first electroless plating seed layer 130 below. An etching process is then performed to remove the exposed part of the first electroless plating seed layer 130 to form the structure shown in FIG. 1H .

Please continue to refer to FIG. 1I , and then a second metallizable photosensitive and developable substrate 125 may be disposed on one of the first metallizable photosensitive and developable substrates 120 . In this embodiment, the second metallizable photosensitive-developable substrate 125 can be disposed on the lower first metallizable photosensitive-developable substrate 120. Of course, this embodiment is only for illustration. In other embodiments, The second metallizable photosensitive-developable substrate 125 can also be disposed on the upper first metallizable photosensitive-developable substrate 120 , and the present invention does not limit the arrangement of the second metallizable photosensitive-developable substrate 125 . In this embodiment, the material of the second metallizable photosensitive and developable substrate 125 includes a photosensitive material, in other words, the second metallizable photosensitive and developable substrate 125 may have light sensitivity. In this embodiment, the material of the second metallizable photosensitive and developable substrate 125 can be the same as that of the first metallizable photosensitive and developable substrate 120 , and the material can also include polyimide. In this embodiment, the second blind hole 126 and the third patterned circuit layer 145 can be formed on the second metallizable photosensitive and developable substrate 125 through a manufacturing process similar to the above.

In detail, in this embodiment, the second metallizable photosensitive and developable substrate 125 can be followed by performing an exposure and development process similar to the above, so as to form a plurality of second blind holes 126 on the second metallizable photosensitive and developable substrate 125 , wherein the second blind hole 126 exposes part of the second patterned circuit layer 142 . Next, an electroless plating process is performed to form a second electroless plating seed layer 135 on the second metallizable photosensitive and developable substrate 125 , and the second electroless plating seed layer 135 covers the inner wall of the second blind hole 126 . In this embodiment, the materials of the first chemical plating seed layer 130 and the second chemical plating seed layer 135 may be the same and both include nickel. Next, a third patterned wiring layer 145 is formed, wherein the third patterned wiring layer 145 is disposed on the second electroless plating seed layer 135 and filled in the second blind hole 126 to be electrically connected to the second patterned wiring layer 142. connect. In this embodiment, the materials of the second patterned circuit layer 142 and the third patterned circuit layer 145 may be the same and both include copper. In this way, the manufacturing method of the circuit board structure 100 is roughly completed.

In terms of structure, the circuit board structure 100 may include a substrate 110, a plurality of first metallizable photosensitive and developable substrates 120, a first electroless plating seed layer 130, a second patterned circuit layer 142, and a second patterned circuit layer 142 as shown in FIG. 1H. Two metallizable photosensitive and developing substrates, a second electroless plating seed layer and a third patterned circuit layer. As shown in FIG. 1A , the substrate 110 includes an insulating substrate 111 , an upper surface 112 , a lower surface 114 opposite to the upper surface 112 , and a first patterned circuit layer 116 disposed on the insulating substrate 111 . In detail, the substrate 110 may include a through hole 118 penetrating through the insulating substrate 111 and a filling material 119 , and the first patterned circuit layer 116 covers the inner wall of the through hole 118 . The filling material 119 can be filled in the through hole 118 . The first metallizable photosensitive and developable substrate 120 is respectively disposed on the upper surface 112 and the lower surface 114 of the substrate 110 . Each first metallizable photosensitive and developable substrate 120 includes a plurality of first blind holes 122, which respectively expose at least part of the first patterned circuit layer 116, and the material of the first metallizable photosensitive and developable substrate 120 includes photosensitive material, so as to directly pattern the first metallizable photosensitive and developable substrate 120 through an exposure and development process. The first electroless plating seed layer 130 is disposed on the first metallizable photosensitive and developable substrate 120 and covers the inner walls of the first blind holes 122 . The second patterned circuit layer 142 is respectively disposed on the first electroless plating seed layer 130 and filled in the first blind hole 122 to be electrically connected to the first patterned circuit layer 116 .

Moreover, the second metallizable photosensitive-developable substrate 125 is disposed on one of the first metallizable photosensitive-developable substrates 120, the second metallizable photosensitive-developable substrate 125 includes a plurality of second blind holes 126, the second The second blind hole 126 exposes at least part of the second patterned circuit layer 142, and the material of the second metallizable photosensitive and developable substrate 125 includes a photosensitive material, thus making the second metallizable photosensitive and developable substrate 125 have light sensitivity . The second electroless plating seed layer 135 is disposed on the second metallizable photosensitive and developable substrate 125 and covers the inner wall of the second blind hole 126 . The third patterned circuit layer 145 is disposed on the second electroless plating seed layer 135 and filled in the second blind hole 126 to be electrically connected to the second patterned circuit layer 142 .

To sum up, the present invention utilizes the photosensitive properties of the metallizable photosensitive and developable substrate to perform an exposure and development process to form a plurality of blind holes on the metallizable photosensitive and developable substrate. Moreover, the present invention forms an electroless plating seed layer on the surface of the metallizable photosensitive development substrate through an electroless plating process, so that the subsequent electroplating process using the electroless plating seed layer as a conductive path forms a patterned circuit layer, and the patterned circuit layer Filling in the blind holes to electrically connect the patterned lines between the stacked structures through the blind holes. Therefore, the present invention effectively simplifies the process steps of the circuit board structure and improves the efficiency of the process. In addition, the present invention can also avoid the problem that glue slag generated by laser drilling remains in the blind hole in the existing blind hole process, thereby improving the process yield of the circuit board structure.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (7)

1. A circuit board structure, characterized in that, comprising: A substrate, including an upper surface, a lower surface opposite to the upper surface, and a first patterned circuit layer; A plurality of first metallizable photosensitive and developable substrates are respectively arranged on the upper surface and the lower surface, each of the first metallizable photosensitive and developable substrates includes a plurality of first blind holes, and the plurality of first metallizable photosensitive and developable substrates include a plurality of first blind holes. A blind hole respectively exposes at least part of the first patterned circuit layer, and each of the first metallizable photosensitive and developable substrates is photosensitive; The first chemical plating seed layer is disposed on the plurality of first metallizable photosensitive and developable substrates and covers the inner wall of each of the first blind holes; The second patterned circuit layer is respectively disposed on the first electroless plating seed layer and filled in the plurality of first blind holes, so as to be electrically connected to the first patterned circuit layer; a second metallizable photo-developable substrate disposed on one of the plurality of first metallizable photo-developable substrates, the second metallizable photo-developable substrate comprising a plurality of second blind vias, The plurality of second blind holes exposes at least part of the second patterned circuit layer, and the second metallizable photosensitive and developable substrate is photosensitive; The second chemical plating seed layer is disposed on the second metallizable photosensitive developable substrate and covers the inner walls of the plurality of second blind holes; and The third patterned circuit layer is disposed on the second electroless plating seed layer and filled in the plurality of second blind holes so as to be electrically connected with the second patterned circuit layer. 2 . The circuit board structure according to claim 1 , wherein the substrate further comprises an insulating base material, and the first patterned circuit layer is disposed on the insulating base material. 3 . 3 . The circuit board structure according to claim 2 , wherein the substrate further comprises a through hole penetrating through the insulating substrate, and the first patterned circuit layer covers an inner wall of the through hole. 4 . 4 . The circuit board structure according to claim 3 , wherein the substrate further comprises a filling material, which is filled in the through hole. 5 . The circuit board structure according to claim 1 , wherein a material of the plurality of first metallizable photosensitive and developable substrates and the second metallizable photosensitive and developable substrate comprises polyimide. 6 . The circuit board structure according to claim 1 , wherein the material of the first electroless plating seed layer and the second electroless plating seed layer includes nickel. 7. The circuit board structure according to claim 1, wherein the material of the second patterned circuit layer and the third patterned circuit layer comprises copper.