US20140042122A1 - Method of manufacturing printed circuit board - Google Patents
Method of manufacturing printed circuit board Download PDFInfo
- Publication number
- US20140042122A1 US20140042122A1 US13/963,907 US201313963907A US2014042122A1 US 20140042122 A1 US20140042122 A1 US 20140042122A1 US 201313963907 A US201313963907 A US 201313963907A US 2014042122 A1 US2014042122 A1 US 2014042122A1
- Authority
- US
- United States
- Prior art keywords
- photosensitive resist
- opening part
- forming
- set forth
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 91
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 42
- 239000002184 metal Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 206010027439 Metal poisoning Diseases 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 239000011701 zinc Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 239000002952 polymeric resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0079—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the method of application or removal of the mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Definitions
- the present invention relates to a method of manufacturing a printed circuit board.
- the via hole is orthogonally etched due to a straight property of the plasma.
- a void may be generated therein.
- the present invention has been made in an effort to provide a method of manufacturing a printed circuit board capable of forming a via hole having a tapered shape by a plasma etching method by forming an opening part of a photosensitive resist in a foot shape.
- the present invention has been made in an effort to provide a method of to manufacturing a printed circuit board capable of simultaneously forming a plurality of via holes by a plasma etching method.
- a method of manufacturing a printed circuit board including: preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer; forming a photosensitive resist on the insulating layer; forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist; forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and forming a via by filling the via hole.
- the photosensitive resist may be made of a positive photosensitive material.
- the forming of the opening part of which the side surface has the foot shape may include: forming a mask on the photosensitive resist for patterning the opening part; exposing the photosensitive resist; removing the mask; and forming the opening part by developing the photosensitive resist.
- the mask may be patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is closed.
- the foot of the opening part may be controlled by an exposure amount at the time of exposing the photosensitive resist.
- the foot of the opening part may be formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
- the foot of the opening part may be controlled by a thickness of the photosensitive resist.
- the method may further include, before the exposing of the photosensitive resist, curing the photosensitive resist.
- the photosensitive resist may be made of a negative photosensitive material.
- the forming of the opening part of which a side surface has a foot shape may include: forming a mask on the photosensitive resist for patterning of the opening part; exposing the to photosensitive resist; removing the mask; and forming the opening part by developing the photosensitive resist.
- the mask may be patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is open.
- the foot of the opening part may be controlled by an exposure amount at the time of exposing the photosensitive resist.
- the foot of the opening part may be formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
- the foot of the opening part may be controlled by a thickness of the photosensitive resist.
- the via hole may be formed by a plasma etching method.
- the method may further include, after the forming of the via hole, removing the photosensitive resist remaining on the insulating layer.
- the photosensitive resist may be coated in a liquid state.
- FIGS. 1 to 9 are exemplary views showing a method of manufacturing a printed circuit board according to the preferred embodiment of the present invention.
- FIGS. 10 to 18 are exemplary views showing a method of manufacturing a printed circuit board according to another preferred embodiment of the present invention.
- FIGS. 1 to 9 are exemplary views showing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention.
- the base substrate 110 may include an insulating layer 111 and a circuit layer 120 .
- the insulating layer 111 may be made of a composite polymer resin that is generally used as an interlayer insulation material.
- the insulating layer 111 may be made of a prepreg, or an epoxy based resin such as Ajinomoto Build up Film (ABF), FR-4, a Bismaleimide Triazine (BT) or the like.
- the insulating layer may have a form of a substrate or a film.
- the material and the form of the insulating layer are not limited in the preferred embodiment of the present invention.
- the circuit layer 120 may include a circuit pattern 121 , a connection pad 122 , and a via (not shown).
- the circuit layer 120 may be made of a conductive material.
- the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like.
- the circuit layer 120 may be formed in the insulating layer 111 .
- the circuit layer 120 formed in the insulating layer 111 is shown as a single layer, but is not limited thereto. That is, the circuit layer 120 may be formed in a single layer and a multilayer.
- a photosensitive resist 131 may be formed on the base substrate 110 .
- the photosensitive resist 131 may be formed on the insulating layer 111 of the base substrate 110 .
- the photosensitive resist 131 may be made of a positive photosensitive material in the preferred embodiment of the present invention.
- the photosensitive resist 132 may be formed by being coated in a liquid state on the insulating layer 111 .
- the photosensitive resist 131 may be formed so as to have a thickness enough to form a foot in the opening part 140 to be formed later. That is, a shape of the foot of the opening part 140 to be formed later may be controlled according to the thickness of the photosensitive resist 131 .
- the photosensitive resist 131 may have a thickness of 10 um to 150 um, which is a general range in the industry. However, in the case in which the thickness of the photosensitive resist 131 is deviated from the above-mentioned range, at the time of forming the opening part 140 , the photosensitive resist 131 may have the thickness of several nm to several mm in which the foot may be formed.
- a mask 210 may be formed on the photosensitive resist 131 .
- the mask 210 may be formed in an upper portion of a region in which the opening part 140 of the photosensitive resist 131 is to be formed.
- the mask 210 may be formed in a shape in which a portion corresponding to a region in which the opening part 140 of the photosensitive resist 131 is formed is closed. That is, the mask 210 may be formed so that other regions except a region in which the opening part 140 of the photosensitive resist 131 are exposed to the outside.
- the opening part 140 may be formed in the photosensitive resist 131 .
- the opening part 140 of the photosensitive resist 131 may be formed so as to expose the insulating layer 111 positioned on the connection pad 122 .
- the opening part 140 may be formed by performing exposure and development processes on the photosensitive resist 131 . Firstly, a thermosetting process may be performed on the photosensitive resist 131 .
- the exposure process may be performed on the photosensitive resist 131 .
- the exposure process may be performed on the remaining region of the photosensitive resist 131 except the region which is closed by the mask 210 .
- an exposure amount is controlled, thereby making it possible to form the opening part 140 in a foot shape later.
- the exposure process may be performed with the exposure amount in which the singular number of steps has the range of ⁇ 20% to 250%.
- the exposure amount is not limited thereto.
- the exposure process may be performed in the range at which the singular number of steps is ⁇ 1% to 500%.
- the mask 210 formed on the photosensitive resist 131 may be removed.
- the development process may be performed on the photosensitive resist 131 .
- a portion at which the exposure process is not performed may be removed by a developer. That is, the region of the photosensitive resist 131 closed by the mask 210 is removed, thereby making it possible to form the opening part 140 .
- the development process is performed under an overdevelopment condition or an underdevelopment condition, thereby making it possible to form the foot of the opening part 140 .
- the opening part 140 of which the side surface 141 has a foot shape may be formed in the photosensitive resist 131 .
- both of the exposure and the development processes are performed according to each condition in order to form the foot of the opening part 140 , but is not limited thereto. That is, only one condition of the exposure condition and the development condition for forming the foot of the opening part 140 is selected to perform the exposure and the development processes, thereby making it possible to form the opening part 140 having the foot shape.
- a via hole 150 may be formed on the base substrate 110 .
- the via hole 150 may be formed by etching the insulating layer 111 exposed by the opening part 140 of the photosensitive resist 131 .
- the via hole 150 may be formed by a plasma etching method. In the plasma etching method, a plurality of via holes 150 may be simultaneously formed. The plasma etching process may be performed until the connection pad 122 is exposed to the outside.
- the via hole 150 may be formed in a tapered shape by the opening part 140 having the foot shape of the photosensitive resist 131 .
- the opening part 140 having the foot shape in which the side surface 141 thereof has a slope an upper diameter and a bottom diameter of the opening part 140 are different, respectively. That is, in the side surface 141 of the opening part 140 , height thereof may be smaller toward the center of the opening part 140 . Therefore, a thickness of the photosensitive resist 131 may be smaller toward the center of the opening part 140 .
- the insulating layer 111 may be etched in proportion to the thickness of the photosensitive resist 131 .
- the insulating layer 11 may be thinly etched, in a region having a thin thickness of the photosensitive resist 131 , the insulating layer 111 may be deeply etched, and in a region not having the photosensitive resist 131 , the insulating layer 111 may be etched at maximum.
- the opening part 140 of the photosensitive resist 131 has the foot shape, such that the via hole 150 may be formed in the tapered shape even in the case in which the etching process is performed by the plasma having a straight property.
- the photosensitive resist 131 remaining on the base substrate 110 may be removed.
- the photosensitive resist 131 may be removed by the plasma etching process performed for forming the via hole 150 .
- the photosensitive resist 131 may remain on the base substrate 110 even after forming the via hole 150 .
- a desmear process may be performed.
- a seed layer 160 may be formed on the insulating layer 111 and inner wall of the via hole 150 .
- the seed layer 160 may be formed so as to serve as a leadline for an electroplating process to be performed later.
- a method of forming the seed layer 160 is not specifically limited, but conventional depositing methods known in the art may be used.
- the seed layer 160 may be formed by a wet plating method such as an electroless plating method. Otherwise, the seed layer 160 may be formed by a dry plating method such as a sputtering method.
- a metal layer 170 may be formed on the seed layer 160 and inner wall of the via hole 150 .
- the metal layer 170 may be made of a conductive material.
- the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like.
- a method of forming the metal layer 170 is not specifically limited, but conventional depositing methods known in the art may be used.
- the metal layer 170 may be formed by using the seed layer 160 as the leadline and performing the electroplating process.
- a via 171 may be formed.
- the via 171 may be formed by removing the remaining metal layer 170 and the seed layer 160 except the metal layer 170 filled in the via hole 150 .
- the metal layer 170 and the seed layer 160 may be removed by a physical polishing machining process. Otherwise, the metal layer 170 and the seed layer 160 may be removed by a city etching process and a wet etching process.
- only the via 171 is formed, but is not limited thereto. That is, in addition to the via 171 , a circuit pattern may be formed on the insulating layer 111 by patterning the metal layer 170 .
- FIGS. 10 to 18 are exemplary views showing a method of manufacturing a printed circuit board according to another preferred embodiment of the present invention.
- the base substrate 110 is prepared.
- the base substrate 110 may include an insulating layer 111 and a circuit layer 120 .
- the insulating layer 111 may be made of a composite polymer resin that is generally used as an interlayer insulation material.
- the insulating layer 111 may be made of a prepreg, or an epoxy based resin such as Ajinomoto Build up Film (ABF), FR- 4 , a Bismaleimide Triazine ( 131 ) or the like.
- the insulating layer may have a form of a substrate or a film.
- the circuit layer 120 may include a circuit pattern 121 , a connection pad 122 , and a via (not shown).
- the circuit layer 120 may be made of a conductive material.
- the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like.
- the circuit layer 120 may be formed in the insulating layer 111 .
- the circuit layer 120 formed in the insulating layer 111 is shown as a single layer, but is not limited thereto. That is, the circuit layer 120 may be formed in a single layer and a multilayer.
- a photosensitive resist 132 may be formed on the base substrate 110 .
- the photosensitive resist 132 may be formed on the insulating layer 111 of the base substrate 110 .
- the photosensitive resist 132 may be made of a negative photosensitive material in another preferred embodiment of the present invention.
- the photosensitive resist 132 may be formed by being coated in a liquid state on the insulating layer 111 .
- the photosensitive resist 132 may be formed so as to have a thickness enough to form a foot in the opening part 140 to be formed later. That is, a shape of the foot of the opening part 140 to be formed later may be controlled according to the thickness of the photosensitive resist 132 .
- the photosensitive resist 132 may have a thickness of 10 um to 150 um, which is a general range in the industry. However, in the case in which the thickness of the photosensitive resist 132 is deviated from the above-mentioned range, at the time of forming the opening part 140 , the photosensitive resist 132 may have the thickness of several nm to several mm in which the foot may be formed.
- a mask 210 may be formed on the photosensitive resist 132 .
- the mask 210 may be formed in a shape in which a portion corresponding to a region in which the opening part 140 of the photosensitive resist 132 is formed is open. That is, the mask 210 may be formed so as to expose only the region in which the opening part 140 is to be formed in the photosensitive resist 132 to the outside.
- the mask 140 may be formed on the photosensitive resist 132 .
- the opening part 140 of the photosensitive resist 132 may be formed so as to expose the insulating layer 111 positioned on the connection pad 122 .
- the opening part 140 may be formed by performing exposure and development processes on the photosensitive resist 132 .
- the mask 210 formed on the photosensitive resist 132 may be removed.
- the development process may be performed on the photosensitive resist 132 .
- a portion at which the exposure process is performed may be removed by a developer.
- the development process is performed under an overdevelopment condition or an underdevelopment condition, thereby making it possible to form the foot of the opening part 140 .
- the opening part 140 of which the side surface 141 has a foot shape may be formed in the photosensitive resist 132 .
- both of the exposure and the development processes are performed according to each condition in order to form the foot of the opening part 140 , but is not limited thereto. That is, only one condition of the exposure condition and the development condition for forming the foot of the opening part 140 is selected to perform the exposure and the development processes, thereby making it possible to form the opening part 140 having the foot shape.
- a via hole 150 may be formed on the base substrate 110 .
- the via hole 150 may be formed by etching the insulating layer 111 exposed by the opening part 140 of the photosensitive resist 132 .
- the via hole 150 may be formed by a plasma etching method. The plasma etching may be performed until the connection pad 122 is exposed to the outside.
- the via hole 150 may be formed in a tapered shape by the opening part 140 having the foot shape of the photosensitive resist 132 .
- the opening part 140 having the foot shape in which the side surface 141 thereof has a slope an upper diameter and a bottom diameter of the opening part 140 are different, respectively. That is, in the side surface 141 of the opening part 140 , height thereof may be smaller toward the center of the opening part 140 . Therefore, a thickness of the photosensitive resist 132 may be smaller toward the center of the opening part 140 .
- the insulating layer 111 may be etched in proportion to the thickness of the photosensitive resist 132 .
- the insulating layer 11 may be thinly etched, in a region having a thin thickness of the photosensitive resist 132 , the insulating layer 111 may be deeply etched, and in a region not having the photosensitive resist 132 , the insulating layer 111 may be etched as much as possible.
- the opening part 140 of the photosensitive resist 132 has the foot shape, such that the via hole 150 may be formed in the tapered shape even in the case in which the etching process is performed by the plasma having a straight property.
- the photosensitive resist 132 exposed to the plasma may be also simultaneously etched. Therefore, as shown in FIG. 14 , as the via hole 150 is formed, the photosensitive resist 132 may be removed, or the thickness thereof may be reduced.
- the photosensitive resist 132 remaining on the base substrate 110 may be removed.
- the photosensitive resist 132 may be removed by the plasma etching process performed for forming the via hole 150 .
- the photosensitive resist 132 may remain on the base substrate 110 even after forming the via hole 150 .
- a desmear process may be performed.
- a seed layer 150 may be formed on the insulating layer 111 and inner wall of the via hole 150 .
- the seed layer 160 may be formed so as to serve as a leadline for an electroplating process to be performed later.
- a method of forming the seed layer 160 is not specifically limited, but conventional depositing methods known in the art may be used.
- the seed layer 160 may be formed by a wet plating method such as an electroless plating method. Otherwise, the seed layer 160 may be formed by a dry plating method such as a sputtering method.
- a metal layer 170 may be formed on the seed layer 160 and inner wall of the via hole 150 .
- the metal layer 170 may be made of a conductive material.
- the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like.
- a method of forming the metal layer 170 is not specifically limited, but conventional depositing methods known in the art may be used.
- the metal layer 170 may be formed by using the seed layer 160 as the leadline and performing the electroplating process.
- a via 171 may be formed.
- the via 171 may be formed by removing the remaining metal layer 170 and the seed layer 160 except the metal layer 170 filled in the via hole 150 .
- the metal layer 170 and the seed layer 160 may be removed by a physical polishing process. Otherwise, the metal layer 170 and the seed layer 160 may be removed by a dry etching process and a wet etching process.
- FIG. 9 only the via 171 is formed, but is not limited thereto. That is, in addition to the via 171 , a circuit pattern may be formed on the insulating layer 111 by patterning the metal layer 170 .
- the opening part of the photosensitive resist is formed in the foot shape, thereby making it possible to form the via hole having the tapered shape using the plasma etching method.
- the via hole is formed by the plasma etching method, thereby making it possible to simultaneously form the plurality of via holes.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Disclosed herein is a method of manufacturing a printed circuit board, the method including: preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer; forming a photosensitive resist on the insulating layer; forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist; forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and forming a via by filling the via hole.
Description
- This application claims the benefit of Korean Patent Application No. 10-2012-0088449, filed on Aug. 13, 2012, entitled “Method of Manufacturing a Printed Circuit Board”, which is hereby incorporated by reference in its entirety into this application.
- 1. Technical Field
- The present invention relates to a method of manufacturing a printed circuit board.
- 2. Description of the Related Art
- Recently, a demand for a technology of directly mounting a semiconductor chip on a printed circuit board with high density of the semiconductor chip, and high speed of signal transmission speed has become increased. Accordingly, a printed circuit board having high density and high reliability capable of implementing a high density semiconductor chip has been required to be developed.
- Specification which is required for the printed circuit board having the high density and high reliability has a close relationship with that of the semiconductor chip, and there are many challenges such as miniaturization of a circuit, high electrical property, high speed signal transmission structure, high reliability, high functionality, and the like. In order to implement these challenges, a technology of a printed circuit board capable of forming a via hole is required. U.S. Pat. No. 6,240,636 discloses the via hole formed by generally using a laser or a drill. However, in the case of forming the via hole by using the laser or the drill, a plurality of via holes are required to be individually processed. In the case of forming the via hole by using plasma, the plurality of via holes may be simultaneously processed. However, at the time of performing a plasma etching process, the via hole is orthogonally etched due to a straight property of the plasma. In the case in which the via hole does not have a tapered shape but is orthogonally etched, at the time of filling the via hole by an electroplating process, a void may be generated therein.
- The present invention has been made in an effort to provide a method of manufacturing a printed circuit board capable of forming a via hole having a tapered shape by a plasma etching method by forming an opening part of a photosensitive resist in a foot shape.
- Further, the present invention has been made in an effort to provide a method of to manufacturing a printed circuit board capable of simultaneously forming a plurality of via holes by a plasma etching method.
- According to a preferred embodiment of the present invention, there is provided a method of manufacturing a printed circuit board, the method including: preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer; forming a photosensitive resist on the insulating layer; forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist; forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and forming a via by filling the via hole.
- The photosensitive resist may be made of a positive photosensitive material.
- The forming of the opening part of which the side surface has the foot shape may include: forming a mask on the photosensitive resist for patterning the opening part; exposing the photosensitive resist; removing the mask; and forming the opening part by developing the photosensitive resist.
- In the forming of the mask, the mask may be patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is closed.
- In the forming of the opening part, the foot of the opening part may be controlled by an exposure amount at the time of exposing the photosensitive resist.
- In the forming of the opening part, the foot of the opening part may be formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
- In the forming of the opening part, the foot of the opening part may be controlled by a thickness of the photosensitive resist.
- The method may further include, before the exposing of the photosensitive resist, curing the photosensitive resist.
- The photosensitive resist may be made of a negative photosensitive material.
- The forming of the opening part of which a side surface has a foot shape may include: forming a mask on the photosensitive resist for patterning of the opening part; exposing the to photosensitive resist; removing the mask; and forming the opening part by developing the photosensitive resist.
- In the forming of the mask, the mask may be patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is open.
- In the forming of the opening part, the foot of the opening part may be controlled by an exposure amount at the time of exposing the photosensitive resist.
- In the forming of the opening part, the foot of the opening part may be formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
- In the forming of the opening part, the foot of the opening part may be controlled by a thickness of the photosensitive resist.
- In the forming of the via hole, the via hole may be formed by a plasma etching method.
- The method may further include, after the forming of the via hole, removing the photosensitive resist remaining on the insulating layer.
- In the forming of the photosensitive resist, the photosensitive resist may be coated in a liquid state.
- The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1 to 9 are exemplary views showing a method of manufacturing a printed circuit board according to the preferred embodiment of the present invention; and -
FIGS. 10 to 18 are exemplary views showing a method of manufacturing a printed circuit board according to another preferred embodiment of the present invention. - The objects, features and advantages of the present invention will be more clearly understood from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. Further, in the following description, the terms “first”, “second”, “one side”, “the other side” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms. Further, in the description of the present invention, when it is determined that the detailed description of the related art would obscure the gist of the present invention, the description thereof will be omitted.
- Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
-
FIGS. 1 to 9 are exemplary views showing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention. - Referring to
FIG. 1 , abase substrate 110 is prepared. Thebase substrate 110 may include aninsulating layer 111 and acircuit layer 120. - The
insulating layer 111 may be made of a composite polymer resin that is generally used as an interlayer insulation material. For example, theinsulating layer 111 may be made of a prepreg, or an epoxy based resin such as Ajinomoto Build up Film (ABF), FR-4, a Bismaleimide Triazine (BT) or the like. In addition, the insulating layer may have a form of a substrate or a film. However, the material and the form of the insulating layer are not limited in the preferred embodiment of the present invention. - The
circuit layer 120 may include acircuit pattern 121, aconnection pad 122, and a via (not shown). Thecircuit layer 120 may be made of a conductive material. For example, the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like. - The
circuit layer 120 may be formed in theinsulating layer 111. InFIG. 1 , thecircuit layer 120 formed in theinsulating layer 111 is shown as a single layer, but is not limited thereto. That is, thecircuit layer 120 may be formed in a single layer and a multilayer. - Referring to
FIG. 2 , aphotosensitive resist 131 may be formed on thebase substrate 110. Thephotosensitive resist 131 may be formed on theinsulating layer 111 of thebase substrate 110. Thephotosensitive resist 131 may be made of a positive photosensitive material in the preferred embodiment of the present invention. In addition, thephotosensitive resist 132 may be formed by being coated in a liquid state on theinsulating layer 111. The photosensitive resist 131 may be formed so as to have a thickness enough to form a foot in theopening part 140 to be formed later. That is, a shape of the foot of theopening part 140 to be formed later may be controlled according to the thickness of the photosensitive resist 131. For example, the photosensitive resist 131 may have a thickness of 10 um to 150 um, which is a general range in the industry. However, in the case in which the thickness of the photosensitive resist 131 is deviated from the above-mentioned range, at the time of forming theopening part 140, the photosensitive resist 131 may have the thickness of several nm to several mm in which the foot may be formed. - Referring to
FIG. 3 , amask 210 may be formed on the photosensitive resist 131. Themask 210 may be formed in an upper portion of a region in which theopening part 140 of the photosensitive resist 131 is to be formed. Themask 210 may be formed in a shape in which a portion corresponding to a region in which theopening part 140 of the photosensitive resist 131 is formed is closed. That is, themask 210 may be formed so that other regions except a region in which theopening part 140 of the photosensitive resist 131 are exposed to the outside. - Referring to
FIG. 4 , theopening part 140 may be formed in the photosensitive resist 131. Theopening part 140 of the photosensitive resist 131 may be formed so as to expose the insulatinglayer 111 positioned on theconnection pad 122. - The
opening part 140 may be formed by performing exposure and development processes on the photosensitive resist 131. Firstly, a thermosetting process may be performed on the photosensitive resist 131. - After performing the thermosetting process, the exposure process may be performed on the photosensitive resist 131. Here, the exposure process may be performed on the remaining region of the photosensitive resist 131 except the region which is closed by the
mask 210. Here, an exposure amount is controlled, thereby making it possible to form theopening part 140 in a foot shape later. For example, the exposure process may be performed with the exposure amount in which the singular number of steps has the range of ±20% to 250%. However, at the time of performing the exposure process, the exposure amount is not limited thereto. In the case in which the foot of theopening part 140 may be controlled, the exposure process may be performed in the range at which the singular number of steps is ±1% to 500%. - After performing the exposure process, the
mask 210 formed on the photosensitive resist 131 may be removed. - After removing the
mask 210, the development process may be performed on the photosensitive resist 131. In the photosensitive resist 131, a portion at which the exposure process is not performed may be removed by a developer. That is, the region of the photosensitive resist 131 closed by themask 210 is removed, thereby making it possible to form theopening part 140. Here, the development process is performed under an overdevelopment condition or an underdevelopment condition, thereby making it possible to form the foot of theopening part 140. - By performing the thermosetting, exposure, and development processes, the
opening part 140 of which theside surface 141 has a foot shape may be formed in the photosensitive resist 131. - In the preferred embodiment of the present invention, the thermosetting process is performed before the exposure process in order to form the
opening part 140 of which theside surface 141 has the foot shape, but is not limited thereto. The thermosetting process may be easily omitted by those skilled in the art, according to a material, or the like, of the photosensitive resist 131. - In addition, in the preferred embodiment of the present invention, both of the exposure and the development processes are performed according to each condition in order to form the foot of the
opening part 140, but is not limited thereto. That is, only one condition of the exposure condition and the development condition for forming the foot of theopening part 140 is selected to perform the exposure and the development processes, thereby making it possible to form theopening part 140 having the foot shape. - Referring to
FIG. 5 , a viahole 150 may be formed on thebase substrate 110. The viahole 150 may be formed by etching the insulatinglayer 111 exposed by theopening part 140 of the photosensitive resist 131. The viahole 150 may be formed by a plasma etching method. In the plasma etching method, a plurality of viaholes 150 may be simultaneously formed. The plasma etching process may be performed until theconnection pad 122 is exposed to the outside. - Here, at the time of performing the plasma etching process, the via
hole 150 may be formed in a tapered shape by theopening part 140 having the foot shape of the photosensitive resist 131. In theopening part 140 having the foot shape in which theside surface 141 thereof has a slope, an upper diameter and a bottom diameter of theopening part 140 are different, respectively. That is, in theside surface 141 of theopening part 140, height thereof may be smaller toward the center of theopening part 140. Therefore, a thickness of the photosensitive resist 131 may be smaller toward the center of theopening part 140. At the time of the plasma etching process, the insulatinglayer 111 may be etched in proportion to the thickness of the photosensitive resist 131. That is, in a region having a thick thickness of the photosensitive resist 131, the insulating layer 11 may be thinly etched, in a region having a thin thickness of the photosensitive resist 131, the insulatinglayer 111 may be deeply etched, and in a region not having the photosensitive resist 131, the insulatinglayer 111 may be etched at maximum. - As described above, the
opening part 140 of the photosensitive resist 131 has the foot shape, such that the viahole 150 may be formed in the tapered shape even in the case in which the etching process is performed by the plasma having a straight property. - Due to the properties of plasma etching, at the time of etching the insulating
layer 111, the photosensitive resist 131 exposed to the plasma may be also simultaneously etched. Therefore, as shown inFIG. 5 , as the viahole 150 is formed, the photosensitive resist 131 may be removed, or the thickness thereof may be reduced. - Referring to
FIG. 6 , the photosensitive resist 131 remaining on thebase substrate 110 may be removed. The photosensitive resist 131 may be removed by the plasma etching process performed for forming the viahole 150. However, in the case in which the thickness of the photosensitive resist 131 is thick, the photosensitive resist 131 may remain on thebase substrate 110 even after forming the viahole 150. In order to remove the photosensitive resist 131 remaining on thebase substrate 110, a desmear process may be performed. - Referring to
FIG. 7 , aseed layer 160 may be formed on the insulatinglayer 111 and inner wall of the viahole 150. Theseed layer 160 may be formed so as to serve as a leadline for an electroplating process to be performed later. For example, a method of forming theseed layer 160 is not specifically limited, but conventional depositing methods known in the art may be used. For example, theseed layer 160 may be formed by a wet plating method such as an electroless plating method. Otherwise, theseed layer 160 may be formed by a dry plating method such as a sputtering method. - Referring to
FIG. 8 , ametal layer 170 may be formed on theseed layer 160 and inner wall of the viahole 150. Themetal layer 170 may be made of a conductive material. For example, the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like. A method of forming themetal layer 170 is not specifically limited, but conventional depositing methods known in the art may be used. For example, themetal layer 170 may be formed by using theseed layer 160 as the leadline and performing the electroplating process. - Referring to
FIG. 9 , a via 171 may be formed. The via 171 may be formed by removing the remainingmetal layer 170 and theseed layer 160 except themetal layer 170 filled in the viahole 150. For example, themetal layer 170 and theseed layer 160 may be removed by a physical polishing machining process. Otherwise, themetal layer 170 and theseed layer 160 may be removed by a city etching process and a wet etching process. InFIG. 9 , only the via 171 is formed, but is not limited thereto. That is, in addition to the via 171, a circuit pattern may be formed on the insulatinglayer 111 by patterning themetal layer 170. -
FIGS. 10 to 18 are exemplary views showing a method of manufacturing a printed circuit board according to another preferred embodiment of the present invention. Referring toFIG. 10 , thebase substrate 110 is prepared. Thebase substrate 110 may include an insulatinglayer 111 and acircuit layer 120. - The insulating
layer 111 may be made of a composite polymer resin that is generally used as an interlayer insulation material. For example, the insulatinglayer 111 may be made of a prepreg, or an epoxy based resin such as Ajinomoto Build up Film (ABF), FR-4, a Bismaleimide Triazine (131) or the like. In addition, the insulating layer may have a form of a substrate or a film. - However, the material and the form of the insulating layer are not limited in the preferred embodiment of the present invention.
- The
circuit layer 120 may include acircuit pattern 121, aconnection pad 122, and a via (not shown). Thecircuit layer 120 may be made of a conductive material. For example, the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like. - The
circuit layer 120 may be formed in the insulatinglayer 111. InFIG. 1 , thecircuit layer 120 formed in the insulatinglayer 111 is shown as a single layer, but is not limited thereto. That is, thecircuit layer 120 may be formed in a single layer and a multilayer. - Referring to
FIG. 11 , a photosensitive resist 132 may be formed on thebase substrate 110. The photosensitive resist 132 may be formed on the insulatinglayer 111 of thebase substrate 110. The photosensitive resist 132 may be made of a negative photosensitive material in another preferred embodiment of the present invention. In addition, the photosensitive resist 132 may be formed by being coated in a liquid state on the insulatinglayer 111. The photosensitive resist 132 may be formed so as to have a thickness enough to form a foot in theopening part 140 to be formed later. That is, a shape of the foot of theopening part 140 to be formed later may be controlled according to the thickness of the photosensitive resist 132. For example, the photosensitive resist 132 may have a thickness of 10 um to 150 um, which is a general range in the industry. However, in the case in which the thickness of the photosensitive resist 132 is deviated from the above-mentioned range, at the time of forming theopening part 140, the photosensitive resist 132 may have the thickness of several nm to several mm in which the foot may be formed. - Referring to
FIG. 12 , amask 210 may be formed on the photosensitive resist 132. Themask 210 may be formed in a shape in which a portion corresponding to a region in which theopening part 140 of the photosensitive resist 132 is formed is open. That is, themask 210 may be formed so as to expose only the region in which theopening part 140 is to be formed in the photosensitive resist 132 to the outside. - Referring to
FIG. 13 , themask 140 may be formed on the photosensitive resist 132. Theopening part 140 of the photosensitive resist 132 may be formed so as to expose the insulatinglayer 111 positioned on theconnection pad 122. - The
opening part 140 may be formed by performing exposure and development processes on the photosensitive resist 132. - Firstly, the exposure process may be performed on the photosensitive resist 132. Here, the exposure process may be performed only in the region open by the
mask 210. Here, an exposure amount is controlled, thereby making it possible to form theopening part 140 in a foot shape later. For example, the exposure process may be performed with the exposure amount in which the singular number of steps is ±20% to 250%. However, at the time of performing the exposure process, the exposure amount is not limited thereto. In the case in which the foot of theopening part 140 may be controlled, the exposure process may be performed in the range at which the singular number of steps is ±1% to 500%. - After performing the exposure process, the
mask 210 formed on the photosensitive resist 132 may be removed. - After removing the
mask 210, the development process may be performed on the photosensitive resist 132. In the photosensitive resist 132, a portion at which the exposure process is performed may be removed by a developer. Here, the development process is performed under an overdevelopment condition or an underdevelopment condition, thereby making it possible to form the foot of theopening part 140. - By performing the exposure and the development processes, the
opening part 140 of which theside surface 141 has a foot shape may be formed in the photosensitive resist 132. - In the preferred embodiment of the present invention, both of the exposure and the development processes are performed according to each condition in order to form the foot of the
opening part 140, but is not limited thereto. That is, only one condition of the exposure condition and the development condition for forming the foot of theopening part 140 is selected to perform the exposure and the development processes, thereby making it possible to form theopening part 140 having the foot shape. - Referring to
FIG. 14 , a viahole 150 may be formed on thebase substrate 110. The viahole 150 may be formed by etching the insulatinglayer 111 exposed by theopening part 140 of the photosensitive resist 132. The viahole 150 may be formed by a plasma etching method. The plasma etching may be performed until theconnection pad 122 is exposed to the outside. - Here, at the time of performing the plasma etching process, the via
hole 150 may be formed in a tapered shape by theopening part 140 having the foot shape of the photosensitive resist 132. In theopening part 140 having the foot shape in which theside surface 141 thereof has a slope, an upper diameter and a bottom diameter of theopening part 140 are different, respectively. That is, in theside surface 141 of theopening part 140, height thereof may be smaller toward the center of theopening part 140. Therefore, a thickness of the photosensitive resist 132 may be smaller toward the center of theopening part 140. At the time of the plasma etching process, the insulatinglayer 111 may be etched in proportion to the thickness of the photosensitive resist 132. That is, in a region having a thick thickness of the photosensitive resist 132, the insulating layer 11 may be thinly etched, in a region having a thin thickness of the photosensitive resist 132, the insulatinglayer 111 may be deeply etched, and in a region not having the photosensitive resist 132, the insulatinglayer 111 may be etched as much as possible. - As described above, the
opening part 140 of the photosensitive resist 132 has the foot shape, such that the viahole 150 may be formed in the tapered shape even in the case in which the etching process is performed by the plasma having a straight property. - Due to the properties of the plasma etching, at the time of etching the insulating
layer 111, the photosensitive resist 132 exposed to the plasma may be also simultaneously etched. Therefore, as shown inFIG. 14 , as the viahole 150 is formed, the photosensitive resist 132 may be removed, or the thickness thereof may be reduced. - Referring to
FIG. 15 , the photosensitive resist 132 remaining on thebase substrate 110 may be removed. The photosensitive resist 132 may be removed by the plasma etching process performed for forming the viahole 150. However, in the case in which the thickness of the photosensitive resist 132 is thick, the photosensitive resist 132 may remain on thebase substrate 110 even after forming the viahole 150. In order to remove the photosensitive resist 132 remaining on thebase substrate 110, a desmear process may be performed. - Referring to
FIG. 16 , aseed layer 150 may be formed on the insulatinglayer 111 and inner wall of the viahole 150. Theseed layer 160 may be formed so as to serve as a leadline for an electroplating process to be performed later. For example, a method of forming theseed layer 160 is not specifically limited, but conventional depositing methods known in the art may be used. For example, theseed layer 160 may be formed by a wet plating method such as an electroless plating method. Otherwise, theseed layer 160 may be formed by a dry plating method such as a sputtering method. - Referring to
FIG. 17 , ametal layer 170 may be formed on theseed layer 160 and inner wall of the viahole 150. Themetal layer 170 may be made of a conductive material. For example, the conductive material may be an electrically conductive metal such as gold, silver, zinc, nickel, copper, or the like. A method of forming themetal layer 170 is not specifically limited, but conventional depositing methods known in the art may be used. For example, themetal layer 170 may be formed by using theseed layer 160 as the leadline and performing the electroplating process. - Referring to
FIG. 18 , a via 171 may be formed. The via 171 may be formed by removing the remainingmetal layer 170 and theseed layer 160 except themetal layer 170 filled in the viahole 150. For example, themetal layer 170 and theseed layer 160 may be removed by a physical polishing process. Otherwise, themetal layer 170 and theseed layer 160 may be removed by a dry etching process and a wet etching process. InFIG. 9 , only the via 171 is formed, but is not limited thereto. That is, in addition to the via 171, a circuit pattern may be formed on the insulatinglayer 111 by patterning themetal layer 170. - As set forth above, with the method of manufacturing the printed circuit board according to the preferred embodiment of the present invention, the opening part of the photosensitive resist is formed in the foot shape, thereby making it possible to form the via hole having the tapered shape using the plasma etching method.
- In addition, with the method of manufacturing the printed circuit board according to the preferred embodiment of the present invention, the via hole is formed by the plasma etching method, thereby making it possible to simultaneously form the plurality of via holes.
- Although the embodiments of the present invention have been disclosed for illustrative purposes, it will be appreciated that the present invention is not limited thereto, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
- Accordingly, any and all modifications, variations or equivalent arrangements should be considered to be within the scope of the invention, and the detailed scope of the invention will be disclosed by the accompanying claims.
Claims (17)
1. A method of manufacturing a printed circuit board, the method comprising:
preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer;
forming a photosensitive resist on the insulating layer;
forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist;
forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and
forming a via by filling the via hole.
2. The method as set forth in claim 1 , wherein the photosensitive resist is made of a positive photosensitive material.
3. The method as set forth in claim 2 , wherein the forming of the opening part of which the side surface has the foot shape includes:
forming a mask on the photosensitive resist for patterning the opening part;
exposing the photosensitive resist;
removing the mask; and
forming the opening part by developing the photosensitive resist.
4. The method as set forth in claim 3 , wherein in the forming of the mask, the mask is patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is closed.
5. The method as set forth in claim 3 , wherein in the forming of the opening part, the foot of the opening part is controlled by an exposure amount at the time of exposing the photosensitive resist.
6. The method as set forth in claim 3 , wherein in the forming of the opening part, the foot of the opening part is formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
7. The method as set forth in claim 3 , wherein in the forming of the opening part, the foot of the opening part is controlled by a thickness of the photosensitive resist.
8. The method as set forth in claim 3 , further comprising, before the exposing of the photosensitive resist, curing the photosensitive resist.
9. The method as set forth in claim 1 , wherein the photosensitive resist is made of a negative photosensitive material.
10. The method as set forth in claim 9 , wherein the forming of the opening part of which a side surface has a foot shape includes:
forming a mask on the photosensitive resist for patterning of the opening part;
exposing the photosensitive resist;
removing the mask; and
forming the opening part by developing the photosensitive resist.
11. The method as set forth in claim 10 , wherein in the forming of the mask, the mask is patterned so that an upper portion of a region in which the opening part of the photosensitive resist is to be formed is open.
12. The method as set forth in claim 10 , wherein in the forming of the opening part, the foot of the opening part is controlled by an exposure amount at the time of exposing the photosensitive resist
13. The method as set forth in claim 10 , wherein in the forming of the opening part, the foot of the opening part is formed by performing a development process under an overdevelopment condition or an underdevelopment condition.
14. The method as set forth in claim 10 , wherein in the forming of the opening part, the foot of the opening part is controlled by a thickness of the photosensitive resist.
15. The method as set forth in claim 1 , wherein in the forming of the via hole, the via hole is formed by a plasma etching method.
16. The method as set forth in claim 1 , further comprising, after the forming of the via hole, removing the photosensitive resist remaining on the insulating layer.
17. The method as set forth in claim 1 , wherein in the forming of the photosensitive resist, the photosensitive resist is coated in a liquid state.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2012-0088449 | 2012-08-13 | ||
KR1020120088449A KR20140021914A (en) | 2012-08-13 | 2012-08-13 | Method of manufacturing a printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140042122A1 true US20140042122A1 (en) | 2014-02-13 |
Family
ID=50065409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/963,907 Abandoned US20140042122A1 (en) | 2012-08-13 | 2013-08-09 | Method of manufacturing printed circuit board |
Country Status (3)
Country | Link |
---|---|
US (1) | US20140042122A1 (en) |
JP (1) | JP2014039032A (en) |
KR (1) | KR20140021914A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140374919A1 (en) * | 2013-06-24 | 2014-12-25 | Imec | Method for Producing Contact Areas on a Semiconductor Substrate |
CN111526666A (en) * | 2020-04-30 | 2020-08-11 | 生益电子股份有限公司 | PCB manufacturing method |
DE102021209939A1 (en) | 2021-09-08 | 2023-03-09 | Gebr. Schmid Gmbh | Printed Circuit Board Manufacturing Process and Printed Circuit Board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114080100B (en) * | 2020-08-21 | 2024-11-12 | 欣兴电子股份有限公司 | Circuit board and method for forming holes therein |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4543320A (en) * | 1983-11-08 | 1985-09-24 | Energy Conversion Devices, Inc. | Method of making a high performance, small area thin film transistor |
US20120161330A1 (en) * | 2010-12-22 | 2012-06-28 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
-
2012
- 2012-08-13 KR KR1020120088449A patent/KR20140021914A/en not_active Withdrawn
-
2013
- 2013-08-09 US US13/963,907 patent/US20140042122A1/en not_active Abandoned
- 2013-08-12 JP JP2013167785A patent/JP2014039032A/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4543320A (en) * | 1983-11-08 | 1985-09-24 | Energy Conversion Devices, Inc. | Method of making a high performance, small area thin film transistor |
US20120161330A1 (en) * | 2010-12-22 | 2012-06-28 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140374919A1 (en) * | 2013-06-24 | 2014-12-25 | Imec | Method for Producing Contact Areas on a Semiconductor Substrate |
US10332850B2 (en) * | 2013-06-24 | 2019-06-25 | Imec | Method for producing contact areas on a semiconductor substrate |
CN111526666A (en) * | 2020-04-30 | 2020-08-11 | 生益电子股份有限公司 | PCB manufacturing method |
DE102021209939A1 (en) | 2021-09-08 | 2023-03-09 | Gebr. Schmid Gmbh | Printed Circuit Board Manufacturing Process and Printed Circuit Board |
Also Published As
Publication number | Publication date |
---|---|
KR20140021914A (en) | 2014-02-21 |
JP2014039032A (en) | 2014-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2010135721A (en) | Printed circuit board comprising metal bump and method of manufacturing the same | |
JP2007324559A (en) | Multilayer circuit board with fine pitch and fabricating method thereof | |
US7919408B2 (en) | Methods for fabricating fine line/space (FLS) routing in high density interconnect (HDI) substrates | |
KR20160070588A (en) | Embedded printed circuit board and method of manufacturing the same | |
US20140034359A1 (en) | Printed circuit board and method of manufacturing printed circuit board | |
JP2007012854A (en) | Semiconductor chip and its manufacturing method | |
US20150373833A1 (en) | Printed circuit board and method of manufacturing the same | |
JP2009283739A (en) | Wiring substrate and production method thereof | |
KR101831643B1 (en) | Package substrate comprising surface interconnect and cavity comprising electroless fill | |
JP2016042543A (en) | Method for forming circuit board | |
KR101063519B1 (en) | Method for manufacturing copper bumps of fine pitch | |
KR20150102504A (en) | Embedded board and method of manufacturing the same | |
US20110000083A1 (en) | Method of manufacturing printed circuit board having metal bump | |
KR101474642B1 (en) | Printed circuit board and method of manufacturing the same | |
US20140042122A1 (en) | Method of manufacturing printed circuit board | |
JP2011187913A (en) | Electronic element incorporation type printed circuit board, and method of manufacturing the same | |
JP2015043408A (en) | Printed circuit board and manufacturing method of the same | |
US20150083480A1 (en) | Interposer board and method of manufacturing the same | |
KR101039774B1 (en) | Bump Formation Method for Printed Circuit Board Manufacturing | |
KR101582547B1 (en) | Semiconductor package with semiconductor chip embedded therein and method for manufacturing the same | |
US20150195902A1 (en) | Printed circuit board and method of manufacturing the same | |
US20090294979A1 (en) | Semiconductor substrate and method of manufacturing the same | |
KR101044106B1 (en) | Landless Printed Circuit Board and Manufacturing Method Thereof | |
US20150129291A1 (en) | Printed circuit board and method of manufacturing printed circuit board | |
KR100576652B1 (en) | Manufacturing method of double sided wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRO-MECHANICS CO., LTD., KOREA, REPUBL Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JUNG, JAE MOK;KIM, MIN SOO;SONG, HUN JUNE;AND OTHERS;SIGNING DATES FROM 20130806 TO 20130808;REEL/FRAME:030988/0710 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |