JPH0452880A - Line plotting address generating circuit - Google Patents

Abstract

PURPOSE:To simplify control and to make it possible to apply the line plotting address generating circuit also to a different address map by applying a prescribed mask to the address next to an address to be formed to form the address concerned and latching and outputting a physical address by a clock pulse generated by monitoring an address change. CONSTITUTION:An X address change and a Y address change are respectively calculated by a circuit consisting of a selector 1, a latch circuit 2 and an adder 3 and a circuit consisting of a selector 12, a latch circuit 13 and an adder 14. On the other hand, succeeding X and Y addresses are respectively formed by a circuit consisting of a selector 4, a latch circuit 5 and an adder 6 and a circuit consisting of a selector 9, a latch circuit 10 and an adder 11. Respective AND circuits 7, 8 are respectively masked by an X address mask value 104 and a Y address mask value 108 to form appropriate X and Y addresses. A physical address 111 is latched and outputted by an OR circuit 15 and a latch circuit 16 in accordance with a clock pulse 110 outputted from a change detecting circuit 17 for outputting the pulse 110 in each address change. Thus, the line plotting address generating circuit whose control is simplified can be obtained by using similar hardwares.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line drawing address generation circuit that is used to generate addresses for a memory, and particularly relates to a line drawing address generation circuit when one address space corresponds to a two-dimensional plane.

〔overview〕

The present invention provides a line drawing address generation circuit that generates an address for drawing a line on a two-dimensional plane. An address is generated, a predetermined mask is applied to the next generated address to generate an address, the generated X address and Y address are logically summed as a physical address, and the change in the address is monitored. generate a clock pulse,
By latching and outputting the physical address using this clock pulse, control is simplified and the system can be applied to different address maps.

[Conventional technology]

Conventionally, a line drawing address generation circuit for a memory having a two-dimensional address map as shown in FIG. A selector 18 to select, a latch circuit 19 that holds the output of the selector 18 using a clock pulse 114, and an adder 2 that adds the output of the latch circuit 19 and the X address change amount 113 to generate the next X address.
0, Y at 1/s initial value 115, and the output of the adder 23 to select one of them; a latch circuit 22 that holds the output of the selector 21 with a clock pulse 117; and an adder 23 that adds the output of 1 and the Y address change amount 11B to generate the next Y address.

The selector 18 is for selecting whether to hold the initial X address value 112 in the latch circuit 19 or to hold the next X address generated by the adder 20 in the latch circuit 19, and the starting point of the straight line is It is given to the X address initial value 112 and held in the latch circuit 19.

Adder 20 adds address change amount 113 to the current X address, which is the output of latch circuit 19, to generate the next X address. The selector 21 has a Y address initial value of 115.
This is to select whether to hold the next Y address in the latch circuit 22 or to hold the next Y address generated by the adder 23 in the launch circuit 22, and the starting point of the straight line is given to the initial Y address value 115 and the latch circuit 22 to be held. The adder 23 adds the Y address change amount to the current Y address, which is the output of the latch circuit 22, to generate the next Y address. A physical memory address is obtained by combining the X address (K bit) from the latch circuit I9 and the Y address (L bit) from the latch circuit 22 as upper and lower (it is arbitrary to decide which is upper or lower). generate.

This conventional line drawing address generation circuit sets the starting point of a straight line to
Address initial value 112 and Y address initial value 115
The slope of the straight line is given as the amount of change in the X address (ΔXH1
, 3 and Y address change amount (ΔY) 116, ΔY
/ΔX.

[Problem to be solved by the invention]

In this conventional line drawing address generation circuit, the smaller address variation is set to "1", and the X address variation is set to 11.
It is necessary to always apply the smaller clock pulse of 3 and the Y address change amount 116, and to thin out the larger clock pulse according to the value of the slope (ΔY/ΔX).

For example, in the case of △Y/ΔX=5, if clock pulses are applied at the same time, the amount of change in the X address 113 is [l, but the amount of change in the Y address], 1
Since fi is 5, unless one clock pulse is applied to the Y address for five clock pulses to the X address, a continuous straight line will not be obtained and the line will be missing. If the slope is 1/2≦ΔY/△X≦2, both the X address change 1113 and the Y address change amount 116 are set to “1”, and the cycles of the clock pulses 114 and 117 are controlled. A continuous straight line cannot be obtained unless the slope is controlled. Therefore, it is necessary to control the frequency of the clock pulse 114 and the clock pulse 117 to control the slope.
It had the disadvantage of being extremely complex.

Also, when generating addresses for curves such as quadratic curves,
Since it is necessary to sequentially change the address change amount 113, the Y address change amount 116, and the clock pulses 114 and 117 in accordance with the current X address and Y address, external control becomes extremely complicated and practical. It had some unreasonable flaws.

Furthermore, when generating the physical address 118, the bits on the X address and the bits on the Y address are physically matched, so when changing the address map on a two-dimensional plane, the hardware must be changed. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-dimensional plane line drawing address generation circuit which is easy to control and does not require changing the hardware when the address map changes, by eliminating the above-mentioned drawbacks. .

[Means to solve the problem]

The present invention provides a line drawing address generation circuit equipped with a means for generating an address for drawing a line on a two-dimensional plane. X address change calculation means and Y address change calculation means that calculate the change and Y address change, and add the current X address and Y address and the calculated X address change and Y address change, respectively. and next X
The first X that generates the address and Y address respectively
an address generation means and a first Y address generation means;
a second X-address generating means for masking the generated next X-address and Y-address with an X-address mask value and a Y-address mask value, respectively, to respectively generate X-addresses and Y-addresses suitable for a two-dimensional planar address map; a second Y address generation means, a physical address generation means for generating a physical address from the generated X address and Y address, and monitoring the calculated X address change amount and Y address change amount, and detects a change in the address. The present invention is characterized in that it includes address change detection means that outputs a clock pulse every time the physical address is output, and address output means that latches and outputs the physical address in accordance with the output clock pulse.

[Effect]

The X address change amount calculation means and the Y address change amount calculation means calculate the X address change amount and the Y address change amount using the first and second order differential coefficients of the respective address change amounts. First X address generation means and first Y
The address generating means adds the current address and the calculated address change amount to generate the next X address and Y address. The second X address generation means and the second Y address generation means apply a predetermined mask to the generated next address to generate an X address and a Y address that match the target map. The physical address generating means generates a physical address by, for example, taking the logical sum of the previously generated X address and Y address. The change detection means monitors the address change and outputs a clock pulse every time the address changes. The address output means latches and outputs the physical address in accordance with this clock pulse.

Therefore, regardless of the amount of address change (ΔY/ΔX), there will be no gap in the line segment, and for example, even in the case of a quadratic curve, it is only necessary to give the address change first and second derivative coefficients, making it easy to control. You will be able to do this.

Furthermore, it is only necessary to change the setting of the address mask value for different address maps, and there is no need to change the hardware.

〔Example〕

Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is a line drawing address generation circuit equipped with a means for generating an address for drawing a line on a two-dimensional plane. 102
and 106 and change second derivative coefficients 103 and 1
X address change calculation means and X address change amount calculation means for calculating the X address change amount and the
Selector 1, latch circuit 2 and adder 3 as address change calculation means, selector 12, latch circuit 13 and adder 14, and current X address and
A selector as a first X-address generation means and a first X-address generation means that add the address and the calculated X-address variation and X-address variation to generate the next X-address and X-address, respectively. 4, latch circuit 5, adder 6, and selector 9
, a latch circuit 10 and an adder 11, and mask the generated next X address and X address with an X address mask value 104 and an X address mask value 108, respectively, to create an and AND circuits 7 and 8 as second X address generation means and second X address generation means for respectively generating the X address and Y'
An OR circuit 15 as a physical address generation means that generates an address or a physical address 111, and an address change detection unit that monitors the calculated X address change amount and the X address change amount and outputs a tarok pulse 110 every time the address changes. It is provided with a change detection circuit 17 as a means, and a latch circuit 16 as an address output means for latching and outputting the physical address 111 according to the output clock pulse 110.

Then, selector 1 has X address change 1 blowing differential coefficient 1
02 and the output of the adder 3 are manually input, and the X address change two-stroke differential coefficient 103 and the output of the latch circuit 2 are input manually to the adder 3. Further, the X address initial value 101 and the output of the adder 6 are input to the selector 4, and the output of the adder 3 and the output of the latch circuit 5 are input to the adder 6. Here, selectors 1 and 4, latch circuits 2 and 5, adders 3 and 6, and AND circuit 7 constitute X address generation section 24.

Similarly, the Y address change 1st differential coefficient 106 and the output of the adder 14 are input to the selector 12, and the Y address change 2nd differential coefficient 107 and the latch circuit 13 are input to the adder 14.
The output is human-powered. Further, the selector 9 is input with the X address initial value 105 and the output of the adder 11, the adder 11 is input with the output of the adder 14 and the output of the launch circuit 10, and the adder 11 is input with the output of the adder 14 and the output of the launch circuit 10. 14 and the output of the latch circuit 10 are manually input.

Here, the selectors 9 and 12, the latch circuits 10 and 13, the adders 11 and 14, and the AND circuit 8 constitute a Y address generation section 25.

Furthermore, the same clock pulse 109 is input to each of the latch circuits 2.5.10 and 13.

Next, the operation of this embodiment will be explained.

The selector 1 selects the X address change one-time differential coefficient (■ bit) 102 and the current X address change, and the latch circuit 2 holds the change. Adder 3 includes X address change 2-blow differential coefficient (I-pi)) 103 and latch circuit 2
and the output of the next X address change (ebit)
generate. The selector 4 selects the initial X address value 101 of the starting point of the line segment and the X address from the adder 6, and the latch circuit 5 holds the output of the selector 4. Adder 6
adds the current X address (M+I bits) and the change in X address of the adder 3 output ((■ bits)) to generate the next X address (M+1 bits).

Only the upper M bits actually become the X address.

FIG. 3 shows the relationship between the M bit and the I bit. Third
In the figure, the part with parentheses indicates the Y address generation section 25. The LSBs of the X address change (■ bit) and the X address internal operation (M+If need) are of the same digit, and only the upper M bits of the M+I bits constitute the actual address.

Since the X address change 1-stroke differential coefficient 102 and the second-order differential coefficient 103 are set up to ■ bits below the decimal point, a fine slope (ΔY/ΔX) of the line segment can be set. The AND circuit 7 masks the upper bits with the X address mask value 104 in order to make the upper M bits of the internal operation of the X address (M+I bits) the number of bits of the X address.

X address generation section 24 and Y address generation section 25 in FIG.
has a similar function, the selector 12 selects the Y address change 1 blow differential coefficient (J-pi)) 106 and the current X address change, and the latch circuit 13 outputs the output of the selector 12 which is the change. Hold. The adder 14 has a Y address change 2-stroke differential coefficient (J focus) 107 and a latch circuit 1.
3 is added to generate the next X address change (J bits). The selector 9 selects the initial Y address value 105 of the starting point of the line segment and the Y address from the adder 11, and the latch circuit 10 holds the output of the selector 9. The adder 11 adds the current Y address and the change in the X address (J bits) of the output of the adder 14 to generate the next Y address (N+J bits). AND circuit 8 is
In order to make the upper N bits of the Y address internal calculation (N+J bits) equal to the bit number of the Y address, the upper bits are masked by the Y address mask value 108.

The OR circuit 15 generates one physical address (K and L bits) using the X address and Y address obtained by the AND circuits 7 and 8 as an upper address and a lower address. Then, the output of the OR circuit 15 is transferred to the latch circuit 16.
is held and output. The clock for the latch circuit 16 is the output of the change detection circuit 17. The change detection circuit 17 is
The X address change amount which is the output of the adder 3 of the X address generation section 24 is compared with the X address change amount which is the output of the adder 14 of the Y address generation section 25, and the AND circuit 7 or 8, and outputs a clock pulse 110 when the address changes.

Therefore, the starting point of the line segment is set to the initial value of X address 101 and Y
Given as the address initial value 105, the initial slope of the line segment (
ΔY/ΔX) is set as the X address change 1st differential coefficient 102 and the Y address change 1st differential coefficient 106, and in the case of a curve, give the X address change 2nd differential coefficient 103 and the Y address change 2nd differential coefficient 107. This allows you to draw any line segment.

In the case of a straight line, X and Y address change 2 blowing differential coefficient 1
Both 03 and 107 are set to 0.

As explained above, in this example, the slope of the line segment (ΔY/
ΔX) is given as the decimal point of the actual address as the X address change and the X address change, and the address is automatically latched every time the address with the larger address change changes. By applying the same clock pulse 109 to each of the latch circuits 2, 5, 10 and 13 regardless of the magnitude of the clock pulse 109, the line segment does not become missing, and control is very simple.

Furthermore, even when a quadratic curve address is generated, it is only necessary to give the X address change two-stroke differential coefficient and the Y address change two-stroke differential coefficient, and the control is very simple.

Furthermore, since the physical address is generated from the X address and the Y address using an OR circuit, it is possible to handle two-dimensional planes with different address maps by simply setting the X address mask value and the Y address mask value. Identical hardware can be used.

〔Effect of the invention〕

As explained above, according to the present invention, the line segment does not become missing regardless of the slope of the line segment, and the address of the quadratic curve also gives the X, Y address quadratic differential coefficient. In addition, the same hardware can be used for two-dimensional planes with different address maps to realize a line drawing address generation circuit that is extremely easy to control by simply setting the X and Y address mask values. It can be done and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an address map on a two-dimensional plane. FIG. 3 is a bit correspondence diagram of the X address generation section and the Y address generation section. FIG. 4 is a block diagram showing a conventional example. 1.4.9.12.1.8.21...Selector, 2.
5.10.13.16.19.22...Latch circuit,
3.6.11.14.20.23...Adder, 7.8
...AND circuit, 15-...OR circuit, 17...change detection circuit, 24...X address raw acid section, 25...
Y address generation unit, 101.112...X address initial value, 102...X address change 1-stroke differential coefficient, 10
3...X address change 2-stroke differential coefficient, 104...X address mask value, 105.115...Y address initial value, 106...Y address change 1-stroke differential coefficient, 107
...Y address change 2-stroke differential coefficient, 108...Y address mask value, 109.110.114.117...
- Clock pulse, 111.118...Physical address, 113...X address change amount, 116...X address change amount.

Claims (1)

[Scope of Claim] A line drawing address generation circuit equipped with means for generating an address for drawing a line on a one- or two-dimensional plane, comprising: a first-order differential coefficient of change and a second-order differential coefficient of change of an X address and a Y address; X address change amount calculation means and Y address change amount calculation means for calculating the X address change amount and Y address change amount, respectively, and the current X address and Y address and the calculated X address.
a first X address generating means and a first Y address generating means for generating the next X address and Y address, respectively, by adding the address change amount and the Y address change amount, respectively; and the generated next X address. and a second X address generation means and a second Y address generation means for respectively masking the Y address with an X address mask value and a Y address mask value and respectively generating an X address and a Y address suitable for a two-dimensional planar address map. , physical address generation means for generating a physical address from the generated X address and Y address, and monitoring the calculated X address change amount and Y address change amount and outputs a clock pulse every time the address changes. A line drawing address generation circuit comprising: address change detection means; and address output means for latching and outputting the physical address in accordance with the output clock pulse.