JPH0449198B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit, and particularly to a semiconductor memory that achieves a sufficiently small average operating current.

An example of a conventional memory circuit will be explained with reference to FIGS. 1 to 3. First, FIG. 1 will be briefly explained. Address input signal Ai, chip enable input signal CE, and data input signal Din write enable signal WB are input to input buffer 101, respectively. From the buffered signals Ai′,i′,
A desired memory cell is selected by address decoder 102 and Y address decoder 103. The Din control unit 104 and the Dout control unit 106 control data writing and reading, respectively. Second
The figure shows a memory cell matrix section 105. A memory cell 109 is arranged at each intersection of a plurality of word lines and a plurality of bit lines. Here, the memory cell 109 is assumed to be a 6-transistor cell having a CMOS structure as shown in FIG.

Next, the operation of memory cell matrix section 105 will be explained. First, when the memory circuit is selected, that is, when the chip enable input signal CE is at a high level, only one
Only the word line of a row and the bit line of only one column are selected. A concrete explanation is as follows.
First, among the plurality of X decoder outputs, that is, the plurality of word lines, only one row becomes high level, and only the memory cells connected to this selected word line can transmit data with the bit line. Next, only one of the plurality of Y decoder outputs becomes high level, and as a result, the plurality of Y switch circuits 1
Only one of 08 becomes conductive, and the selected bit line connected to the selected Y switch circuit 108 and the Din control section 104, or the selected bit line and the sense amplifier to the Dout control section 106
It becomes possible to transmit data between Therefore, of the memory cells connected to the selected word line, reading or writing can be performed to only the memory cell connected to the selected bit line, that is, only one memory cell.

In addition, in FIG. 2, the mutual conductance gmp of the P channel transistor Q101 (or Q102) at the end of the bit line is equal to the mutual conductance of the N channel transistor Q103 or Q104 of the Y switch circuit 108 in order to facilitate the write operation. It is assumed that it is designed to be sufficiently smaller than gms. Further, it is assumed that the gmp is set to have an appropriate ratio to the respective mutual conductances gmt and gmd of the N-channel transistors Q111, Q113 or Q112, Q114 in the memory cell. The ratio is determined based on the speed of reading data from the memory cell to the bit line and the stability of the memory cell having the circuit configuration shown in FIG.

FIG. 4 shows waveforms at various parts during a read operation in this conventional example. The address input signal Ai switches, then the chip enable input signal CE rises, the X decoder operates, the word line WL switches, and the memory cell that can perform data transmission with the bit line changes, so the bit line BL , the data on BL is also switched. Then, the Y decoder output is switched, and the read data is transmitted to the data bus lines DB, DB. From FIG. 4, it can be seen that one of the bit lines BL, BL shows a waveform toward Vcc, and the other shows a waveform toward an intermediate level. However, this intermediate level is determined by the P channel transistor Q101 or Q1 at the end of the bit line.
02 and the mutual conductance of each of the N-channel transistors Q111, Q113 or Q112, Q114 in the memory cell,
In this case, Q101→Q111→Q113 or Q
A through current flows through the path 102→Q112→Q114. Incidentally, this through current flows in the same manner to all bit lines, and occupies a large proportion of the average operating current. For example, in a memory circuit having 128 columns of bit lines, if a through current of approximately 200 .mu.A flows per bit line column, the total through current will be approximately 25.6 mA. The through current of the unselected bit line is not a current necessary for the read operation, so it is better to keep it as small as possible. In this conventional example, in order to reduce the through current, the mutual conductance gmp, gmt,
gmd to a pre-designed ratio gmp:gmt:gmd
must be made smaller without changing. However, as gmt and gmd become smaller, the data reading speed from the memory cell to the bit line becomes slower. As described above, in a memory circuit configured as in this conventional example, an unnecessarily large through current flowing from the P-channel transistor at the end of the bit line to the memory cell during a read operation cannot be avoided, and therefore the average operating current It also had the disadvantage of becoming larger.

An object of the present invention is to suppress the through current as much as possible by keeping the selected word line at a high level for a certain period of time during a read operation, and setting the selected word line to a low level after data latch is completed.
Achieve a sufficiently small average operating current. The purpose is to provide memory circuits.

The memory circuit according to the first aspect of the invention comprises:
In a memory circuit having a memory cell consisting of a storage element and a transfer gate arranged between the storage element and a bit line, means for latching read data, means for detecting latch completion, and a latch completion detection signal are provided. The invention is characterized in that it also includes means for blocking the transfer gate.

Alternatively, a memory circuit according to a second aspect of the present invention is characterized in that a resistor is disposed between the bit line and the power supply in the memory circuit.

Alternatively, a memory circuit according to a third aspect of the present invention includes, in the memory circuit of the first aspect,
The present invention is characterized by comprising means for precharging the bit line.

Alternatively, a memory circuit according to a fourth aspect of the present invention is a memory circuit according to the first, second, or third aspect, in which the memory element is connected to one input of two inverters to the other. The flip-flop circuit is connected to the outputs of the flip-flop circuit.

A first embodiment of the present invention is shown in FIGS. 5 and 6. First, the configuration of the memory circuit according to this embodiment will be briefly explained with reference to FIG. 5 which is a block diagram. This embodiment is a memory circuit in which a data latch section 301, a latch completion detection section 302, and a word line control section 303 are added to the conventional example. Therefore,
Input buffer, address decoder, Din and Dout
The operation of the control section is similar to that of the conventional example. The data latch section 301 latches read data. A latch completion detection section 302 detects the completion of the latch and generates a word line activation signal φx.
The word line control unit 302 outputs a signal Wi that is in phase with the output Xi of the X decoder 102 only during the period when φx is at a high level.

FIG. 6 shows a logic circuit diagram of the data latch section 301, the latch completion detection section 302, and the word line control section 303. The data latch section 301 includes transfer gates Q301 and Q302, and a delay circuit 30.
4, a flip-flop 305. First, after the chip enable buffer signal CE' rises,
Read data on data bus line DB, amplified by sense amplifier 107, is transferred onto latch bus line LB by transfer gates Q301 and Q302. On the other hand, said
After a required period of time has passed in the delay circuit 304 after CE' rises, the flip-flop 305 is activated, and at the same time, the transfer gates Q301 and Q3 are activated.
02 is blocked. At this time, flip-flop 3
05 latches the read data on the latch bus lines LB, LB. The latch completion detection unit 302 lowers the word line activation signal φx, which is the NAND output of the latch bus line LB, when at least one of the potentials on the latch bus line LB becomes low level. The word line control unit 303 uses the φx to control the rise and fall of the word line selected in advance by the X decoder 302.

FIG. 7 shows waveforms at various parts during the read operation of this embodiment. Like FIG. 4, FIG. 7 takes address access as an example. The address output signal Aj is switched, the chip enable input signal CE rises, and the X decoder output Xi and the Y decoder output Yj are switched by the rise of the chip enable buffer signal CE'. On the other hand, said
The word line activation signal φX is activated by the rising edge of CE′.
rises, and therefore the word line signal Wi rises. As a result, only one word line is selected, ie, goes high, and the data of the memory cell connected to that word line appears on the bit line. Then, according to the Y decoder output Yj that has already been determined, only one sense amplifier is activated, and the data on the bit line connected to the sense amplifier is transmitted to the data bus line DB, and then to the transfer gate. Q301, Q30
2 to the latch bus line LB.
Then, after the required time has elapsed, the flip-flop 30
5 is activated and latches the data on the LB. On the other hand, at approximately the same time, the latch completion detection section 302 detects a change in the voltage levels of LB and LB, and the φx falls, and furthermore, the word line signal Wi falls. As a result, the transfer gate in the memory is cut off, and the through current flowing from the P-channel transistor at the end of the bit line to the memory cell is also cut off. Then, both bit lines BL and BL go to the Vu level.

As is clear from the above explanation, in this embodiment, the through current that flows from the P-channel transistor at the end of the bit line to the memory cell only flows for a certain period when the word line is at a high level during reading. . On the other hand, in the conventional example, as already explained, the through current flows constantly, making the average operating current unnecessarily large. That is, this embodiment has the drawbacks of the conventional example. This has a great advantage in that the unnecessarily large through current flowing through the memory cell can be sufficiently suppressed. If the address cycle time is 1000nsce and the period when the word line is at high level is 20nsce, then
The average value of the through current is extremely small, 2% of the conventional example. For example, the average value, which was 25.6 mA in the conventional example, becomes 25.6×0.02=0.5 mA by adopting this embodiment.

A second embodiment of the invention is shown in FIG.

This embodiment is a memory circuit in which the memory cell matrix section 105 in the first embodiment is replaced with a memory cell matrix section 501 shown in FIG.

FIG. 9 shows waveforms at various parts during the read operation of this embodiment. The read operation waveforms in FIG. 9, like FIGS. 4 and 7, take address access as an example.

This embodiment differs from the first embodiment in that the bleach charge circuit 502 is in a cutoff state when the word line signal Wi is at a high level.
With such a configuration, there is no need to consider the mutual conductance ratio gmp:gmt:gmd described in the conventional example, which facilitates circuit design and increases margin against manufacturing variations.

As described above, the present invention makes it possible to sufficiently reduce the average operating current by keeping the selected word line at a high level for a predetermined period of time, and by setting the selected word line to a low level after data sensing is completed. This realizes a memory circuit. Note that each of the above embodiments is an example in which the present invention is applied to a memory circuit with a CMOS configuration, but a memory circuit with an NMOS configuration,
The present invention can also be applied to NMOS-CMOS hybrid memory circuits. It goes without saying that various other application examples that satisfy the gist of the present invention are possible.

[Brief explanation of drawings]

1 to 3 are circuit diagrams showing a conventional memory circuit, FIG. 4 is a signal waveform diagram showing its read operation, and FIGS. 5 to 6 are circuit diagrams showing a first embodiment of the present invention. 7 is a signal waveform diagram showing the read operation, FIG. 8 is a circuit diagram showing a second embodiment of the present invention, and FIG. 9 is a signal waveform diagram showing the read operation. 101...Input buffer, 102...X address decoder section, 103...Y address decoder section, 104...Din control section, 105...Memory cell matrix section, 106...Dout control section, 1
07...Sense amplifier, 108...Y switch circuit, 109...Memory cell, 301...Data latch section, 302...Latch completion detection section, 303...
...Word line control unit, 304...Delay circuit, 305
...Flip-flop, 501...Memory cell matrix section, 502...Precharge circuit, 5
03...Delay circuit, 201, 4010601...
Address input signal Ai, 202, 402, 602
...Chip enable input signal CE, 203,4
03,603...Chip enable input buffer signal CE', 204,404,604...X decoder output (selection), 205,405,605...X
Decoder output (unselected), 206, 406, 60
6...Y decoder output (selection), 207, 407,
607...Y decoder output (non-selected), 408,
608...Word line activation signal φx, 409,6
09...Word line signal Wi (selection), 208, 41
0,610...Bit line BL, 209,411,
611...Bit line BL, 210, 412, 61
2...Data bus line DB, 211, 413, 61
3...Data bus line DB, 414,614...Latch bus line LB, 415,615...Latch bus line LB.

Claims (1)

[Claims] 1. A memory cell consisting of a storage element and a first transfer gate arranged between the storage element and each pair of bit lines, controlled by a word line, and rendered conductive when the word line is selected. A memory circuit having a data bus, a sense amplifier provided for each pair of bit lines and selectively amplifying and transmitting the read data of the memory cells to the data bus, a data latch flip-flop, and the data bus. a second transfer gate that transmits read data transmitted to the data latch flip-flop to the data latch flip-flop; and a second transfer gate that changes the second transfer gate from a conductive state to a non-conductive state after a predetermined delay time after the chip enable signal is activated. control means for changing the data latch flip-flop from an inactive state to an active state at the same time as the data latch is set; means for generating a latch completion detection signal when data latching in the flip-flop is completed; 1. A memory circuit comprising means for setting a word line in a non-selected state.