JPH0448778A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology for reducing clock skew in a gate array and realizing high-speed LSI as a result. This paper relates to a technique useful for gate arrays called the packing method.

[Conventional technology]

Figure 3 is based on the document “IEICE Technical Research Report ■LD89
FIG. 103 is a pattern diagram showing an example of realizing clock distribution in a conventional gate array shown in "Pages 47 to 52 of 103.

In FIG. 3, A is a clock input terminal into which external clock signal a is input, 2 is a clock driver, 3 is a clock receiver, and 4 is a receiver/driver connection that connects the output of clock receiver 3 and the input of clock driver 2. The wiring and IC are connected to the output of the clock driver 2 using a clock signal line made of second layer metal that is thicker than the normal signal wiring,
IA is a clock signal line made of first layer metal connected to the clock signal 11c via a through hole, IB is a clock signal line made of second layer metal connected to clock signal line IA via a through hole, and ID is a clock signal line. signal, %i
1B is a clock branch line made of first layer metal wiring connected to IC via a through hole, IE is a clock signal line made of second layer metal wiring connected from clock branch line ID via a through hole, 5a is a flip-flop. 5b is a combinational circuit, 6 is a second layer power supply wiring made of a second layer metal that supplies power to the areas of internal cells 5a and 5b, and 7 is a sequential circuit such as
is the input/output buffer area. The above clock signal line IA
and IB constitute a ring-shaped wiring, and the clock signal mlE
connects the clock support T/1AID and the input/output terminal of the sequential circuit 5a. Further, the clock signal lines IA and IB, the clock signal line IC, the clock branch line ID, and the clock signal *IE constitute a clock signal wiring.

Next, the wiring method and operation of a conventional semiconductor integrated circuit device will be explained. In the semiconductor integrated circuit device shown in FIG. 3, the clock signal! IB,
Wire the IC in advance.

MIa for wiring the clock signals wAIB, IC: is treated as an internal gate and second layer power wiring prohibited area in the wiring program, so that it does not affect the wiring of normal signal lines by the wiring program. In addition, for the wiring of the clock signal line IA, a wiring area is secured in advance inscribed in the input/output buffer area 7, and it is treated as an area where internal cell placement is prohibited and signal wiring due to the first layer metal is prohibited. The clock support 111 does not affect the wiring of the signal line.
D needs to be thicker than normal signal lines to suppress skew, but the number of clock signal lines IB and IC must be equal to the number of internal cell rows to be placed in the first layer signal wiring channel.
Wiring to connect can be easily done using current commercially available layout tools. Also,
The connection between the clock signal line IE and the sequential circuit 5a can also be easily made using a commercially available layout tool.

In this way, a large number of sequential circuits 5a can be driven at once by the clock driver 2 without a special program for clock signal wiring, so it is possible to reduce the skew of the clock signal. That is, since each clock signal line is arranged in a mensch shape, the resistance from the clock driver to the sequential circuit is reduced, and the skew of the clock signal is reduced.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit device is configured as described above, and since it always requires one clock branch line in each column in which a macro cell is arranged, there are the following problems.

■Clock branch lines are also wired for macrocell columns that do not have sequential circuits.

(2) In a structure such as SOG (Sea-of-Gate), the number of macrocell columns varies depending on the user's circuit, so the performance of the clock distribution cell varies depending on the user's circuit.

■As chips become more highly integrated, the number of macrocell rows also increases.
For example, if the number of sequential circuits to be driven is 2000, the load capacitance is 100 pF, and the capacitance of the clock branch line alone is 2.
It reaches 00 pF or more and becomes a major cause of delay in the rise time, fall time and phase difference of the clock signal.

The present invention has been made in view of these points, and its purpose is to address the following points in a mask slice type gate array.

1) There is little variation in the performance of the clock distribution cell even if slices are different for one mask.

ii) Rising/falling characteristics, phase difference, skew, etc. can be reduced.

ii) By reducing the load capacity of the clock distribution circuit, charging and discharging current can be reduced, resulting in low noise, low power consumption,
It is possible to realize a highly reliable LSI.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a clock receiver that receives an external clock signal, and at least one clock driver that receives the output of the clock receiver and drives a sequential circuit. , a clock signal wiring for connecting the output of this clock driver to a sequential circuit, and a plurality of sequential circuits connected to the clock signal wiring, and the clock signal wiring is connected adjacent to the inner circumference of the input/output buffer area. A ring-shaped wiring consisting of a third-layer metal wiring and a second-layer metal wiring, which run adjacent to and parallel to the second-layer power wiring arranged in the internal cell area, and connected to the output terminal of the clock driver. and at least one second-layer metal wiring connected to the ring-shaped wiring, and at least one third-layer metal clock branch line connected to the second-layer metal wiring and the ring-shaped wiring. , the clock signal wiring is arranged in a grid pattern.

[Effect]

In the semiconductor integrated circuit device according to the present invention, the clock branch lines in the third layer can be provided as slice cells in advance without being affected by the arrangement of macro cells, so there is no need to unnecessarily increase the number of clock branch lines (load capacity, etc.). By reducing this, it becomes possible to achieve higher speed, higher reliability, and lower power consumption.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a logic diagram showing the logic of clock signals in the semiconductor integrated circuit device according to the present invention. Clock signal line 1
has many branches, and the clock signal is driven by two clock drivers 2. The external clock signal a is input to the clock receiver 3, and the output of the clock receiver 3 is supplied to the clock driver 2 via the receiver/driver connection wiring 4.

FIG. 1 is a pattern diagram showing a semiconductor integrated circuit device as an embodiment of the present invention that realizes the clock signal logic diagram shown in FIG. In FIG. 1, A is a clock input terminal into which an external clock signal a is input, 2 is a clock driver, 3 is a clock receiver, and 4 is a clock receiver 3.
The receiver/driver connection wiring connects the output of the clock driver 2 to the input of the clock driver 2, the IC is a clock signal line made of second layer metal that is thicker than the normal signal wiring connected to the output of the clock driver 2, and the IA is connected to the clock signal line 1c. A clock signal line made of third layer metal is connected via a through hole, IB is a clock signal line made of second layer metal connected to clock signal mlA via a through hole, and ID is a clock signal line made of second layer metal connected to clock signal 11BIC via a through hole. 5a is a sequential circuit such as a flip-flop, and 5b is a combination. circuit, 6 is an internal cell 5a,
A second layer power supply wiring made of a second layer metal supplies power to a region 5b, and a human output buffer region 7. The clock signal lines IA and IB constitute a ring-shaped wiring, and the clock signal WIE connects the black branch line ID and the input/output terminal of the sequential circuit 5a. In addition, the clock signal lines IA and 1B
, clock signal 1! The IC, clock branch line ID, and clock signal &IIE constitute a black signal line.

Next, the wiring method and operation of the embodiment of the present invention will be explained. In the semiconductor integrated circuit device shown in FIG.
Similarly to the layer power supply wiring 6, the clock signal lines IB and IC are wired in advance. Since the area where the clock signal lines IB and IC are wired is treated as an internal gate and second layer power wiring prohibited area in the wiring program, it does not affect the wiring of normal signal lines by the wiring program. In addition, since the wiring of the clock signal line IA is made of third layer metal, it is possible to place internal cells (macro cells) below it and to route signals using first and second layer metals. ,
This does not affect normal signal line wiring using the wiring program. The clock branch line ID needs to be thicker than the normal signal line to suppress skew, but it should be wired in advance so that it is connected to the clock signal &ILB and IC using the third layer metal, and integrated with IA, IB and IC. It is easy to overlap those registered as slice cells after arranging the internal cells, and then wire the clock signal line IE made of second layer metal from the clock branch line ID to the sequential circuit 5a using a conventional general software program. It is possible to do so.

In this way, a large number of sequential circuits 5a can be driven at once by the clock driver 2 without a special program for clock signal wiring, so it is possible to reduce the skew of the clock signal. That is, since each clock signal line is arranged in a mesh shape, the resistance from the clock driver to the sequential circuit is reduced, and the skew of the clock signal is reduced.

Furthermore, a third line is added to the clock branch line ID and clock signal line IA.
By using layered metal wiring, it is possible to achieve lower load capacitance and increase speed.

〔Effect of the invention〕

As explained above, according to the present invention, the clock signal wiring can be prepared in advance as a mesoche-like slice cell using the second layer metal and the third layer metal, and then placed and routed. faster clock signals,
It is possible to achieve lower skew, lower power consumption, and higher reliability6

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a logic diagram showing the logic of clock signals in the device of FIG. 1, and FIG. 3 is a pattern diagram showing conventional clock distribution. It is a diagram. A... Black input terminal, IA to IC, IE... Clock signal line, ID... Clock branch line, 2... Clock driver, 3... Clock receiver, 4... Receiver driver Connection wiring, 5a... sequential circuit, 5b
...Combination circuit, 6...Second layer power supply wiring, 7...
I/O buffer area.

Claims (1)

[Claims] a clock receiver that receives an external clock signal, at least one clock driver that receives the output of this clock receiver and drives a sequential circuit described later, a clock signal wiring for connecting the output of this clock driver to the sequential circuit described later, and a clock a plurality of sequential circuits connected to a signal wiring, and the clock signal wiring includes a ring-shaped wiring consisting of a third layer metal wiring and a second layer metal wiring adjacent to the inner periphery of the input/output buffer area; , at least one second-layer metal wiring running adjacent to and parallel to the second-layer power supply wiring disposed in the internal cell region, connected to the output terminal of the clock driver, and connected to the ring-shaped wiring; A semiconductor integrated circuit device comprising the second layer metal wiring and at least one third layer metal clock branch line connected to the ring-shaped wiring and arranged in a grid pattern.