JPH0442612A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To speed up a change in an output signal and to attain excellent level conversion by connecting the gate of a 1st or 2nd element to the gate of a current mirror via a capacitive component. CONSTITUTION:A 1st and a 2nd input signal (at input terminals 1,2) are fed to the gates of 1st and 2nd elements of one polarity (N-channel elements 3,4) respectively and one terminal of each of the 1st and 2nd elements is connected together via a current mirror circuit and the output signal is extracted from the connecting point via an inverter (a P-channel element 8 and an N-channel element 9). In the level conversion circuit formed as above, the gate of the 1st or the 2nd element connecting to the output side element of the current mirror circuit is connected to the connecting point of the gates of the current mirror circuit via a capacitive component (capacitor 11). Thus, a change in the potential of the gate connecting point of the current mirror circuit goes to fast to make a change in the output signal fast, thereby implementing excelling level conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to, for example, TTL (Transistor
O~5 from TransistorLogic) circuit
The v level signal is converted to TPT (Thin Film T
The present invention relates to a level conversion circuit used when converting a signal to a 0-15V level signal of a transistor (transistor) circuit.

[Summary of the Invention] The present invention relates to a level conversion circuit, and a circuit in which one ends of a first and second element to which an input signal is supplied are connected to each other via a current mirror, and an output signal is extracted from this connection point. By connecting the gate of the first or second element to the gate of the current mirror via a capacitive component, the change in the output signal is made faster and good level conversion is performed.

[Conventional technology]

For example, TTL level (0 to 5 V) (D signal
As a circuit for converting into a PT level (0-15■) signal, the applicant of the present application previously proposed a circuit as shown in FIG. 4 (see Japanese Utility Model Application Publication No. 8230/1999).

In the figure, for example, TTL level signals are supplied to the input terminal (IO2) with mutually inverted phases. Signals from these input terminals (1) and (2) are connected to N-type elements (3), respectively.
) (4) and these N-type elements (3
)(4) source is grounded. Furthermore, this N-type element (
The drain of 3) is connected to the TPT level power supply terminal (6) through the P-type element (5) that constitutes the input side (diode) of the current mirror circuit, and the drain of the N-type element (4) is connected to the output of the current mirror circuit. It is connected to a power supply terminal (6) through a P-type element (7) constituting the side (transistor).

For example, the connection point between the N-type element (4) and the P-type element (7) is connected to the output terminal ( 1
0).

Therefore, in this circuit, the input terminals (1) and (2) are connected to TTL levels (0, for example, as shown in FIG.
~V+) is supplied, these signals are supplied to the gates of the N-type elements (3) and (4), thereby forming a P-type element (5) (
A signal as shown by curve C in the figure is formed at the connection point of the gate 7) (where Vthp is the threshold voltage of the P-type element). Therefore, in this circuit, the N-type element (4)
and P-type element (7) operate in a complementary manner, and when element (7) is on, element (4) is off and element (7) is turned on.
) is used to charge the input capacitance of the P-type element (8) and N-type element (9) that constitute the inverter, and when element (4) is on, element (7) is off. Therefore, all of the current flowing through element (4) flows through elements (8) and (9).
is used to discharge the input capacitance of . As a result, a signal that changes at the TPT level (0 to VZ) is formed at the connection midpoint of elements (4) and (7), as shown by curve d in the figure, and this signal is transmitted to elements (8) and (9). The output terminal (10) receives a signal that is in phase with the signal supplied to the input terminal (1) and changes at the TPT level.

[Problem to be solved by the invention]

However, in this circuit, the element (
5) The potential at the connection point of the gate in (7) is affected by g of element (5) and the time constant due to the gate capacitance of element (5) in 7), relative to the input signal shown by curves a and b. It will be a gradual change. For this reason, for example, even if element (4) is turned on, element (7) is not turned off immediately, resulting in a significant time delay in the signal shown by curve d. This is a very serious problem, especially when converting the level of high-speed clock signals and the like.

This application has been made in view of these points, and is intended to enable high-speed changes in output signals with a simple configuration.

[Means to solve the problem]

The present invention provides first and second input signals (input terminals (1), (2),
)) are supplied to the gates of the first and second elements (N-type elements (3) and (4)) of one polarity, respectively, and these first
and connect one end of the second element to another polarity element (P-type element (5
) (7)) are connected to each other via a current mirror circuit to which a second voltage level is supplied (power supply terminal (6)), and an inverter ( P-type element (8), N-type element (9))
In a level converter circuit configured to take out an output signal via an output terminal (10), the gate of the first or second element connected to the output side element of the current mirror circuit is connected to a capacitive component ( This level conversion circuit is characterized in that it is connected to the connection point of the gate of the current mirror circuit via a capacitor (11).

[Effect]

According to this, since an input signal of inverted polarity is supplied to the connection point of the gate of the current mirror circuit via the capacitive component, the potential at this point changes quickly, and the output signal changes quickly. Good level conversion can be performed.

〔Example〕

In Figure 1, the gate of an N-type element (4) connected to the input terminal (2) is connected to the gates of P-type elements (5) and (7) that constitute a current mirror circuit via a capacitor (11). Connected to points. The rest is the same as the circuit described in the prior art section.

As a result, in this circuit, the signal supplied to the input terminal (2) is passed through the P-type element (5) via the capacitor (11).
) (7), and the potential at this connection point changes at the timing of the signal supplied to the input terminal (2).

Therefore, in this circuit, input terminals (1) and (2) have TTL levels (0 to 2) as shown by curves a and b in FIG.
When input signals of V+) are supplied, these signals are connected to the gates of N-type elements (3) and (4) at the connection point of the gates of P-type elements (5) and (7) constituting the current mirror circuit. At the same time, the signal from the input terminal (2) is supplied via the capacitor (11), thereby forming a signal as shown by curve C in the figure (however, Vthp
is the threshold voltage of the P-type element).

These signals cause the N-type element (4) and the P-type element (7) to operate in a complementary manner, so that when element (7) is on, element (4) is turned off and all of the current flowing through element (7) is turned off. It is used to charge the input capacitance of the P-type element (8) and the N-type element (9) that constitute the inverter, and when the element (4) is on, the element (7) is turned off and the element (4)
) is used to discharge the input capacitance of elements (8) and (9). This results in elements (4) (7)
A signal that changes with the TFT level (0 to v2) is formed at the connection midpoint as shown by curve d in the figure, and this signal is inverted by elements (8) and (9) and sent to the output terminal (10). for,
A signal that is in phase with the signal supplied to the input terminal (1) and that changes at the TPT level is taken out.

That is, in this circuit, the change in potential at the connection point of the gates of the P-type elements (5) and (7) constituting the current mirror circuit is sped up by the signal supplied to the input terminal (2), thereby increasing the output signal. Change will occur rapidly.

In this way, according to the above circuit, an input signal of inverted polarity is supplied to the connection point of the gate of the current mirror circuit via the capacitive component, so the potential at this point changes quickly, and the output signal changes quickly. This allows for good level conversion.

In the above circuit, as a guideline for the capacitance value CX of the capacitor (11), assuming that the gate capacitance of the P-type elements (5) (7) is C, , C, □, approximately CX',C9I109□ All you have to do is choose.

Figure 3 shows the actual response characteristics of the circuit described above, obtained through simulation.
For the input signal shown in , the potential change at the connection point of the gate of the current mirror circuit is as shown in curve B, and the potential change at the connection midpoint of elements (4) and (7) is as shown in curve C. Become. On the other hand, the broken lines indicate the case of conventional circuits, and as is clear from the figure, the response characteristics are faster.

Therefore, according to the above-mentioned circuit, when this circuit is applied to a liquid crystal display device, for example, this circuit is made on-chip together with the liquid crystal display panel, and the TT
It becomes possible to perform driving by supplying an L level signal. This eliminates the need for an external drive circuit, etc., making it possible to reduce the power and cost of the device.

Furthermore, the above-mentioned speed increase also enables application to, for example, HDTV signals.

Further, according to the above-mentioned circuit, the margin of fluctuation of the threshold voltage of the N-type elements (3) (4) is increased, and high reliability and high stability of the circuit are achieved.

〔Effect of the invention〕

According to this invention, since an input signal of inverted polarity is supplied to the connection point of the gate of the current mirror circuit via the capacitive component, the potential at this point changes quickly, and the output signal changes quickly. , it is now possible to perform a good level conversion.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of a level conversion circuit according to the present invention;
Figure 2 is a timing chart for explaining this, and Figure 3 is a timing chart diagram for explaining this.
FIG. 4 is a waveform diagram obtained by simulation, FIG. 4 is a configuration diagram of a conventional level conversion circuit, and FIG. 5 is a timing chart for explaining the same. (1) and (2) are input terminals to which, for example, TTL level signals are supplied with mutually inverted phases, and (3) and (4) are N terminals to which signals from these input terminals (1) and (2) are respectively supplied. (5) (7) is a P-type element that constitutes a current mirror circuit, (6) is a TPT level power supply terminal, (8)
(9) is a P-type element forming the inverter, (9) is an N-type element forming the inverter, (10) is an output terminal, and (11) is a capacitor serving as a capacitance component. Agent Hidemori Matsukuma Figure 2

Claims (1)

[Claims] First and second input signals, which are changed at a first voltage level and whose phases are inverted with respect to each other, are supplied to the gates of the first and second elements of one polarity, respectively; 1st and 2nd
One end of each element is connected to each other through a current mirror circuit which is made up of elements of other polarity and is supplied with a second voltage level, and through an inverter which is supplied with the second voltage level from these connection points. In a level conversion circuit configured to take out an output signal, the gate of the first or second element connected to the output side element of the current mirror circuit is connected to the gate of the current mirror circuit via a capacitive component. A level conversion circuit characterized in that it is connected to a point.