JPH0440561U - - Google Patents
Info
- Publication number
- JPH0440561U JPH0440561U JP8152690U JP8152690U JPH0440561U JP H0440561 U JPH0440561 U JP H0440561U JP 8152690 U JP8152690 U JP 8152690U JP 8152690 U JP8152690 U JP 8152690U JP H0440561 U JPH0440561 U JP H0440561U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- ceramic substrate
- substrate
- snap line
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
図は本考案の一実施例を示し、第１図はセラミ
ツク基板の平面図、第２図は要部の断面図、第３
図は基板にベース層をメツキした状態を示す断面
図、第４図は該メツキ層にエツチングを施した状
態を示す要部の断面図、第５図は該ベース層に銅
体をメツキした状態を示す要部の断面図、第６図
はセラミツク基板を分割して一方の回路基板に他
方の回路基板を立設した状態を示す要部の断面図
である。
１……セラミツク基板、２……回路パターン、
３……スナツプライン、４……連結パターン、１
２……回路基板。
The figures show one embodiment of the present invention, in which Fig. 1 is a plan view of a ceramic substrate, Fig. 2 is a sectional view of the main part, and Fig. 3 is a plan view of a ceramic substrate.
The figure is a cross-sectional view showing a base layer plated on the substrate, Figure 4 is a cross-sectional view of the main part showing the plated layer has been etched, and Figure 5 is the base layer plated with a copper body. FIG. 6 is a cross-sectional view of the main part showing a state in which the ceramic substrate is divided and one circuit board is placed upright on the other circuit board. 1...Ceramic substrate, 2...Circuit pattern,
3...Snap line, 4...Connection pattern, 1
2...Circuit board.
Claims (1)
設けると共に、該セラミツク基板を分割するスナ
ツプライン上を通過して対峙した回路パターンを
導通する連結パターンを設け、更に、該スナツプ
ラインにて基板のみを分割し、分割して形成され
た一方の回路基板と他の回路基板とを該連結パタ
ーンにて接続したことを特徴とする回路基板の接
続装置。 A plurality of circuit patterns are provided on one ceramic substrate, and a connecting pattern is provided that passes over a snap line that divides the ceramic substrate and connects the opposing circuit patterns, and further, only the substrate is divided at the snap line, 1. A circuit board connection device, characterized in that one circuit board and another circuit board, which are formed by dividing, are connected by the connection pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8152690U JPH0440561U (en) | 1990-07-31 | 1990-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8152690U JPH0440561U (en) | 1990-07-31 | 1990-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0440561U true JPH0440561U (en) | 1992-04-07 |
Family
ID=31627556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8152690U Pending JPH0440561U (en) | 1990-07-31 | 1990-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0440561U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006148127A (en) * | 2004-11-22 | 2006-06-08 | Valeo Vision | Manufacturing method of support of light emitting diode interconnected in three-dimensional environment |
-
1990
- 1990-07-31 JP JP8152690U patent/JPH0440561U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006148127A (en) * | 2004-11-22 | 2006-06-08 | Valeo Vision | Manufacturing method of support of light emitting diode interconnected in three-dimensional environment |