JPH04372220A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an in-circuit interface of a MOS type integrated circuit.

0002

2. Description of the Related Art Conventionally, when transferring signals between two or more circuit blocks, a signal line or a bus line 3 is used to connect a functional block 1 and a functional block 2, as shown in FIG. , transfer was performed using a signal 4 having a voltage amplitude equal to the power supply voltage of both circuits. For example, if the power supply voltage of both circuits is 5V, the amplitude of the signal line between both circuits is also 5V.
Met.

0003

[Problems to be Solved by the Invention] Day by day, LSIs are becoming more highly integrated and faster. Along with this, power consumption per chip has also increased. Therefore, it is necessary to reduce the power consumption of chips in order to fit them into existing packages or to realize long-term operation using batteries.

For example, when configuring a logic LSI,
There are many bus lines for transferring signals between circuits or between functional blocks. In particular, digital logic LSIs often have a large number of signal lines and occupy a considerable area within the chip. Most of these signal lines or bus lines have long wiring lengths, so
The wiring capacity associated with this is also large. For example, in the case of a video signal processing processor μDSP, the power consumed by the bus line accounts for about 25% of the power consumption of the entire chip. Furthermore, as elements become smaller and scaled, the parasitic capacitance of transistors decreases, but the length of wiring between circuits inside the chip does not decrease, so the proportion of wiring capacitance in the total parasitic capacitance increases. It is expected that. Therefore, the proportion of power consumed when charging and discharging these wirings increases. Therefore, in order to reduce the power consumption of LSIs, it is important to reduce the power consumed by these wirings.

An object of the present invention is to reduce the power consumption of highly integrated LSIs.

[0006]

[Means for Solving the Problems] In order to solve the above problems, power consumption is reduced by lowering the power supply voltage of the entire LSI. However, lowering the power supply voltage also reduces the operating speed of the circuit. Therefore, in the present invention, as shown in FIG. 1, the signal amplitude of the functional circuit portion is set to the same potential as the power supply voltage.
The input/output section of the circuit is equipped with a circuit that has a signal level conversion function. As a result, only the signal amplitude of the signal line between circuits or the bus line that transfers signals between functional blocks can be lowered. As a result, less power is consumed by charging and discharging the signal line or bus line.

However, when a CMOS-configured inverter is used as the level conversion circuit in the output section, the driving ability of the PMOS transistor is significantly reduced when the power supply voltage is low. This is the “Low” level of the input signal and the PM
Because the potential difference between the sources of the OS transistor becomes smaller,
This is because the current driving ability of the PMOS transistor becomes smaller. As a result, the driving ability of the buffer circuit that drives the signal line or bus line is significantly reduced, which impedes high-speed operation of the chip. Therefore, in order to increase the driving ability at a low power supply voltage, a circuit configuration was adopted in which two stages of NMOS transistors were connected in series and a high voltage was applied to the gate of each transistor, as shown in FIG. The circuit of FIG.
When the potential difference between the power supply voltage applied to the drain of the MOS transistor 14 and the "High" level of the gate input signal is larger than the threshold voltage Vth of the NMOS transistor 14, the "High" level of the output rises to the power supply voltage. do. Furthermore, if the gate voltage of the NMOS transistor 14 is high enough, the transistor is strongly “ON”.
Therefore, the driving capacity becomes larger than when using a conventional CMOS inverter.

The circuit configuration of the present invention makes the amplitude of the signal used for signal transfer between circuits lower than the power supply voltage inside the circuit, thereby realizing low power consumption of the entire element. be.

[0009]

[Operation] When the circuit configuration of the present invention shown in FIG. 1 is used, the power consumption of the chip can be reduced compared to the case of the conventional circuit configuration shown in FIG. 2. Here, power consumption can be calculated using equation (1) shown below.

[0010]P=fCV2
...(1) (P: power consumption, f: operating frequency, C: capacitance, V: power supply voltage) For example, when the power supply voltage of the chip is 1.5V, if the signal amplitude of the bus line is reduced to 0.5V, , the power consumed in the bus line is reduced to 1/9 when compared to conventional circuits.

[0011] Also, in the circuit driving the bus line, the circuit shown in FIG.
By using a circuit with high driving ability even at a low power supply voltage as shown in , it is possible to achieve higher speeds than a conventional circuit using a normal CMOS inverter at a low power supply voltage.

0012

Embodiment A first embodiment of the present invention is shown in FIG. FIG. 1 shows a semiconductor integrated circuit having a circuit configuration according to the present invention. Figure 1
In this case, the signal amplitude of the signal line or bus line 3 is smaller than the signal amplitude in the functional block 1 and the functional block 2. That is, a signal 4 having a voltage amplitude equal to the power supply voltage of the circuit in the functional block 1 is converted into a low amplitude signal 5 by the output level conversion circuit 6, and is transferred via the signal line or bus line 3. Furthermore, the low amplitude signal 5 is
The input level conversion circuit 7 converts the level up to the signal amplitude within the functional block 2. Thereby, the signal line or bus line 3 with a large wiring capacitance is operated with a low amplitude, so that the power consumed by charging and discharging the signal line can be significantly reduced. Furthermore, since it only lowers the signal amplitude of the signal line, it does not lead to a reduction in the speed of the entire circuit.

FIG. 3 shows a specific circuit example of the output level conversion circuit 6 and the input level conversion circuit 7 used in the first embodiment. The output level conversion circuit 6 is a normal CMO
It can be configured with an S inverter. At this time, the source of the PMOS transistor is connected to the low voltage power supply 8. Also,
A signal 4 having a voltage amplitude equal to the power supply voltage of the circuit in the functional block 1 is input to the input gate. On the other hand, the input level conversion circuit 7 is composed of a level shift circuit and an inverter circuit each consisting of two sets of CMOS inverters. The sources of the PMOS transistors 10 and 11 of the level shift circuit are connected to a potential 9 equal to the power supply voltage of the circuit,
A low amplitude signal 5 transferred via the signal line or bus line 3 is input to the gates of the NMOS transistors 12 and 13.

Next, FIG. 4 shows the basic circuit configuration of another output level conversion circuit 6 used in the circuit configuration of the present invention. Here, the CMOS inverter circuit used in the output level conversion circuit 6 of FIG. 3 has a problem in that the driving ability of the PMOS transistor is significantly reduced when the potential of the low voltage power supply 8 is low. This is because when the power supply voltage decreases, the potential difference between the source potential of the PMOS transistor and the "Low" level of the input signal becomes smaller, so that the current driving ability when "ON" is reduced due to the nature of the PMOS transistor. This problem can be solved by using a circuit configured as shown in FIG. The circuit shown in FIG. 4 has two NMOS transistors 14 and 15 connected in series, a low voltage power supply 8 is connected to the drain of the NMOS transistor 14, and NMOS transistors 14 and 15 are connected in series.
A signal 4 having a voltage amplitude equal to the power supply voltage of the circuit is input to the gates of the MOS transistors 14 and 15. The reason why the speed can be increased by using the circuit shown in Fig. 4 is that the PMO
The carrier mobility of an NMOS transistor is about three times greater than that of an S transistor. Also, N.M.O.
This is because by applying a high voltage to the gate of the S transistor, the potential between the gate and the source can be increased, and the transistor can be turned on strongly. Conventionally, when the circuit shown in FIG. 4 is used as an output buffer, N
Since the drain potential of the MOS transistor 14 and the signal potential of the gate input are equal, the output potential of the buffer is “High”.
h" level rose only to the power supply voltage -Vth. Therefore, it was unsuitable for the output buffer of a low voltage circuit as it would cause a drop in signal level. However, if applied to the circuit configuration of the present invention, Since the potential drop of the power supply voltage -Vth is not a problem, it can be used as an output buffer.Also, with the conventional CMOS inverter buffer, by using a low voltage power supply, it can be used as an output buffer between the gate and source of a PMOS transistor. However, since the circuit in Fig. 4 is composed of NMOS transistors and a high voltage is applied to the gate, the potential difference between the gate and source is large, and the drive ability due to the drop in power supply voltage becomes a problem. Capacity decline is not a problem.

FIG. 5 shows a first specific inventive circuit of the output level conversion circuit shown in FIG. 4. The circuit has a configuration in which two NMOS transistors 16 and 17 are connected in series.

A low voltage power supply 8 is connected to the drain of the NMOS transistor 16. Further, an inverter 18 is arranged to control the gate of the NMOS transistor 16. The potential of this inverter is connected to a potential 9 equal to the power supply voltage of the circuit. With the circuit configuration shown in FIG. 5, the voltage applied to the gate is high even when the power supply voltage is low, so a buffer circuit with high driving ability can be realized. In FIG. 5, the inverter 18 is used to control the gate of the NMOS transistor 16, but the NMOS transistor 17 may also be controlled by the inverter 18.

FIG. 6 shows a second specific invention circuit of the output level conversion circuit shown in FIG. 4. The output level conversion circuit shown in FIG. 6 includes a CMOS inverter including a PMOS transistor 19 and an NMOS transistor 20, an NMOS transistor 21, and a CMOS inverter 22 that generates an inverted signal of an input signal. A low voltage power supply 8 is connected to the source of the PMOS transistor 19 and the drain of the NMOS transistor 20, and the CMOS inverter 22 is connected to a potential 9 equal to the power supply voltage of the circuit. With this circuit,
The potential of the low voltage power supply 8 is low, and the PMOS transistor 19
Even if the driving ability of the transistor is low, since it is driven by the NMOS transistor 21, a decrease in the driving ability can be prevented.

FIG. 7 shows the circuit configuration of another input level conversion circuit invented this time. When adopting the circuit configuration shown in FIG. 1, the input buffer 7 to the functional block 2 must also have a signal level shifting function. conventionally,
A circuit as shown in FIG. 3 was used as the level conversion circuit. Therefore, we have now invented a level conversion circuit with a CMOS inverter configuration shown in FIG. 7 as a level conversion circuit for low voltage circuits. The circuit of the present invention includes a high Vth PMOS transistor 23 and a low Vth NMOS transistor 2.
Consists of 4. The source of the PMOS transistor 23 is connected to a potential 9 equal to the power supply voltage of the circuit. A low amplitude signal 5 is input to the gates of the PMOS transistor 23 and the NMOS transistor 24 . V of PMOS transistor
If th, the power supply voltage of the circuit, and the amplitude of the low amplitude signal are appropriately set, a signal 4 having a voltage amplitude equal to the power supply voltage of the circuit is outputted at the output of the inverter. For example, if the “High” level of the input low amplitude signal is 0.5V and the potential 9, which is equal to the circuit power supply voltage, is 1.5V, the PMO
If the Vth of the S transistor 23 is greater than or equal to 1 V and less than 1.5 V, it functions as a level conversion circuit. Here, when a normal CMOS inverter is used as an input buffer that also serves as a level converter, the input "High" level potential is lower than the source potential of the PMOS transistor, so the PMOS transistor does not turn "OFF" and always passes through. Current flows and power consumption increases. However, in the circuit of the present invention, the PMOS transistor 23 and the NMOS transistor 24 are not turned on at the same time, so that the through current can be prevented. Therefore, by using the circuit of the present invention, it is possible to configure an input buffer circuit that also functions as a level shifter with a small number of elements. Here, in FIG. 7, the PMOS transistor 23 with a high Vth is used as the PMOS transistor, but like the NMOS transistor 24, the Vth
It is also conceivable to configure the PMOS transistor using a transistor with a low voltage and change the Vth of the PMOS transistor by changing the substrate potential.

A second embodiment of the invention is shown in FIG. Figure 8
The circuit includes a signal line that transfers a low amplitude signal 5 between a functional block 1 and a functional block 2, and an inverted signal 2 of the low amplitude signal 5.
The circuits are connected by two signal lines that transfer the signal. The circuit configuration shown in FIG. 8 transfers positive logic and negative logic of the signal, thereby reducing malfunctions with low amplitude signals. Therefore, the signal amplitude can be further reduced compared to the case of transfer using a single signal line. In addition, in the case of the differential input type level conversion circuit used in the input level conversion circuit in FIG. 3, positive logic and negative logic signals are required.
A negative logic signal was being generated within the input level conversion circuit. However, if positive logic and negative logic signals are simultaneously transferred as in the circuit configuration of the present invention, there is no need to create a negative logic signal in the input level conversion circuit section. In this way, Figure 8
By adopting the circuit configuration, malfunctions with low amplitude signals are reduced, and at the same time, when a differential input type level conversion circuit is used, there is no need to generate a negative logic signal again.

In the above embodiment, only the case of a positive power supply voltage is shown, but the circuit of the present invention can also be applied to the case of a negative power supply voltage. For example, when implementing the circuit in Figure 4 with a negative power supply voltage, a PMO transistor is used instead of an NMOS transistor.
It is sufficient to use an S transistor.

[0021]

According to the present invention, the signal amplitude of the signal line used for signal transfer between circuits is consumed by the wiring between the circuits by using a signal amplitude having a lower potential than the signal amplitude inside both circuits. This has the effect of reducing power consumption. for example,
In the case of the video signal processing processor μDSP, the power consumed by the bus line is approximately 25% of the power consumption of the entire chip.
occupies Here, if the signal amplitude of the bus line is reduced to 1/3, the power consumption of the bus line is reduced to 1/9 compared to the conventional one. This results in a 22.5% reduction in the power consumption of the entire chip, which is a significant reduction in power consumption. Further, by using the circuit of the present invention in an output level conversion circuit, there is an effect of preventing a decrease in the operating speed of the circuit at low power supply voltage. Furthermore, by using the input level conversion circuit of the present invention, the level conversion circuit can be configured with a small circuit scale, so that the circuit scale does not increase.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a conventional circuit configuration.

FIG. 3 is a diagram showing a specific circuit example of the first embodiment of the semiconductor device according to the present invention.

FIG. 4 is a diagram showing the basic circuit configuration of the output level conversion circuit of the present invention.

FIG. 5 is a diagram showing an output level conversion circuit of the present invention.

FIG. 6 is a diagram showing an output level conversion circuit of the present invention.

FIG. 7 is a diagram showing an input level conversion circuit of the present invention.

FIG. 8 is a diagram showing the basic configuration of a first embodiment of a semiconductor device according to the present invention.

[Explanation of symbols]

1... Functional block 1, 2... Functional block 2, 3... Signal line or bus line, 4... Signal with voltage amplitude equal to the power supply voltage of the circuit, 5... Low amplitude signal, 6... Output level conversion circuit,
7... Input level conversion circuit, 8... Low voltage power supply, 9... Potential equal to the power supply voltage of the circuit, 10... PMOS transistor,
11...PMOS transistor, 12...NMOS transistor, 13...NMOS transistor, 14...NMOS transistor, 15...NMOS transistor, 16...NM
OS transistor, 17...NMOS transistor, 18
...CMOS inverter, 19...PMOS transistor,
20...NMOS transistor, 21...NMOS transistor, 22...CMOS inverter, 23...PMOS transistor, 24...NMOS transistor, 25...inverted signal of low amplitude signal 5.

Claims (5)

[Claims] 1. A semiconductor device that transfers signals between a plurality of circuit blocks, characterized in that the amplitude of the signal to be transferred is converted to an amplitude smaller than the signal amplitude of the circuit block, and the signal is transferred. Semiconductor equipment. 2. The semiconductor device according to claim 1, further comprising an output buffer circuit and an input buffer circuit having a signal level conversion function. 3. The output buffer circuit having a signal level conversion function according to claim 2, wherein a signal having a higher potential amplitude than the source or drain potential is input to the gate of the MOS transistor. Device. 4. A semiconductor device that transfers signals between a plurality of circuit blocks, wherein a differential signal whose amplitude is smaller than the signal amplitude of the circuit block is used as the signal to be transferred. 5. A semiconductor device characterized in that the circuits according to claims 1 to 4 are constructed within the same integrated circuit.