JPH04172015A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To switch an ECL compatible operation to a CMOS level operation by a control signal by controlling the continuity of plural output transistors according to a control input impressed to a control input terminal, and outputting different output logical levels. CONSTITUTION:This circuit is equipped with at least one control input terminal EN, and plural output transistors MP1, MN1, and MN2. Then, the continuity of plural output transistors MP1, MN1, and MN2 is controlled according to the control input impressed to the control input terminal EN, and the different output logical levels are outputted. That is, when the control input EN is in a low level, the transistor MN2 is turned off, so that this circuit can be equivalent to the output buffer of an open drain constitution by the transistor MP1 when viewed from an output terminal OUT, and an interface equivalent to an ECL compatible output buffer can be obtained. And also, when the control input En is in a high level, the output transistors MP1, MN1, and MN2 are operated as the buffers which output normal CMOS logical levels. Thus, this circuit can be operated as both the CMOS level buffer and the ECL compatible buffer by the control of the control signal EN.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to output buffer circuits, and more particularly to an ECL compatible output buffer circuit implemented in a CMOS integrated circuit.

[Conventional technology]

As a conventional ECL level compatible CMOS output buffer, as shown in FIG.
Open circuit with transistor MPI as output transistor
Some have a drain structure.

In this case, for example, the positive power supply V oo = OV, the negative power supply V
CMOS) - transistor as SS=-4,5V
I am running it in L environment. The size of the output transistor MP1 is set to a constant that can swing from, for example, -0.9V to -0.2V, which is approximately the same as the logic amplitude of ECL when the load resistance is 50Ω. Since the output transistor MPI is large in size due to 50Ω drive, the input terminal IN CMO
It is generally driven by an inverter INV that receives S amplitude.

Such an ECL-compatible output buffer has a characteristic impedance Z. Suitable for high-speed interfaces in which a =50Ω transmission line is terminated with a terminating resistor R↑=50Ω, and can be used for high-speed communication systems of approximately 150MHz without sacrificing the characteristics of high integration and low power consumption of CMOS integrated circuits. It is attracting attention as a technology for construction.

[Problem to be solved by the invention]

However, even in this conventional ECL compatible output buffer, a direct current flows through the termination power supply Vtt (=2V). Particularly when the transmission line is long, signal reflection cannot be ignored, making it necessary to use such an ECL compatible interface (parallel termination interface), which also unavoidably increases power consumption due to termination.

However, if the signal lines are short enough that reflections are not a concern, such as when mounted as a multi-chip on a ceramic or silicon substrate, this interface is of excessive quality and the power consumption Considering the heat issue and the mounting of the termination resistor, it is actually better to use ordinary CMOS.
There are benefits to the interface.

In other words, as long as conventional output buffers are used, the problem is that the optimal interface differs depending on the environment in which the LIS chip is implemented, so the output buffer must be changed to match the implementation format. there were.

An object of the present invention is to provide an output buffer circuit in which an optimal interface can be selected depending on the environment in which it is implemented.

[Means to solve the problem]

The output buffer circuit of the present invention has at least one control input terminal and a plurality of output transistors, and controls conduction of the plurality of output transistors in response to a control input applied to the control input terminal. It is characterized by outputting different output logic levels.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The CMOS level signal applied to the input terminal IN is input to the gate of the output PMO6) - transistor MPI and NMO3) - transistor MNI whose source terminals are respectively connected to the positive power supply VDD and the negative power supply 55 through the inverter INV. be done.

The drain terminals of transistors MPI and MHI are output NM
O3) The transistor MN2 is connected to the train and source terminals, the gate terminal of the transistor MN2 is connected to the control input EN, and the output terminal OUT is connected to the transistor MPI.
, are connected to the drain terminals of MN2.

In this circuit, since the transistor MN2 is turned off when the control input EN is at a low level, when viewed from the output terminal OUT, the circuit becomes equivalent to an output buffer having an oven-drain structure using the transistor MPI.

Therefore, if the transmission line is terminated with a terminating resistor RT (=50Ω) and a terminating power supply VTT (=2■) as shown in Fig. 3, it can be used as the conventional ECL compatible output buffer shown in Fig. 7. An equivalent interface can be realized. In this case, the size of transistor MP1 is set to match the logic amplitude shown in FIG.

When the control input EN is at a high level, the output transistors MPI, MNI, and MN2 operate as a buffer that outputs the normal CM*S logic level.

In other words, if this circuit is used, it can be operated as both a CMOS level buffer and an ECL compatible buffer under the control of the human controller EN.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. This embodiment uses the N for output level switching shown in the first embodiment.
Instead of the MOS transistor MN2, a configuration is adopted in which a signal obtained by taking NOR logic with the input IN and the control input ENB is input to the gate terminal of the output NMO9 transistor MNI,
Transistor MNI can be directly controlled by human control ENB.

In other words, when the control input ENB is at a high level, the transistor MNI is always off, so the transistor MP
Acts as an oven drain buffer by I, EC
Applicable to L compatible interface.

When control human power ENB is low level, normal CMOS
Acts as a level buffer. In this case, the negative power supply V
The NMOS transistor pulled down to the 55 side is MNl.
Since there is only one stage, it is possible to obtain a larger driving capacity than in the first embodiment.

In the above embodiments, the positive power supply V is used in all cases. The PMO3) transistor MPI that is pulled up to the 0 side is the same in both ECL compatible operation and CMOS operation.

Next, FIGS. 5 and 6 show third and fourth embodiments of the present invention. This circuit is used in ECL compatible operation and in CM
The drive capability of the pull-up transistor is made variable during OS operation.

In the circuit shown in Fig. 5, in addition to the circuit shown in Fig. 4, an output PMOS)-
A transistor MP2 is provided, and an output obtained by NANDing the control input terminal EN and the input IN is connected to its gate terminal.

As a result, the control human power EN is at a high level, and the control human power EN is at a high level.
When B is low level, the pull-up transistor is PM
O3) Transistors MPI and MP2, pull-down transistors operate as CMOS level buffers for NMOS) transistor MNI.

When the human control power EN is at a low level and the human control power ENB is at a high level, the output transistor MPI operates as an oven drain buffer.

That is, in this embodiment, the drive capability of the pull-up transistor is greater during CMOS level operation than during ECL compatible operation.

In the circuit shown in Fig. 6, in addition to the circuit shown in Fig. 4, the output PM
OS) PM○S transistor MP2. Connect MP3 connected in series, and connect the gate terminal of transistor MP2 to the output of inverter INV.
The gate terminal of transistor MP3 is connected to control input EN.

When operating as a CMOS level buffer, the pull-up transistors are connected to MP1, MP2. M
A series connection of P3 is added.

That is, in this embodiment, the drive capability of the pull-up transistor is smaller when operating as a CMOS level buffer.

〔Effect of the invention〕

As explained above, the output buffer of the present invention uses ECL
Compatible operation and CMOS level operation can be switched by a control input terminal. It is also possible to independently set the driving capacity in the re-operation mode.

Therefore, if the output level of the present invention is used, it can operate as a CMOS level buffer in implementations that drive short wiring, and as an ECL compatible buffer in implementations that drive long wiring (transmission paths). This LSI chip has the effect of making it possible to use an interface that is optimal from the standpoint of power consumption and speed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the first embodiment of the present invention, Fig. 2 is an explanatory diagram of CMO3 logic amplitude and ECL compatible logic amplitude, and Fig. 3 is an explanation of the operation of the circuit of the first embodiment of the present invention. 4 to 6 are circuit diagrams showing second and third embodiments of the present invention, respectively, and FIG. 7 is a circuit diagram of a conventional ECL compatible output buffer. VDD...Positive power supply, VSS...Negative power supply, VT...
・Terminal power supply, MPI, MP2. MP3=iMO3) Transistor, MN1, MN2/NMOS transistor, INV...inverter, NOR...NOR circuit, NAND...NAND circuit, line...transmission line, R,...terminal resistor, IN・・・Input terminal, OUT・
...Output terminal, EN, ENB...Control terminal.

Claims (1)

[Claims] having at least one control input terminal and a plurality of output transistors, and controlling conduction of the plurality of output transistors in response to a control input applied to the control input terminal to output different output logic levels. An output buffer circuit featuring: