JP2601223B2 - Simultaneous bidirectional input/output buffer - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THEINVENTION The present invention relates to a semiconductor device, and more particularly to an input/output circuit thereof.

[0002]

2. Description of the Related Art In the input/output circuits of semiconductor devices, bidirectional buffers that serve both input and output purposes are often used, which are effective in reducing the number of wiring lines required for signal transmission between semiconductor devices.

Conventionally, bidirectional buffers for input and output of semiconductor devices have generally been implemented using tri-state buffer type circuits that use input/output in a time-division manner, or ECL/G
There are buffers that use the wiring logic of wired connections, which are used in TL interfaces, etc.
TL (Gunning Transistor Logic) is a high-speed, low-amplitude interface between CMOS.

Among these buffers, tri-state buffers and the like have a relatively slow response speed due to the control of signal switching, and it is difficult to operate them at high speed.

Furthermore, in a bidirectional buffer using a wired connection, the received data can only be defined as an "OR" or "AND" signal with both output data.

For this reason, when output data from one bidirectional buffer is at a high level (A
In other states, the output of the other side cannot be received, and data transfer is not possible when the input and output are mutually independent.

In contrast to such bidirectional buffers, simultaneous bidirectional input/output buffers have been proposed as an interface format that allows high-speed, completely independent data transfer for input and output.

This is achieved by forming a bidirectional buffer of the type shown in FIG.
As shown in FIG. 4, two semiconductor devices a and b are connected by a single wire, and the signal logic level is high level=V
dd, low level=0, and mid level=(Vdd/2)
This is realized by taking three values:

3, in the simultaneous bidirectional buffer IOBUF, a CMOS inverter consisting of a pMOS transistor P1 and an nMOS transistor N1 constitutes an output side circuit which receives an output signal from an internal circuit of a semiconductor device (not shown) via an output terminal OUT and drives and outputs the signal to an input/output terminal IO. The input side circuit of the simultaneous bidirectional buffer IOBUF is made up of two comparators C, one input terminal of which is connected to the input/output terminal IO and the output of which is connected to the input terminal of a selector SEL.
1, C2, and an input terminal IN that transmits the output of the selector SEL to an internal circuit of a semiconductor device (not shown), and the reference voltages (logical determination levels) of the two comparators C1, C2
VR1 and VR2 are, for example, 1/4 of the power supply voltage VDD,
3/4, etc., and the comparators C1 and C2 detect the signal level of the input/output terminal IO and its logical determination levels VR1 and VR
The comparison result with 2 is output.

That is, referring to FIG. 3, in the input side circuit of the simultaneous bidirectional buffer IOBUF, if the signal inputted from the input/output terminal IO is 1/4 VDD or less, the comparators C1 and C2 both output a logical value of "0", and if the signal inputted from the IO terminal is 3/4 VDD or more, the comparators C1 and C2 both output a logical value of "1".
is output, and the selector SEL is turned on regardless of the logical value of the output signal OUT input to the selector SEL as a selection signal.
The signal level of the input/output terminal IO is outputted from the output terminal IO.

Furthermore, when the signal level of the input/output terminal IO is 1/
If the voltage is within the range of 4 VDD to 3/4 VDD, the comparators C1 and C2 output logical values "1" and "0", respectively.
Depending on the logical value of the output signal OUT, one of the comparators C1 and C2 is selected and output from the selector SEL, and the buffer operates to detect the logical value of the other's output according to the logical value of its own output signal OUT and the level of the input signal.

[0012] In other words, referring to Figure 4, when the signal levels of the transmission signals of the two buffers a and b are different, the potential level of the signal line becomes an intermediate level, and the reception signals of the two buffers switch the logical threshold value for the level of this signal line according to their own transmission signal to determine the content of the transmission signal from the other side.

[0013] Such simultaneous bidirectional input/output buffers do not require the waiting time required for synchronization to switch between transmission and reception, as is the case when tri-state buffers are used, allowing for high-speed operation, and unlike general wired connections, allows complete separation of input and output signals.

[0014]

However, it is known that in such a circuit, it is difficult to guarantee an intermediate level when a plurality of semiconductor devices are connected.

This will be explained with reference to Fig. 4. Here, between two semiconductor devices a and b, when the pMOS transistor P1 on the a side is in an on state and the nMOS transistor N1 on the b side is in an on state, the level (potential) of the signal line
is determined by the on-resistance of these transistors. When the on-resistance of the pMOS transistor P1 on the a side is higher than that of the nMOS transistor N1 on the b side, the current I flowing between the semiconductor devices a and b is determined almost entirely by the on-resistance of the pMOS transistor P1 on the a side, and the signal level is Vdd/
In the opposite case, that is, p on the a side
When the on-resistance of the MOS transistor P1 is lower than that of the nMOS transistor N1 on the b side, the signal level is set to be higher than Vdd/2.
The same is true for the relationship between the transistor N1 and the pMOS transistor P1 on the b-side.

Generally, the performance of a transistor in a semiconductor device is evaluated by comparing M
It is extremely difficult in terms of manufacturing management to suppress variations and achieve consistency among OS transistors, and further to guarantee consistency in performance and characteristics among different semiconductor devices.

For this reason, when a simultaneous bidirectional input/output buffer as shown in FIG. 3 is used under normal manufacturing variations,
The variation in on-resistance of MOS transistors is 50 to 7
0%, and the intermediate output level has a disadvantage of having a variation of about 20 to 30% with respect to Vdd/2 which is the design center.

In some cases, a resistor is connected in series to the output buffer section to stabilize the intermediate level, but this also poses the problem of increased burden in manufacturing and managing the resistors.

SUMMARY OF THE PRESENT EMBODIMENT It is therefore an object of the present invention to provide a semiconductor device which overcomes the above problems and stabilizes the intermediate output level in such a simultaneous bidirectional buffer.

[0020]

[Means for solving the Problems] In order to achieve the above-mentioned object, the present invention provides a simultaneous bidirectional input/output buffer comprising a CMOS type output buffer which outputs an output signal of a semiconductor device to an input/output terminal, and an input buffer circuit which receives the input/output terminal as an input and outputs three values to the semiconductor device according to the output signal and the signal level of the input/output terminal, further comprising a means for controlling a current flowing through the CMOS type output buffer, and controls so as to set an intermediate value level to an intermediate value of a power supply voltage.

The present invention is preferably a simultaneous bidirectional input/output buffer for simultaneously inputting and outputting data via one terminal of a semiconductor device, the terminal having three logic levels, and an input logic decision level of the bidirectional buffer being variable according to the logic output content of the bidirectional buffer, the output circuit of the bidirectional buffer being made of a CMOS logic circuit, and the high potential side power supply and the C
A first current limiting means is inserted between the low potential power supply and the CMOS logic circuit, and a second current limiting means is inserted between the low potential power supply and the CMOS logic circuit.
The present invention provides a simultaneous bidirectional input/output buffer having a current limiting means inserted therein.

In the simultaneous bidirectional input/output buffer of the present invention, the first current limiting means is preferably a pMO
forming a first current mirror circuit using S transistors;
The second current limiting means is characterized in that it comprises a second current mirror circuit made up of nMOS transistors.

[0023] The simultaneous bidirectional input/output buffer of the present invention is preferably characterized in that the currents determining the operating states of the first and second current mirror circuits are supplied from the outside via the respective terminals of the semiconductor device.

[0024]

The present invention achieves stabilization by controlling the current of the transistors in the on-state of the output buffer to correctly control the midpoint level to the midpoint of the power supply voltage when the bidirectional buffers are interconnected, thereby avoiding fluctuations in the midpoint level due to variations in the characteristics between the transistors of different conductivity types that make up the output buffer.

In the present invention, a current limiting circuit comprising a current mirror circuit is added to the simultaneous bidirectional input/output buffer, thereby stabilizing the intermediate potential level even when there is a large variation in the manufacturing process of the semiconductor device.

Furthermore, according to the present invention, when two semiconductor devices are interconnected via wiring, the current flowing through the MOS transistor of one conductivity type in the CMOS logic circuit of the bidirectional buffer on one side and the MOS transistor of the other conductivity type in the bidirectional buffer on the other side becomes equal, and the intermediate level is accurately maintained at 1/2 the power supply voltage, and is not dependent on variations in device characteristics between chips.

The present invention makes it possible to variably set the capacity/impedance of a buffer from an external terminal of a semiconductor device.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the drawings.

[0029]

[Embodiment 1] A first embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram of a semiconductor device including a simultaneous bidirectional input/output buffer according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram showing this connection between two semiconductor devices a and b.

Referring to FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a plurality of simultaneous bidirectional buffers IOBU.
F, and level generating circuits VBPG and VBNG for providing the operating bias potentials VBP and VBN thereof.

The simultaneous bidirectional buffer IOBUF has an output terminal OUT and an input terminal I
The output side circuit has four pMOS and nMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, and P10 connected in series between a power supply Vdd and a ground potential, with their sources and drains connected to each other.
The gates of the MOS transistors P1 and N1 are commonly connected to the output terminal OUT, and the drains are connected to the input/output terminal IO and the input determination unit IBUF.

Furthermore, the gates of the MOS transistors P2 and N2 are supplied with operating bias potentials VBP and VBN from level generating circuits VBPG and VBNG, respectively.

The input decision unit IBUF has two logical decision levels VR, V ...
1. Compare VR2 with the potential of the input/output terminal IO. 2
The two comparators C1, C2 are connected to a selector circuit which is selected by an output terminal OUT, and the output of the selector circuit is connected to an input terminal IN and an internal circuit of the semiconductor device.

Referring to FIG. 1, the level generating circuit VBPG
is a circuit that generates an operating bias VBP to be applied to the simultaneous bidirectional buffer IOBUF, and is composed of pMOS transistors P3 and P4 whose sources and drains are connected in series between a power supply Vdd and a reference current input terminal IREF1, and a comparator C3 that performs a potential comparison between a reference potential VR0 and the reference current input terminal IREF1.
It is connected to the gate of the MOS transistor P4.

Similarly, the level generating circuit VBNG generates an operating bias VB
N, which includes nMOS transistors N3 and N4 whose sources and drains are connected in series between the ground potential and the reference current input terminal IREF2, and a reference potential V
It comprises a comparator C4 which performs a potential comparison between R0 and a reference current input terminal IREF2, and the output VBN of this comparator C4 is connected to the gate of an nMOS transistor N4.

In this embodiment, the reference potential VR0 gives an output intermediate level=Vdd×1/2, and the logical decision levels VR1 and VR2 are VDD·3/4 and Vdd
・A potential of 1/4 is given.

[0037] Then, the reference current input terminals IREF1 and I
REF2 is maintained such that a mutually equal predetermined current (constant current) flows in or out from the outside of the semiconductor device.
The sizes of N1 and N2 are equal to N3 and N4.

Next, the operation of this embodiment will be described.

As shown in FIG. 2, between two semiconductor devices a and b
Now, a case will be described in which the simultaneous bidirectional buffer according to the present embodiment described above is connected, the output terminal OUT on side a is at the “H” level, the output terminal OUT on side b is at the “L” level, and the wiring between the semiconductor devices is at an intermediate level.

The nMOS transistor N1 on the a side and the pMOS transistor P1 on the b side are turned on, and the current flowing through them is the nM
On the b side, it is limited by the nMOS transistor N2 that is mirror-connected to the OS transistor N4, and on the b side, it is limited by the pMOS transistor P2 that is mirror-connected to the pMOS transistor P4 of the level generating circuit VBPG.

The level generating circuit VBNG determines the gate potentials of the nMOS transistors N2 and N4 in the comparator C4 so that the potential of the reference current input terminal IREF2 is kept at the same potential as the reference potential VR0.

For this reason, the nMOS transistors N1 and N
2, the drain potential of the nMOS transistor N2 is V
In the case of dd/2, the same current as that applied to the terminal IREF2 flows. This also applies to the level generating circuit VBPG.

Reference current input terminals IREF1, IREF2
Since the same current flows through both sides a and b,
The current flowing through the pMOS transistors P1 and P2 on the b-side of the MOS transistors N1 and N2 is equal to this reference current, and the intermediate level is accurately maintained at Vdd/2, and is not dependent on manufacturing variations in the transistors between the two semiconductor devices.

Although the present invention has been described above with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments conforming to the principles of the present invention.

[0045]

As described above, according to the present invention (claim 1), the current of the transistor flowing in the CMOS type output buffer is controlled, and the intermediate level when the bidirectional buffers are interconnected is correctly set to the intermediate value (1/2) of the power supply voltage.
2), it has the effect of stabilizing the intermediate level without being dependent on variations in characteristics such as on-resistance between transistors of different conductivity types constituting the output buffer and variations in characteristics between chips.

According to the present invention (claims 2 and 3),
By adding a current limiting circuit, preferably a current mirror circuit, to the simultaneous bidirectional input/output buffer, it is possible to have an effect of stabilizing the intermediate potential level even when there is a large variation in the manufacturing process of the semiconductor device.

According to the present invention (claims 2 and 3),
When two semiconductor devices are interconnected through wiring using a simple circuit configuration, the CMOS of the bidirectional buffer on one side
The current flowing through the MOS transistor of one conductivity type in the logic circuit and the MOS transistor of the bidirectional buffer on the other side is equal, and the intermediate level is accurately maintained at 1/2 the power supply voltage, and is not dependent on variations in device characteristics between chips.

Furthermore, according to the present invention (claim 4), there is an effect that the capacity/impedance etc. of the buffer can be varied from outside the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor device including a simultaneous bidirectional input/output buffer according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a state in which two semiconductor devices of FIG. 1 are connected together;

FIG. 3 is a circuit diagram of a semiconductor device including a conventional simultaneous bidirectional input/output buffer.

4 is a diagram showing a state in which two semiconductor devices of FIG. 3 are connected together;

[Explanation of symbols]

IOBUF Bidirectional buffer IBUF Input judgment section VGNB, VBPG Bias generation circuit C1, C2, C3, C4 Voltage comparator IO, OUT, IN Signal terminal IREF1, IREF2 Reference current input terminal VR0, VR1, VR2 Reference potential terminal N1, N2, N3, N4 nMOS transistor P1, P2, P3, P4 pMOS transistor

Claims (4)

(57) [Claims] [Claim 1] A simultaneous bidirectional input/output buffer comprising: a CMOS output buffer which outputs an output signal of a semiconductor device to an input/output terminal; and an input buffer circuit which receives the input/output terminal as an input and outputs three values to the semiconductor device according to the output signal and the signal level of the input/output terminal, further comprising a means for controlling a current flowing through the CMOS output buffer, and controls the intermediate level to be set to the intermediate value of a power supply voltage. [Claim 2] A simultaneous bidirectional input/output buffer for simultaneously inputting and outputting through one terminal of a semiconductor device, the terminal having three logic levels, and an input logic decision level of the bidirectional buffer being variable according to the logic output content of the bidirectional buffer, the output circuit of the bidirectional buffer being made of a CMOS logic circuit, a first current limiting means being inserted between a high potential side power supply and the CMOS logic circuit, and a second current limiting means being inserted between a low potential side power supply and the CMOS logic circuit.
A simultaneous bidirectional input/output buffer comprising a second current limiting means inserted between said buffer and an OS logic circuit. 3. The first current limiting means comprises a first current mirror circuit using pMOS transistors, and the second current limiting means comprises a first current mirror circuit using pMOS transistors.
3. The current limiting means according to claim 2, further comprising a second current mirror circuit formed by nMOS transistors.
The simultaneous bidirectional input/output buffer described herein is 4. The simultaneous bidirectional input/output buffer according to claim 3, wherein currents determining the operating states of said first and second current mirror circuits are supplied from the outside via respective terminals of said semiconductor device.