JPH04370955A - Integrated circuit wiring method - Google Patents
Integrated circuit wiring methodInfo
- Publication number
- JPH04370955A JPH04370955A JP14854291A JP14854291A JPH04370955A JP H04370955 A JPH04370955 A JP H04370955A JP 14854291 A JP14854291 A JP 14854291A JP 14854291 A JP14854291 A JP 14854291A JP H04370955 A JPH04370955 A JP H04370955A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- tisi
- contact hole
- wiring layer
- burying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 abstract description 19
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract description 2
- 239000002356 single layer Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は集積回路の多層配線のコ
ンタクト穴部での接続方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting multilayer wiring in integrated circuits at contact holes.
【０００２】0002
【従来の技術】従来集積回路の配線接続法として、コン
タクト穴部にＷ叉はポリＳｉを埋め込む方法はあった。2. Description of the Related Art Conventionally, as a wiring connection method for integrated circuits, there has been a method of burying W or poly-Si in contact holes.
【０００３】0003
【発明が解決しようとする課題】しかし、上記従来技術
によるとコンタクト穴部の配線抵抗が高くなると言う課
題が有った。[Problems to be Solved by the Invention] However, the above-mentioned prior art has a problem in that the wiring resistance in the contact hole increases.
【０００４】本発明は、かかる従来技術の課題を解決し
低抵抗で且つコンタクト穴部を埋め込む新しい集積回路
の配線接続法を提供する事を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide a new integrated circuit wiring connection method that has low resistance and buries contact holes.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成する為に本発明は集積回路の配線接続法に関
し、（１） 少なくともコンタクト穴部にＴｉＮ，Ｔ
ｉＳｉ叉はＴｉを埋め込む手段を取る事、及び（２）
コンタクト穴部はＴｉＮ，ＴｉＳｉ叉はＴｉを埋め込
むと共に、前記ＴｉＮ，ＴｉＳｉ叉はＴｉ膜を絶縁膜上
に延在して配する手段を取る事、等の手段を取る。[Means for Solving the Problems] In order to solve the above problems and achieve the above objects, the present invention relates to a wiring connection method for integrated circuits.
(2) taking steps to embed iSi or Ti; and (2)
The contact hole portion is filled with TiN, TiSi, or Ti, and the TiN, TiSi, or Ti film is disposed extending over the insulating film.
【０００６】[0006]
【実施例】以下、実施例により本発明を詳述する。[Examples] The present invention will be explained in detail with reference to Examples below.
【０００７】図１は本発明の一実施例を示す集積回路の
要部の断面図である。すなわち、Ｓｉから成る基板１の
表面には拡散層から成る第１の配線層２が形成されて成
ると共に、絶縁膜３を介して前記第１の配線層２上に開
けられたコンタクト穴部にＴｉＮ，ＴｉＳｉ叉はＴｉを
埋め込んで形成したプラグ部４を形成し、その後Ａｌ等
から成る第２の配線層４を形成したものである。尚、プ
ラグ部４のＴｉＮ，ＴｉＳｉ叉はＴｉは単層でも多層で
あっても良く、更にプラグ部４のＴｉＮ，ＴｉＳｉ叉は
Ｔｉはエッチバック法によるスパッタ成膜法や選択ＣＶ
Ｄ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉ
ｔｉｏｎ）法等により形成する事が出来る。更に、第１
の配線層２は絶縁膜上のＡｌ配線層等の金属配線層であ
っても良い。FIG. 1 is a sectional view of a main part of an integrated circuit showing an embodiment of the present invention. That is, a first wiring layer 2 made of a diffusion layer is formed on the surface of a substrate 1 made of Si, and a contact hole formed on the first wiring layer 2 is formed through an insulating film 3. A plug portion 4 is formed by embedding TiN, TiSi, or Ti, and then a second wiring layer 4 made of Al or the like is formed. Note that the TiN, TiSi, or Ti of the plug portion 4 may be a single layer or a multilayer, and furthermore, the TiN, TiSi, or Ti of the plug portion 4 may be formed by a sputtering film formation method using an etch-back method or a selective CV method.
D (Chemical Vapor Deposit)
tion) method. Furthermore, the first
The wiring layer 2 may be a metal wiring layer such as an Al wiring layer on an insulating film.
【０００８】図２は本発明の他の実施例を示す集積回路
の要部の断面図である。すなわち、Ｓｉから成る基板１
１の表面には拡散層から成る第１の配線層１２が形成さ
れて成ると共に、絶縁膜１３を介して前記第１の配線層
１２上に開けられたコンタクト穴部にＴｉＮ，ＴｉＳｉ
叉はＴｉをプラグ部１４に埋め込んで形成すると共に、
前記絶縁膜１３の表面まで延在させてＣＶＤ法等により
形成して成る。この場合、コンタクト穴部が深いとアス
ペクト比が大となる為に、つきまわりの良好な成膜法に
て成膜する必要が有る。その点、ＣＶＤ法はつきまわり
の良い成膜法で有り、且つ ＴｉＮ，ＴｉＳｉ叉はＴ
ｉはＣＶＤ法により成膜が可能である。この事は図１の
例にも言える事である。Ａｌ等の金属膜等から成る第２
の配線層１５は必ずしも必要では無いが本例では集積回
路の配線の一層の低抵抗化を計る為に示した。FIG. 2 is a sectional view of the main parts of an integrated circuit showing another embodiment of the present invention. That is, the substrate 1 made of Si
A first wiring layer 12 made of a diffusion layer is formed on the surface of the first wiring layer 1, and a contact hole made on the first wiring layer 12 through an insulating film 13 is filled with TiN, TiSi.
Alternatively, while forming Ti by embedding it in the plug portion 14,
It extends to the surface of the insulating film 13 and is formed by a CVD method or the like. In this case, since the aspect ratio becomes large when the contact hole is deep, it is necessary to form the film using a film forming method with good coverage. In this respect, the CVD method is a film forming method with good coverage, and is suitable for TiN, TiSi or T
i can be formed into a film by the CVD method. This also applies to the example shown in FIG. The second layer is made of a metal film such as Al.
Although the wiring layer 15 is not necessarily necessary, it is shown in this example in order to further reduce the resistance of the wiring of the integrated circuit.
【０００９】ＴｉＮ，ＴｉＳｉ叉はＴｉは従来のＷやポ
リＳｉ等と比較して十分に低抵抗であると共に、Ｓｉや
他の金属との接触抵抗も低いので、少なくともプラグ部
にＴｉＮ，ＴｉＳｉ叉はＴｉを埋め込んで形成する事は
、集積回路の多層配線における配線抵抗の減少と共に、
コンタクト穴部での断線不良を無くする為にも好都合で
ある。TiN, TiSi or Ti has a sufficiently low resistance compared to conventional W, poly-Si, etc., and also has low contact resistance with Si or other metals, so TiN, TiSi or Ti is used at least in the plug part. By embedding Ti, the wiring resistance in multilayer wiring of integrated circuits can be reduced, and
This is also convenient for eliminating disconnection defects at the contact hole.
【００１０】0010
【発明の効果】本発明により、低抵抗で且つコンタクト
穴部を埋め込む新しい集積回路の配線接続法を提供する
事が出来る効果が有る。According to the present invention, it is possible to provide a new integrated circuit wiring connection method that has low resistance and buries contact holes.
【図１】本発明の一実施例を示す集積回路の要部の断面
図である。FIG. 1 is a sectional view of a main part of an integrated circuit showing an embodiment of the present invention.
【図２】本発明の他の実施例を示す集積回路の要部の断
面図である。FIG. 2 is a sectional view of a main part of an integrated circuit showing another embodiment of the present invention.
１、１１ ・・・ 基板、
２、１２ ・・・ 第１の配線層、３、１３ ・
・・ 絶縁膜、
４、１４ ・・・ プラグ部、
５、１５ ・・・ 第２の配線層1, 11... Substrate, 2, 12... First wiring layer, 3, 13.
... Insulating film, 4, 14 ... Plug part, 5, 15 ... Second wiring layer
Claims (2)
ｉＳｉ叉はＴｉが埋め込まれて成る事を特徴とする集積
回路の配線法。Claim 1: At least the contact hole is made of TiN, T.
A wiring method for an integrated circuit characterized by embedding iSi or Ti.
Ｔｉが埋め込まれて成ると共に、前記ＴｉＮ，ＴｉＳｉ
叉はＴｉ膜が絶縁膜上に延在して配されて成る事を特徴
とする集積回路の配線法。2. The contact hole is filled with TiN, TiSi, or Ti, and the TiN, TiSi, or
A wiring method for an integrated circuit characterized in that a Ti film is disposed extending over an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14854291A JPH04370955A (en) | 1991-06-20 | 1991-06-20 | Integrated circuit wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14854291A JPH04370955A (en) | 1991-06-20 | 1991-06-20 | Integrated circuit wiring method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04370955A true JPH04370955A (en) | 1992-12-24 |
Family
ID=15455104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14854291A Pending JPH04370955A (en) | 1991-06-20 | 1991-06-20 | Integrated circuit wiring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04370955A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160273A (en) * | 1991-12-05 | 1993-06-25 | Sharp Corp | Contact plug of semiconductor device and formation thereof, and multilayer wiring of semiconductor device and formation thereof |
| WO1997005298A1 (en) * | 1995-08-01 | 1997-02-13 | Multilevel Metals Inc | Titanium-based films formed by chemical vapor deposition |
| DE10208714A1 (en) * | 2002-02-28 | 2003-09-25 | Infineon Technologies Ag | Contact for integrated circuit, running through contact hole in insulation layer between line planes to connect line planes, comprises entirely of titanium and/or titanium nitride |
-
1991
- 1991-06-20 JP JP14854291A patent/JPH04370955A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160273A (en) * | 1991-12-05 | 1993-06-25 | Sharp Corp | Contact plug of semiconductor device and formation thereof, and multilayer wiring of semiconductor device and formation thereof |
| WO1997005298A1 (en) * | 1995-08-01 | 1997-02-13 | Multilevel Metals Inc | Titanium-based films formed by chemical vapor deposition |
| DE10208714A1 (en) * | 2002-02-28 | 2003-09-25 | Infineon Technologies Ag | Contact for integrated circuit, running through contact hole in insulation layer between line planes to connect line planes, comprises entirely of titanium and/or titanium nitride |
| US6903009B2 (en) | 2002-02-28 | 2005-06-07 | Infineon Technologies Ag | Methods for fabricating a contact for an integrated circuit |
| DE10208714B4 (en) * | 2002-02-28 | 2006-08-31 | Infineon Technologies Ag | Manufacturing method for a contact for an integrated circuit |
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