JPH06334048A - Formation of multilayer wiring for semiconductor element - Google Patents

Abstract

PURPOSE:To prevent insufficient conduction by connecting two metallizations formed on a dielectric film of a semiconductor substrate through a connection post thereby eliminating the deposition film. CONSTITUTION:A first insulation layer 12 and a first metallization 13 are formed sequentially on a semiconductor substrate 11 by CVD. A contact hole 14 is then made by photolithography and etching and a first barrier metal film 15, e.g. a Ti or TiN film, of 1000Angstrom and a second barrier metal film 16, e.g. a W film, of 8000Angstrom are grown on the entire surface by CVD. Subsequently, a connection post 18 is formed by photolithography and etching and a connection plug 17 is formed in the contact hole 14. Furthermore, a second dielectric film 19 is formed by CVD after patterning the first metallization 13 and the upper part of the connection post 18 is exposed from the surface of the second dielectric film 19 by etch back. Thereafter, a second metallization 20 is formed by CVD and patterned to obtain a multilayer wiring structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer wiring of a semiconductor device.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a conventional process for forming a multi-layer wiring of a semiconductor device. Hereinafter, a conventional method for forming a multilayer wiring of a semiconductor device will be described. (1) First, as shown in FIG.
An insulating film 22 is formed on top. After that, a first contact hole 23 is formed in the insulating film 22 by sequentially performing photolithography and etching of a known technique.

(2) Next, as shown in FIG.
The barrier metal film 24 and the first metal wiring layer 25 are sequentially formed by the vapor deposition method or the CVD method. (3) After that, as shown in FIG. 2C, the first metal wiring layer 25 and the barrier metal film 24 are patterned by a known technique. After that, the insulating film 26 is formed by the CVD method. Then, the second contact hole 2 is formed by sequentially performing photolithography and etching of a known technique.
7 is formed.

(4) Then, as shown in FIG.
After forming the second metal wiring layer 28 by the vapor deposition method or the CVD method, the second metal wiring layer 28 is patterned by a known technique to form the multilayer wiring.

[0005]

However, in the conventional method for forming a multilayer wiring of a semiconductor element described above, a deposit film (deposited film) remains when forming a contact hole,
There is a problem that a conduction failure occurs, and a disconnection and a short circuit are likely to occur due to poor coverage of the contact hole of the wiring pattern.

Here, the term "deposited film" means that when a second contact hole is formed on a metal wiring layer, if a dry etching technique is used, a base film is formed at the time of over-etching after etching of an insulating film. This is a film formed by aluminum being sputtered with Ar, which is an etching gas, and attached to the side surface of the contact hole or the side surface of the photoresist hole used for etching the contact hole.

The present invention eliminates the above-mentioned problems of disconnection and short circuit due to poor conduction and poor coverage, and a barrier metal film is buried in the first contact hole by the full-scale CVD method, and the second contact hole is An object of the present invention is to provide a method for forming a multi-layer wiring of a semiconductor element, which can form a wiring pattern with good coverage while reducing conduction defects due to a deposited film remaining during through-hole etching by forming the pillar by a pillar formation method. To do.

[0008]

In order to achieve the above object, the present invention provides a method for forming a multilayer wiring of a semiconductor device, which comprises a step of forming a first insulating film on a semiconductor substrate, and a step of forming the first insulating film. A step of forming a first metal wiring layer on the film, a step of forming a first contact hole penetrating the first insulating film and the first metal wiring layer, and a step of depositing a lower barrier metal layer. A step of depositing an upper barrier metal layer made of a refractory metal layer, filling the first contact hole and forming a predetermined thickness on the first metal wiring layer, and selectively forming the upper barrier metal layer. A step of etching to form a connection plug in the first contact hole and a connection pillar extending above the first metal wiring layer; and a second step of exposing the connection pillar. Insulation film forming process When is obtained by so applying and forming a second metal interconnection layer connected to said connection post.

[0009]

According to the present invention, as described above, the first metal wiring layer and the second metal wiring layer are connected to each other by the connecting pillars. It is not necessary to carry out the etching, and the deposition film is not generated, so that the conduction failure can be prevented.

Further, since the first contact hole is a buried plug and the wiring between the first metal wiring layer and the second metal wiring layer is a connection pillar, the coverage and the flatness are improved. You can

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view of a multi-layer wiring forming process of a semiconductor device showing an embodiment of the present invention. Hereinafter, a multilayer wiring of a semiconductor device showing an embodiment of the present invention will be described with reference to FIG. (1) First, as shown in FIG.
Then, the first insulating film 12 is formed on the first metal wiring layer 1 by the CVD method.
3 are sequentially formed by vapor deposition or a CVD method.

(2) Next, as shown in FIG.
The contact hole 14 is formed by photolithography and etching using known techniques. After that, the first barrier metal film 15, for example, a Ti or TiN film is 1000 Å, and the second barrier metal film 16, for example, a W film is 8000 Å for CV.
The entire surface is grown by the D method. At this time, since the second barrier metal film 16 is used as a connection pillar (described later), the thickness of the second barrier metal film 16 is set to the second value.
The insulating film (described later) has a desired film thickness or more.

(3) Next, as shown in FIG.
Photolithography and etching for forming the connection pillar 18 are sequentially performed. Here, since the etching is performed until the first barrier metal film 15 is exposed, the connection plug 17 is formed in the contact hole 14. (4) Next, as shown in FIG. 1D, the first metal wiring layer 13 is patterned by a known technique. After that, the second insulating film 19 is formed by the CVD method, and then the second insulating film 19 is etched by the etch back method to expose the upper portion of the connection pillar 18 from the surface of the second insulating film 19. Then, the second metal wiring layer 20 is deposited or CVD.
It is formed by the method. Then, by patterning the second metal wiring layer 20 by a known technique, a multilayer wiring structure is obtained.

Although the second insulating film is formed by the etch-back method in the above embodiment, it is of course possible to use the photolithography / etching technique. In this case, the thickness of the second insulating film and the connectivity can be improved. The height of can be set arbitrarily. At this time, since the connectivity is formed, it goes without saying that the connection with the second metal wiring layer can be made more easily and more stably than the conventional method.

Although the connection of the first metal wiring layer and the second metal wiring layer has been described, the invention is not limited to this.
The same effect can be expected when applied to the connection of the second metal wiring layer and above. Furthermore, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0016]

As described above in detail, according to the present invention, the first metal wiring layer and the second metal wiring layer are connected by the connecting pillars. It is no longer necessary to perform etching for forming the contact hole, the deposition film is not generated, and conduction failure can be prevented.

Further, since the first contact hole is a buried plug and the wiring between the first metal wiring layer and the second metal wiring layer is a connection pillar, it is possible to improve the coverage and the flatness. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a multilayer wiring forming process of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional multi-layer wiring forming process for a semiconductor device.

[Explanation of symbols]

 11 semiconductor substrate 12 first insulating film 13 first metal wiring layer 14 contact hole 15 first barrier metal film 16 second barrier metal film 17 connection plug 18 connection pillar 19 second insulating film 20 second metal wiring layer

Claims (2)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of forming a first metal wiring layer on the first insulating film, and a step of forming the first metal wiring layer on the first insulating film. Forming a first contact hole penetrating the first insulating film and the first metal wiring layer; (d) depositing a lower barrier metal layer; and (e) an upper barrier layer made of a refractory metal layer. Depositing a metal layer to fill the first contact hole and
Forming a predetermined thickness on the metal wiring layer, and (f) selectively etching the upper barrier metal layer to form a connection plug in the first contact hole and to form the first metal. A step of forming a connection pillar extending above the wiring layer; (g) a step of forming a second insulating film so that the connection pillar is exposed; and (h) a second metal connected to the connection pillar. And a step of forming a wiring layer, the method for forming a multilayer wiring of a semiconductor element. 2. The formation of the second insulating film in the step (g) has a step of first forming an insulating film on the entire surface and then etching back the entire insulating film to expose the upper surface of the connection pillar. The method for forming a multilayer wiring of a semiconductor device according to claim 1, which is characterized in that.