JPH04366995A - Video display device - Google Patents

Abstract

PURPOSE:To control whether characters are fringed or not, character by character or line by line. CONSTITUTION:This video display device is provided with a fringing ON/OFF data storage circuit 29 which hold flags indicating whether the characters are fringed or not, character by character or line by line, and a flag held in an address specified with a line selection signal R and a column selection signal C is sent as a fringing ON/OFF signal F to a serial converting circuit 28 which generates a fringed pattern. Further, the serial converting circuit 28 selects a fringed display or unfringed display according to the signal F and outputs it.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device, and more particularly to a video display device such as a television, VTR, video camera, laser disc, etc., which superimposes framed characters or patterns.

0002

2. Description of the Related Art FIG. 3 is a block diagram mainly showing a character video signal generation circuit portion of a conventional video display device. This character video signal generation circuit 13 includes a display data RAM 5 that can store codes of all characters (hereinafter referred to as character codes) displayed on the screen at one time.

In order to write the character code "W" sent from the microcomputer 1 into the display data RAM 5, this circuit includes a write address register 2, a write data register 3, a write synchronization circuit 4, and an address selection circuit 6. It is equipped with In response to control and data signal B from microcomputer 1, write address register 2 holds address "A" and write data register 3 holds character code "W". The write synchronization circuit 4 generates a write synchronization signal S, and upon receiving this write signal synchronization S, the address selection circuit 6 selects the display data RA.
Generate address signal U to M5.

[0004] Also, the character code "G" to be displayed
In order to read out from the display data RAM 5, the character video signal generation circuit 13 includes a vertical address counter 12, an oscillation circuit 11, and a horizontal address counter 10. The vertical address counter 12 receives a vertical synchronization signal V and a horizontal synchronization signal H for synchronizing with the scanning line and generates a row selection signal R, which is used to determine the vertical position on the display screen. Send R to the address selection circuit 6. The oscillation circuit 11 receives a horizontal synchronizing signal H and generates a dot clock D whose phase is synchronized with the horizontal synchronizing signal H in order to obtain timing during horizontal scanning. The horizontal address counter 10 receives the horizontal synchronization signal H and the dot clock D, generates a digit selection signal C for determining the horizontal position on the display screen, and supplies the address selection circuit 6 and the write synchronization circuit 4.
Send digit selection signal C to

Furthermore, the selected character code "G"
”, the character video signal generation circuit 13 includes a character generator 7 and a serial conversion circuit 8, and the character generator 7 selects the address signal L generated by the address selection circuit 6. In response to the character code "G", the character pattern "P" for one line of the pattern for one character is
Further, the serial conversion circuit 8 sequentially outputs a character pattern consisting of a plurality of bits for one line dot by dot in accordance with the dot clock D.

The serial conversion circuit 8 further includes a circuit that generates a border pattern "Y", and synthesizes the bordered character pattern with another video signal E to generate a border pattern "Y".
It can also be displayed on RT9.

The operation of the character video signal generation circuit 13 having such a configuration when writing the character code "W" sent from the microcomputer 1 into the display data RAM 5 will be explained.

When the microcomputer 1 sends the character code "W" to be written to the display data RAM 5 to the write data register 3 in accordance with the control and data signal B, the write data register 3 holds the character code "W". Output. Character code “
Address “A” of display data RAM 5 where you want to write “W”
When microcomputer 1 sends address "A" to write address register 2 in accordance with control and data signal B, write address register 2 holds address "A" and outputs it on address signal A. The microcomputer 1 sends a control signal indicating that the write address register 2 holds the address "A" and the write data register 3 holds the character code "W" to the write synchronization circuit 4 in accordance with the control and data signal B. When informed that the write is ready, the write synchronization circuit 4 attempts to output a write synchronization signal S for writing.

However, at this time, the character code "G" for display selected by the address signal U generated by the address selection circuit 6 which receives the row selection signal R and the digit selection signal C is read out from the display data RAM 5. is performed in synchronization with the horizontal synchronization signal H and the vertical synchronization signal V, the write synchronization circuit 4 avoids the timing when the character code "G" is being read, and reads the character code "G".
” during the unnecessary horizontal retrace period and vertical retrace period, the write synchronization signal S is output. Upon receiving the write synchronization signal S, the address selection circuit 6 selects the address signal A, and selects the address on this signal A. "A" is output to the display data RAM 5 as an address signal U, and a character code "W" is written to the address "A" in the display data RAM.

The operation of the circuit when selecting and reading out the character code "G" to be displayed from the display data RAM 5 will be explained. The vertical address counter 12 has a count value initialized in response to a vertical synchronization signal V, advances the count value in response to a horizontal synchronization signal H, and outputs a row selection signal R for determining the vertical position of a scanning line. . The oscillation circuit 11 is
Upon receiving the horizontal synchronizing signal H, the oscillation phase is initialized, and a dot clock D having a frequency corresponding to the horizontal scanning speed of the scanning line is generated and output. The horizontal address counter 10 has its count value initialized in response to the horizontal synchronization signal H, advances the count value in response to the dot clock D, and outputs a digit selection signal C for determining the horizontal position of the scanning line. The address selection circuit 6 receives the row selection signal R and digit selection signal C generated in this way, and selects the display data RA.
An address signal U to M and an address signal L to character generator 7 are calculated and generated according to the respective storage formats, and are output.

The display data RAM 5 receives the address signal U, reads out the character code "G" previously stored at the address specified by the address signal, and outputs it to the character generator 7. The character generator 7 may be a ROM that stores character patterns, and upon receiving the character code "G", selects a pattern for one character (matrix configuration) corresponding to that code, and upon receiving the address signal L, A character pattern "P" for one line of the pattern for one character is output.

To generate a border pattern, patterns for the upper and lower rows are also required, and a total of three rows of patterns are required. Therefore, for example, when the value of the address signal L is "N", a character pattern to be displayed is In this case, the value of the address signal L changes from "(N-1)" to "N" to "(N+1)" within the time it takes to scan the width of one character. The character patterns for three lines are read out (see (a) in FIG. 2).

The serial conversion circuit 8 is a circuit mainly composed of a shift register in order to convert parallel data to serial data. Generally, three sets of shift registers are provided to process the three lines of character patterns required to generate the border pattern. Character patterns consisting of multiple bits for three lines are latched in parallel by three sets of shift registers, and in response to the dot clock D, the character pattern "P" and the generated border pattern "Y" are latched one dot at a time. Output to serial. In this way, the pattern of the bordered display Z generated from the borderless display N is displayed on the screen ((a
).

The video signal generated by the character video signal generation circuit 13 and sequentially output dot by dot is combined with another video signal E and displayed on the CRT 9. For example, if a character pattern is displayed in white and the background is also white, it will be difficult to distinguish the character pattern if there is no border, but if the character pattern is displayed in white and the background is also white, it will be difficult to distinguish the character pattern. When the character's pattern is highlighted, it becomes easier to see regardless of the background condition.

[0015]

[Problems to be Solved by the Invention] However, in conventionally configured video display devices, all character patterns are bordered, so it is difficult to emphasize only certain parts such as the date and time. The problem is that it cannot be handled. An object of the present invention is to solve the problems of the prior art, and to provide a video display device that can control the presence or absence of a border for each character or for each line.

[0016]

[Means for Solving the Problems] In order to achieve this object, the configuration of the video display device of the present invention is such that a character video signal generation circuit having a conventional configuration is provided with a flag indicating the presence or absence of a border for each character or each row. A border presence/absence data storage circuit is provided to hold the border presence/absence data. Here, this border presence/absence data storage circuit receives a line selection signal that determines the vertical position on the screen and a digit selection signal that determines the horizontal position, and stores it at the address specified by these signals. Outputs the flag that is being used. The output flag is sent as a border presence/absence signal to a serial conversion circuit that generates a border pattern. Then, the serial conversion circuit selects and outputs either a bordered display or a borderless display according to this border presence/absence signal.

Furthermore, this border presence/absence data storage circuit may be a ROM, but if it is mainly composed of a writable RAM instead of a ROM, it has an interface with a microcomputer, and A flag indicating the presence or absence of a border is stored in accordance with control and data signals from the controller.

[0018]

[Operation] According to the above-described configuration, the border can be selected and displayed for each character or each line as described below. The value of the flag corresponding to the position on the screen where the character pattern to be emphasized by adding a border is displayed, that is, the value of the flag at the corresponding address of the memory in the border presence/absence data storage circuit, is set to, for example, "1". Then, the value of the flag corresponding to the position on the screen where the character pattern without the border is displayed because it is not desired to be emphasized, that is, the value of the flag of the corresponding address of the memory in the border presence/absence data storage circuit, is set to, for example, "0". do. With this setting, the display character is determined by the address generated by the address generation circuit from the row selection signal and the digit selection signal, and at the same time, the display character is determined from the border presence data storage circuit according to the row selection signal and the digit selection signal. The value of a flag indicating the presence or absence of a border corresponding to the character is read. This read value is sent as a border presence/absence selection signal to a serial conversion circuit that generates a border. If the value of this border presence/absence selection signal is "1", the serial conversion circuit selects and outputs the bordered display. If the value of the border presence/absence selection signal is "0", the serial conversion circuit selects and outputs borderless display. in this way,
Depending on the value of "1" or "0" of the border presence/absence selection signal, the serial conversion circuit selects and outputs either bordered display or borderless display. As a result, it becomes possible to select each character or line and emphasize it with a border, or display it without a border.

If the border presence/absence data storage circuit has an interface with a microcomputer and is configured mainly of RAM, the value of the flag indicating the presence/absence of a border is changed in accordance with control and data signals from the microcomputer. Therefore, the display character to be emphasized can be freely selected anytime and anywhere. Furthermore, by providing an independent border presence/absence data storage circuit, the timing of changing the character code to be displayed and the timing of specifying whether or not to border that character or the line containing that character can be made arbitrary. A simple microcomputer program for setting and changing character codes and flags is sufficient. In particular, if it is sufficient to control the presence or absence of a border for each line, the memory capacity for the total number of characters is not required, so the memory capacity in the border presence/absence data storage circuit may be small.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram mainly showing a character video signal generation circuit portion of a video display device according to an embodiment of the present invention, and corresponds to FIG. 3 showing a conventional example. FIG. 2(a) shows a character pattern and
This is an example of a border pattern surrounding the top, bottom, left and right dots. FIG. 2(b) is a detailed block diagram of a border presence/absence data storage circuit that can control the presence or absence of a border for each row.

A specific example of the configuration of the border presence/absence data storage circuit 29 in this embodiment is shown in FIG. 2(b). The configuration of this circuit is mainly composed of a RAM 29b, an interface 29a with a microcomputer, and an address conversion circuit 2.
9e is added and connected. RAM2
A dual port memory is used for 9b, and the write side address port is connected to the interface 29a. Furthermore, the interface 29a is connected to the microcomputer 1 via control and data signals B. As a result, the microcomputer 1 sends control signals, addresses, and data to the interface 29a via the control and data signal B, and in response, the interface 29a accesses the RAM 29a, and the
The value of a designated flag 29c among the flags stored in M29a can be changed. Therefore, you can set the value of the flag corresponding to the position on the screen where the character pattern you want to emphasize with a border is displayed to "1", or the position on the screen where the character pattern is displayed without the border because you do not want to emphasize it. The value of the flag corresponding to the flag can be set to "0".

The read side address port of the RAM 29b is connected to an address conversion circuit 29e. Further, the address conversion circuit 29e converts the row selection signal R and the digit selection signal C into
I am receiving this. Here, the address conversion circuit 29e is
In response to the row selection signal R, which determines the vertical position, and the column selection signal C, which determines the horizontal position, the address of a flag indicating the presence or absence of a border corresponding to the displayed character, that is, R.
Generate an address to AM29b. The value of the flag 29d specified by this address is “0” or “1”
is read out from the data output and output as a border presence/absence signal F.

Such a border presence/absence data storage circuit 29
The border presence/absence selection signal F generated by is transmitted to the serial conversion circuit 28. Then, depending on the value of "1" or "0" of the border presence/absence selection signal F, the serial conversion circuit 28 selects and outputs either the bordered display Z or the borderless display N. As a result, it becomes possible to selectively add a border for emphasis or display without a border.

Note that the above-mentioned border presence/absence data storage circuit 2
9 is an example using a dual port memory, but other configurations are also possible and will be described below. When a normal RAM is used as the memory, in addition to the above configuration, a circuit corresponding to the address selection circuit 6 may be provided between the interface 29a and address conversion circuit 29e and the RAM 29b. In this configuration, the operation is similar to that of the circuit shown in FIG. 2(b), except that writing from the microcomputer 1 to the RAM 29b is restricted while the border presence/absence signal F is being output.

If the display position of the bordering character is fixed in advance, the memory may be a ROM. At this time, since there is no need to write, the interface 29a is omitted and the ROM and address conversion circuit 29
A circuit is constituted by e. In this configuration,
The operation is similar to that of the circuit shown in FIG. 2(b), except that the flag indicating the presence or absence of a border is not dynamically changed.

When the display position of a character on the screen is determined so that the values of the row selection signal R and the digit selection signal C correspond to a multiple of a power of 2, part of the row selection signal R and the digit selection signal C It is also possible to connect the bit directly to the address input terminal of the RAM or ROM, thereby omitting the address conversion circuit 29e. This configuration also has the same effect as the circuit described above. In addition, when it is necessary to control only one specified row, the border control circuit includes an address register that receives and holds an address according to control and data signal B from the microcomputer, and an address and row selection signal output from this register. R
and a comparator that compares the value of and outputs it as a border presence/absence signal F. Although the border presence/absence data storage circuit, which is a feature of the present invention, has been described above, other operations are the same as those of the conventional example.

[0027]

[Effects of the Invention] As explained above, in the video display device of the present invention, by providing a border presence/absence data storage circuit, the presence/absence of a border is controlled for each character or line, and the date, time, etc. are displayed. This has the effect of allowing you to freely choose whether or not to emphasize text anytime and anywhere. Furthermore, by providing an independent border presence/absence data storage circuit, the timing of changing the character code to be displayed and the timing of specifying whether or not the character should be bordered can be set arbitrarily, which simplifies microcomputer programming. It also has the effect of getting away with something.

[Brief explanation of drawings]

FIG. 1 is a block diagram mainly showing a character video signal generation circuit portion of a video display device according to an embodiment of the present invention.

FIG. 2 shows an example (a) of a character pattern in a video display device and a border pattern generated from the character pattern surrounding dots on the top, bottom, left, and right sides, and a detailed block diagram of a border presence/absence data storage circuit that is a feature of the video display device of the present invention. b).

FIG. 3 is a diagram showing the configuration of a conventional video display device, particularly a block diagram of a character video signal generation circuit portion.

[Explanation of symbols]

1 Microcomputer 2 Write address register 3 Write data register 4 Write synchronization circuit 5 Display data RAM 6 Address selection circuit 7 Character generator 8 Serial conversion circuit 9 CRT 10 Horizontal address counter 11 Oscillation circuit 12 Vertical address counter 13 Character video signal generation circuit 23 Character video signal generation circuit 28 Serial conversion circuit 29 Border presence/absence data storage circuit

Claims (1)

[Claims] Claims: 1. A video display device having a serial conversion circuit for forming a border around a character pattern and serially outputting the border, including a border presence/absence data storage circuit that holds a flag indicating the presence or absence of a border for each character or for each line. , the border presence/absence data storage circuit receives a line selection signal that determines a vertical position on the screen and a digit selection signal that determines a horizontal position, and stores the data at an address specified by these signals. A flag is sent to the serial conversion circuit as a border presence/absence signal, and the serial conversion circuit selects and outputs either a bordered display or a borderless display according to the border presence/absence signal. Video display device.