JPS5928916B2 - Grid pattern generator for cathode ray tube display equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-screen cathode ray tube display device.

In particular, the present invention has a large screen of a first cathode ray tube on which all information is displayed, and a small screen of a second cathode ray tube on which a portion of all information displayed on the large screen is selectively extracted and displayed. The present invention relates to a cathode ray tube display device configured.

More specifically, the present invention divides a scanning line into a large number of picture elements, controls the brightness of each picture element, and uses a plurality of vertical and horizontal picture element matrices to display characters, figures, etc. The present invention relates to a cathode ray tube display device that forms an image and displays it on a screen.

Generally, this type of device has a one-on-one relationship with each of all picture elements on the screen.
The refresh memory (or pattern memory) corresponding to each storage address is read out in synchronization with the raster scanning of the cathode ray tube, and all information stored in this memory is displayed on the screen.

Writing and erasing of information displayed on the screen is performed directly on the screen using, for example, input keys or a light detection device called a light pen. Therefore, the present invention is a device for directly writing and erasing information on a screen using this light pen, and in which the well-known refresh memory as described above is combined with a first cathode ray tube with a large screen and a small one. It is provided in each of the screens and the second cathode ray tube, and is applied to a two-screen cathode ray tube display device in which two sets of large and small cathode ray tube display devices are used as one set.

In particular, the present invention is applied to an apparatus in which the mutual relationship between these two sets of large and small cathode ray tube display apparatuses is as follows.

In other words, this two-screen cathode ray tube display device displays only a portion of the total information displayed on the large screen, e.g.
Character-sized information is displayed on a small screen, and along with this, all information displayed on a large screen is displayed on the refresh memory (herein referred to as pattern memory for convenience) that corresponds to the first cathode ray tube. In other words, the refresh memory (referred to as character memory for convenience) that corresponds to the second cathode ray tube has a capacity corresponding to a picture element for one character. Furthermore, there is a mutual relationship in which one character's worth of adjacent information is transferred between the two memories using a light pen. Further, the present invention is applied to a two-screen cathode ray tube display device having a light pen that can directly write and erase data in one pixel unit on both the large and small screens.

Conventionally, when writing or erasing information directly on a screen using a light pen, the light pen first detects raster light, and when obtaining this detection output, the information on the screen is generally refreshed. The position of the light pen on the screen is determined by latching the count value of the address counter.

The count value of this address counter corresponds to the picture element on the screen. Therefore, when writing and erasing information on the screen pixel by pixel using a light pen,
The raster light that traverses the raster light sensing range or field of view of the light pen must be correspondingly very fine so that the position indicated by the light pen does not shift. On the other hand, in order to make the above-mentioned position determination accurate, it is necessary to make the detection output of the light pen stable. In order to stabilize the detection output of this light pen, it is desirable to widen the field of view of the light pen. Therefore, the field of view of a light pen is usually wide enough to detect several picture elements. As a result, the pixels are made even finer to increase the amount of information displayed on the screen, while the number of pixels detected by the light pen increases to stabilize the detection output. Therefore, even a slight shift of the light pen causes the above-mentioned count value for determining the position to change. Therefore,
Writing and erasing on a pixel-by-pixel basis has been difficult because its position tends to shift. In addition, the finer the picture elements and the denser the picture elements displayed on the screen, the more precise the movements of the hand that operates the light pen are required, but in reality, the hand cannot move with precision. Can not. As a result, the smaller the picture elements are made to increase the amount of information displayed on the screen, the more
Writing and erasing on a picture element basis has become difficult. In particular, if all the information displayed on the screen is, for example, 15 characters horizontally and 8 vertically, 248 dots (picture elements) horizontally and 192 vertical lines, as shown in Figure 1, One character is displayed within a block formed by 16 horizontal dots and 24 vertical lines, and when writing characters with fine lines such as kanji in this display area, the position of the light pen is determined by the angle of the pen, etc. This made it more likely to shift, making it difficult to write accurately.

The present invention has been made in view of this point, and includes a relatively small-sized second cathode ray tube display device that enlarges and displays picture elements for one character on the entire screen. In other words, the lines are corrected and then transferred to the display area for one character at an appropriate position on the first cathode ray tube screen where all information is displayed. It is an object of the present invention to provide a two-screen cathode ray tube display device in which display information on one cathode ray tube screen can be edited. Therefore, the purpose of the present invention is to:
An object of the present invention is to provide a cathode ray tube display device in which there is a relative relationship between the size of a pixel and the field of view of a light pen, and in which writing and erasing can be accurately performed in minute units of one pixel. It is in.

Another object of the present invention is to write and erase information directly on the first cathode ray tube screen on which all information is displayed, and to write and erase information directly on the first cathode ray tube screen on which all information is displayed, and to write and erase the displayed information as necessary in a plurality of regular picture element blocks, for example, one character. The information for each pixel block on the first cathode ray tube screen is enlarged and transferred to the second cathode ray tube screen, the image is corrected or new writing is performed on the second cathode ray tube screen, and any pixel block on the first cathode ray tube screen is transferred again. 2 that can be transferred to the display area
The object of the present invention is to provide a screen cathode ray tube display device. In addition, another object of the present invention is to clarify the transfer position on the first cathode ray tube when writing, erasing, or editing with a light pen, and to provide a guideline for writing across the entire display screen. In order to achieve this, a grid pattern dividing each picture element block is displayed on the screen of the first cathode ray tube.

A further object of the present invention is that when writing, erasing, or editing with a light pen, the detection position of the pen is disturbed by applying the light pen to the boundary between one picture element enlarged and displayed on the second cathode ray tube. In order to prevent this, a grid pattern is displayed on the screen of the second cathode ray tube to divide picture elements.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a block circuit diagram showing the configuration of an apparatus according to an embodiment of the present invention, in which 1 is a first cathode ray tube, 2 is a second cathode ray tube, 3 is a central processing unit (hereinafter simply referred to as CPU), 4 is a light pen, 5
is a key switch for applying a plurality of key inputs to the embodiment device as shown in FIG. The first cathode ray tube 1 also includes a well-known output amplifier 10, a pattern memory 11 in which all information displayed on the screen is stored, a parallel/serial data converter 12, (1) a bus buffer 13, ( 1
) The selector 14 and the first gate circuit 16 constitute a first cathode ray tube display section. The second cathode ray tube 2 includes an output amplifier 20, a character memory 21 in which all information displayed on the screen is stored, and a parallel/serial data converter 2.
2, (2) bus buffer 23, and (2) selector 24
and the second gate circuit 26 constitute a second cathode ray tube display section. The pattern memory 11 is connected to the first cathode ray tube 1.
There is a one-to-one correspondence between all picture elements on the screen and each storage address, and reading is performed in synchronization with raster scanning of the first cathode ray tube 1. As a result, the first cathode ray tube 1 refreshes and displays the information stored in the pattern memory 11 on the screen. Furthermore, data stored at each address of the pattern memory 11 is inputted and outputted via (1) a bus buffer 13, and address data is supplied from (1) a selector 14. On the other hand, in the character memory 21, each storage address has a one-to-one correspondence with each pixel on the screen of the second cathode ray tube 2, and reading is performed in conjunction with raster scanning of the second cathode ray tube 2. .
As a result, the second cathode ray tube 2 refreshes the information stored in the character memory 21 on the screen. The raster scanning of the second cathode ray tube 2 is synchronized with the raster scanning of the first cathode ray tube described above. Furthermore, the character memory 21 is such that data stored at each address is inputted and outputted via (2) a bus buffer 23, and address data is supplied from (2) a selector 24. Here, all the information displayed on the first cathode ray tube 1 is as shown in Fig. 1, and all the displayed pixels are divided periodically into 1 block of 16 x 24 dots. Take as an example.

Therefore, all picture elements displayed on the second cathode ray tube 2 are
As shown in the figure, it becomes 16×24 dots. In addition, here, patterns such as characters displayed on one block are shown in the diagonally shaded area in Figure 3, and the top and bottom three lines, a total of six lines, and the first one dot are used as margins to distinguish patterns between adjacent blocks. Part. Reference numeral 6 in FIG. 2 is a synchronization signal generator which generates a vertical synchronization signal (hereinafter simply referred to as VD) shown in FIG. , a horizontal synchronizing signal (hereinafter simply referred to as HD) shown in FIG. 6B, and a blanking pulse BK are generated and output. Further, 7 is a counter, and the dot clock CP(1) shown in FIG. The dot clock CP shown in B (
2) is created from the clock signal and output. 15 is a pattern address counter configured as shown in FIG.
The above-mentioned VD, . HDl dot clock CP(1) is input, and HD is input to Y(1) counter 151 with VD as reference.
By counting with , the 8-bit parallel diagrams E-L in FIG. Memory (1) Y address data shown in (1) is supplied to (1) selector 14 and (1) latch circuit 41.

At the same time, this pattern address counter 15 counts the dot clock CP(1) (for example, 5.73 MHz) in FIG. 8-bit parallel memory (1)X shown in FIG.
Address data is supplied to (1) selector 14 and (1) latch circuit 41. 25 is a character address counter, and in FIG. 2, the above-mentioned VD. Although the HD and dot clock (2) are shown as being input respectively,
Here, as shown by the same reference numerals in FIG.
A case is shown in which only the X(2) counter 251 outputs X address data.

That is, in principle, the character address counter 25 stores 8-bit parallel memory (2) Y address data and 8-bit parallel memory (2) Y address data.
Bit parallel memory (2) 2) Since the Y address data can be used in common with the memory (1) Y address data shown in FIG. 6 EL described above, the character address counter 25 is configured as described above.
Therefore, as shown in FIG. 5, the 8-bit parallel memory (1) Y address data is given to the character address counter 25 as memory (2) Y address data by the pattern address counter 15, and is directly transferred to the (2) selector. 24 and (2) the latch circuit 42. on the other hand,
X(2) counter 2 of character address counter 25
51 counts the dot clocks CP(2) shown in FIG. 8B with the HD as a reference, outputs 8-bit parallel data C-J in FIG. 8, and stores I in the memory (2). Supplied as X address data to (2) selector 24, F,
G and H are supplied to (2) the latch circuit 42, respectively. As described above, each picture element on the screen of the first and second cathode ray tubes 1 and 2 and the memory (1
) and (2) X and Y address data are output from the pattern address counter 15 and character address counter 25, respectively.

Next, an example for projecting a grid pattern on the screens of the first and second cathode ray tubes 1 and 2 will be described.

First, the above-mentioned 8-bit parallel memory (
1) The lower four bits of the X address data shown in FIG. 7 D, E, F, and G are supplied to the X(1) decoder 153.

This decoder 153 outputs one pulse when all the lower three bits of D, E, and F in FIG. When the panorez of the fourth lower bit in FIG. 7G is 110!1, a gate is applied to extract a pulse as shown in FIG. 7M. This extracted pulse is controlled by an X(1) display gate pulse as shown in FIG. In this case, an X(1) lattice signal representing a total of 15 divisions in the X direction of the screen as shown by 9 to O in FIG. 7M is obtained. As mentioned above, this corresponds to the setting of the screen display format of the first cathode ray tube 1 as 15 characters per line as shown in Figure 1; , the number of divisions of the above-mentioned X(1) lattice signal is also changed to 20. Here, in FIG. 7, A represents HD, and B represents X(1) created based on this HD.
It represents the counter 152 reset signal. on the other hand,
The Y(1) grid signal for forming a grid pattern in the horizontal direction of the screen of the first cathode ray tube 1 is created as follows.

As already mentioned, the screen is divided into eight parts in the vertical direction based on the display format shown in FIG. Also, set the entire display in the Y direction to 1
An example of a configuration with 92 lines is illustrated. Therefore, if one pulse is created for every 24 lines when counting 192 lines, a total of 8 Y(1) grating signals will be obtained. As a result, the pulse generation circuit 1 shown in FIG.
54 to obtain a Y(1) display gate pulse as shown in FIG. A Y(1) lattice signal as shown in FIG. 7M is created by decoding in the Y(1) decoder 156. Such an X(1) lattice signal and a Y(1) lattice signal are added by an OR gate circuit 157 and outputted from a terminal 17.

This terminal 17 is connected to (1) gate circuit 1 as shown in FIG.
Connected to 6. This (1) gate circuit 16 is (1)
From the parallel/serial data converter 12 (1) Output amplifier 10
A gate is applied to the brightness control signal of the picture element on the screen supplied to the screen based on the above-mentioned X and Y(1) lattice signals.
As a result, a grid pattern in the display style shown in FIG. 1 is projected on the screen of the first cathode ray tube 1. next,
An example of a method for creating X and Y(2) grid signals for projecting a grid pattern on the screen of the second cathode ray tube 2 will be described below.

As already mentioned, the picture elements displayed on the second cathode ray tube 2 are composed of a total of 24 pixels in the Y direction of the screen based on the format shown in FIG.

If the entire display in the Y direction of the screen is composed of 192 lines as in the case of the first cathode ray tube 1, if one pulse is created every 8 lines when counting 192 lines, a total of 24 Y ( 2) A grid signal is obtained. Therefore, as shown in FIG. 5, among the 8-bit parallel memory (1) and (2) Y address data of FIG. 6 E to L, which is the output of the Y(1) counter 151, ,F,G
The lower three bits of the Y(2) decoder 253 are branched and supplied to the Y(2) decoder 253. The Y(2) decoder 253 outputs 1 when the lower three pits shown in FIG. 6 E, F, and G all become 1T11V.
A total of 24 Y (
2) Output a grid signal. On the other hand, the X(
2) A grid signal is created as follows.

First, as already mentioned, the picture elements displayed in the X direction on the screen of the second cathode ray tube 2 are divided into 16 pixels based on the display format shown in FIG. Therefore, as shown in Figure 5,
Among the 8-bit parallel outputs C-J in FIG. 8 of the X(2) counter 251, the lower three bits of C, D, and E in FIG. This X (
2) The decoder 252 detects that the lower 3 bits mentioned above are all 1"
When , one pulse is created, and a total of 16 pulses are generated as shown in FIG.
Outputs an X(2) lattice signal divided into X(2) lattice signals. here,
FIG. 8A is created based on HD using the already mentioned X(2) counter 251 reset signal. In addition, the display gate pulse in FIG. 8L is determined from the rising edge of the reset signal in FIG. 8B.
It is generated by a circuit (not shown) by counting the clock signal CP(2) shown in FIG. Such X(2
) lattice signal and Y(2) lattice signal are the OR gate circuit 254
are added and output from terminal 27.

This terminal 27 is connected to the (2) gate circuit 26 shown in FIG. This (2) gate circuit 26 is (2) parallel/
A gate is applied to the brightness control signal of the picture element on the screen supplied from the serial data converter 22 to the (2) output amplifier 20 based on the above-mentioned X and Y (2) grid signals. As a result, a grid pattern in the display style shown in FIG. 3 is projected on the screen of the second cathode ray tube 2. As described above, the pattern address counter 15 and the character address counter 25 each output memory (2) X and Y address data, and output X and Y (1) and (2) X and Y address data.
2) The grating signals are generated by the first grating signal generating means 150 and the second grating signal generating means 250, respectively.

By the way, the above-mentioned (1) selector 14 and (2) selector 24 are connected to the address bus AB from the CPU, which will be described later, as the other input.

The (1) and (2) selectors 14 and 24 select one of the two inputs using the blanking pulse BK.

That is, during the screen refresh display period, in other words, during the non-blanking period, (1) the selector 14 selects the memory (1) X and Y address data input from the pattern address counter 15 and stores the pattern memory 1
Supply to 1. Also, during a similar period, (2) selector 24 receives data from memory (2) X from character address counter 25.
and Y address data input are selected and supplied to the character memory 21. At this time, (1) bus buffer 13 and (2) bus buffer 23 are not chip-selected, so the bus and port facing data bus DB are maintained at high impedance. Therefore, during the above display period, the memory (1) X and Y address data supplied from the pattern address counter 15 is given to the pattern memory 11 via the (1) selector 14. The data at the storage address (here, data in 8-bit units) is output to the data bus.

Similarly, the character memory 21 is given the memory (2) data) is output to the data bus. The data outputted on these data buses 12 and 2 are loaded into shift registers forming parallel/serial converters 12 and 22, respectively, in a well-known manner, from which one picture is output by dot clocks (1) and (2), respectively. Read out in elementary units.

As a result, the data read out becomes screen display data of serial picture element arrays. This display data is based on output amplifiers 110 and 2 for driving a well-known cathode ray tube.
0, the light is supplied to the cathodes of the first and second cathode ray tubes 1 and 2, and is displayed as a bright spot on the screen. When the power is turned on, all parts of the apparatus of this embodiment are set to the initial state, and thereafter the key switch 5 as shown in FIG. 4 is turned on.
Control processing of each part is started using the key input and the light pen 4.

Therefore, the main routine of the CPU 3 is programmed to be based on key input. The key inputs shown in Fig. 4 are 11 large 17 and ``small'' screen key switches and ``write'', 6'' display - ! 1 edit 1!, which are independent of each other, and one of the two switches is selected from each other. be done.

Also, when one of the key switches on the 11 large f1 and 11 screens is selected, the other is released. and,!
The write, display, and edit key switches are also configured to be alternatively pressed to release the others. Therefore, when these switches are pressed, they instruct the device to execute the processing in the corresponding mode. The key switch 5 shown in FIG. 2 switches the CPU in response to such key input.
3. Instructs the processing content to be executed. That is, here, first, when the key switch 5 is pressed, a key input flag is set, and the main routine of the CPU is set in advance to search for this flag, and the binary code data of the corresponding switch translated by the encoder 51 is sent (6). The data is taken into the CPU 3 via the bus buffer 52 and data bus DB. The CPU 3 determines which key is to be input based on this data and executes the input. The key inputs given to the CPU 3 are organized as follows. First, when writing directly on the screen of the first cathode ray tube 1 with the light pen 4, press the key switch of 11 large screen 1W shown in FIG. By applying it to the screen of the cathode ray tube 1, writing is performed on the corresponding picture element. In addition, when writing on the screen of the second cathode ray tube 2, the above-mentioned "\Screen 11
All you have to do is press the key switch, and the rest will be done in the same way. As mentioned above, this is because the 1-write 16 key switch maintains its previous state. Next, if you want to transfer the information drawn on the screen of the second cathode ray tube 2 to the screen of the first cathode ray tube 1, first press the "Small Screen" key switch, then press the "Edit" key switch, By applying the light pen 4 to the screen of the first cathode ray tube 1, the image of the second cathode ray tube 2 is transferred to the block at the position indicated by the light pen 9.

Conversely, when transferring one flock image on the screen of the first cathode ray tube 1 to the second cathode ray tube 2, press the key switch for the large screen 11, press the key switch 11 for editing 11, and press the light pen 4 to a desired block on the screen of the first cathode ray tube 1.

Of course, at this time, there is no need to press the key switch 11 edit 11 as described above. Based on the key inputs for the operations described above, the CPU 3 controls each part, and
Various types of data coming on the data bus DB and address bus AB are processed, and since the operation of each part is almost the same as the writing operation to the character memory 21, this will be explained below.

When the light pen 4 is applied to the screen of the cathode ray tube, it detects raster light scanning the screen in a well-known manner and generates pulses.

Therefore, the sensing output or pulse output from the light pen 4 is generated when the raster light passes within the field of view. As already mentioned, the character address counter 25 stores the memory (2) X and Y address data (1
) Since it is applied to the latch circuit 42, this light pen 4
latches the address data supplied when receiving the detection output from.

This memory (2) X and Y address data indicates the horizontal and vertical positions of picture elements on the screen, so (2)
) The data latched by the latch circuit 42 is sent to the light pen 4.
This data indicates the location on the screen where the . (2)
The data latched by the latch circuit 42 sends character memory address data specifying the storage address of the corresponding character memory 21 to the bus buffer 43 (5), and transfers write data to the character memory 21 to the decoder 4 (318).
4 and then to the bus buffer 45 (4). The memory address data and write data are configured as follows.

First, the character memory address data is 1?8 dots out of a total of 16 dots in the X direction of the screen as a unit, as shown by the diagonal line A in Figure 3. D-3? It is constructed by sequentially corresponding to positions on the screen in the direction of D. In other words, the character memory address data consists of 1 bit indicating whether it is on the left or right half of the screen as '0' or '1', and 5 bits indicating which line out of a total of 24 lines it is on. It is. Next, the data to be written to the character memory 21 is written as the character memory address data circulates in units of 8 dots, which are 16 dots divided into two as described above.
Any data that determines which position among these 8 dots is sufficient.

Therefore, (4) the write data to the character memory 21 that is supplied to the bus buffer 45 is data in which only 1 bit out of 8 bits is set to 1. Therefore, (2) the latch circuit 42 Of the latched memory (2) X and Y address data, the lower 3 bits of the X address data are converted by the 3→8 decoder 44 into 8 bit data corresponding to the 8 dots on the screen as described above. (4) bus buffer 45. Such (4) bus buffer 45 and (5) bus buffer 43 are opened by a command from CPU 3, and each of the above-mentioned write data and character memory address data is Put it on the data bus DB.

The command from the CPU 3 here consists of 16-bit parallel address data, and is output to the address bus AB. For example, if (5) address data for selecting bus buffer 43 is output to address bus AB, this address data is transferred to (2) address decoder 32.
(5) bus bus 4 via track 451.
Let 3 open. (5) The timing of opening the bus buffer 43 is performed at the same time as the timing of reading the memory. The CPU 3 (5) opens the bus buffer 43, takes in the memory address data carried on the data bus DB, and stores it in a predetermined built-in register. On the other hand, (4) Bus Batsuhua 45 was also opened in the same way as Dojo,
The CPU 3 takes in the write data on the data bus DB and stores it in a predetermined built-in register.

This operation of the CPU 3 is performed in a short period of time.
Based on this captured memory address data, the CPU 3 outputs memory address data representing the corresponding storage address of the character memory 21 to the address bus AB, and this data is supplied to the character memory 21 via the (2) selector 24. be done.

At this time, the CPU 3 sends a memory write control signal to the line 3 indicating the writing timing of the character memory 21.
11 to the read/write terminal of the character memory 21 to put the memory in a writing state. At the same time, (2) the bus buffer 23 is opened, and the write data stored in the CPU 3 described above is supplied to the character memory 21 via the data bus DB. Writing to the character memory 21 is completed in the above manner, but instructions for writing and reading this memory are issued by the CP.
This is done by the command of U3.

This command from the CPU 3 is executed during the blanking period, taking into consideration that refresh data and external write data do not collide on the data bus DB. Therefore, this writing/reading operation of the character memory 21 is repeated 24 (lines)×2 times. Also, if a color display device using a color cathode ray tube is used, red, green,
This will be repeated 24×2×3 times, each corresponding to blue. The writing operation of the character memory 21 has been described above, but the writing operation of the pattern memory 11 is also performed in the same way.

In this case, the light pen 5 is applied to the screen of the first cathode ray tube 1 as described above, but (1) the latch circuit 4
1. (7) Bus buffer 46, 3/8 decoder 47, (
6) The operations of the bus buffer 48 and the CPU 3 are similar to those of the character memory 21 described above, so the details will be omitted. Next, an explanation will be given of the operation when information drawn on the screen of the second cathode ray tube 2 by writing as described above is transferred to the screen of the first cathode ray tube 1.

In this case, as already mentioned, CPU3 has 11 small screens 1! and 17 Edit 7] are given key inputs using a key switch. CP by key input of "Small screen" → "Edit"
As already mentioned, the operation of U3 is such that the detection output of the light pen 5 is transferred to the memory (1)X of the pattern address counter 15.
The program is configured to (1) cause the latch circuit 41 to latch the and Y address data, and (6) take in the address data and write data of the pattern memory 11 from the bus buffer 48 and (7) the bus buffer 46. On the other hand, the CPU 3 is provided with pattern memory address data that is regularly divided into predetermined blocks in advance, and when it receives the key input of ``1 Edit'' 6, it executes a predetermined routine that has been set up in advance (7) Bus buffer 46 It calculates to which block the memory address data taken in belongs to and outputs it to the address bus AB as block address data. As a result, the pattern memory 11 is addressed in blocks of corresponding storage addresses. Here, this 1 block is the 1st block here.
As shown in the figure, it is shown as being divided into one character of 24 lines and 16 dots. Therefore, when the key input 11 edit 11 is given to the CPU 3 and the light pen 5 is applied to the screen of the first cathode ray tube 1, the pattern memory address data indicating the position in units of 1 bit is transferred from the bus buffer 46 to the CPU 3 (7). It is taken in and stored.

Then, as described above, the CPU 3 stores the pattern memory 11 corresponding to the block to which the position indicated by the light pen belongs.
The data stored in the character memory 21 is sequentially transferred to the storage address of. At this time, the transferred data in the character memory 21 is written to the pattern memory 11 via the data bus Niro-DB-Iha. The operations of each unit controlling the data transfer and the flow of address data as described above are executed by instructions output from the CPU 3 to the address bus AB.

This order of execution is determined by a routine preset in the CPU 3. The case where the image of the second cathode ray tube 2 is transferred to the first cathode ray tube 1 has been described above, but each part operates in the same way in the reverse case as well.

In this case, input the keys on screen 11 to 11 large screen 1.
1 key input, and press the first cathode ray tube 1 in the same way as above.
This is carried out by applying the light pen 5 to the block to be transferred. The above-described key switch operation can be changed as appropriate by changing the routine set in the CPU 3. Therefore, 1゛ big screen - ゛! Even if a single switch is used instead of the key switch of the small screen 1 to instruct the transfer from the character memory 21 to the pattern memory 11 or vice versa, this does not affect the spirit of the present invention. .
Although the present invention has been described above with reference to a black and white cathode ray tube display device, the present invention can also be applied to a color cathode ray tube display device.

In this case, the memory capacity may be tripled for red, green, and blue, and the same operation as described above may be performed for each of the three primary colors. Furthermore, the grid signal generating means 150 and 250 described above are used to write 11 of the key inputs described above.
The gate circuits 16 and 26 are operated when the key input of 1 is made, and otherwise the gate circuits 16 and 26 operate as parallel/serial data converters 12 and 2.
2 is simply passed to the output amplifiers 10 and 20.

Therefore, the lattice pattern displayed on the first and second cathode ray tubes 1 and 2 is displayed only when the "!Write i1" key is input. Although the description has been made with reference to a device capable of writing, erasing, and transferring information using a pen, the present invention is not limited to such a device. Instead of using one character as in
It is divided into blocks of appropriate size, and all the information of blocks of this size is enlarged and displayed on a second cathode ray tube,
The cathode ray tube display device can have a two-screen configuration in which the user can partially enlarge any information on the first cathode ray tube screen to make it easier to see.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the display format of the first cathode ray tube of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the device of the present invention, and FIG. 3 is a display of the second cathode ray tube of the present invention. FIG. 4 is a diagram showing an example of the configuration of the key input means of the present invention, FIG. 5 is a block diagram showing the configuration of the main part of the device of the present invention, and FIG. A time chart showing the generation process of the grid signal in the Y direction of the screen of the second cathode ray tube, FIG. 7 is a time chart showing the generation process of the grid signal in the screen X direction of the first cathode ray tube, and FIG. 8 is a time chart showing the generation process of the grid signal in the screen X direction of the first cathode ray tube. 3 is a time chart showing the generation process of a grid signal in the X direction of the screen. 15...First counter, 25...Second
Counter, 155, 156...First horizontal grid signal generation means, 153...First vertical grid signal generation means, 2
53... Second horizontal grid generating means, 252...
Second vertical grid generating means, 16...first circuit means,
26...Second circuit means.

Claims (1)

[Claims] 1. Information for one block out of a plurality of information blocks obtained by equally dividing all the information displayed on the screen of the first cathode ray tube is enlarged and displayed on the screen of the second cathode ray tube, In a cathode ray tube display device having a two-screen configuration in which information displayed on the first and second cathode ray tubes can be rewritten and mutually transferred,
a first counter that counts the number of scanning lines included in one information block of the first cathode ray tube as one unit; and at least one pulse is generated at each counting time of the first counter; a first horizontal grid signal generating means for outputting a plurality of pulses during a vertical display period of all the information displayed on the screen; and counting the number of picture elements included in one information block of the first cathode ray tube as one unit. a second counter;
a first pulse producing at least one pulse at each counting time of the second counter and outputting a plurality of pulses during a horizontal display period of all information displayed on the first cathode ray tube;
vertical grid signal generating means, and when rewriting or transferring the display information, the luminance of picture elements displayed on the first cathode ray tube is adjusted according to pulses output from the first vertical and horizontal grid signal generating means; a first circuit means for constant control; and a first circuit means for dividing the total number of scanning lines included in a vertical display period of all information displayed on the second cathode ray tube by the count value of the first counter; At least 1 at the time of vertical scanning of the scanning line at the position corresponding to the division value in synchronization with the vertical scanning of the tube.
a second horizontal lattice signal generating means for outputting pulses, and dividing the total number of pixels included in a horizontal display period of all information displayed on the second cathode ray tube by the count value of the second counter; a second vertical grid signal generating means for outputting at least one pulse at the time of horizontal scanning of a pixel at a position corresponding to the division value in synchronization with horizontal scanning of the second cathode ray tube; and rewriting the display information. or second circuit means for controlling the brightness of picture elements displayed on the second cathode ray tube to be constant in accordance with pulses output from the second vertical and horizontal grid signal generating means when transferring. A grid pattern generator for a cathode ray tube display device, characterized in that: