JPH04363907A - Electronic tuning receiver - Google Patents

Abstract

PURPOSE:To facilitate the adjustment of a tracking error, to relieve the limitation with respect to component arrangement, to improve the degree of freedom of design and to facilitate the setting of a sweep stop level at automatic channel selection of the receiver. CONSTITUTION:The receiver is provided with a storage means 18 storing information with respect to an applied voltage to a voltage variable reactance element to minimize a tracking error and a control means 16 which discriminates whether or not a reception frequency is a frequency stored in the storage means 18, applies the information stored in the storage means 18 to the voltage variable reactance element when the reception frequency is equal to the frequency stored in the storage means 18, obtains the information relating to the applied voltage to the voltage variable reactance element at the reception frequency based on the information corresponding to the frequency stored in the storage means 18 in the vicinity of the reception frequency when the reception frequency differs from the frequency stored in the storage means 18 and applies the information to the voltage variable reactance element. Furthermore, the information relating to a high frequency signal level to implement the sweep stop operation at the automatic channel selection is stored in the storage means 18.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronically tuned receiver using a voltage variable reactance element in a tuning circuit.

0002

2. Description of the Related Art Conventionally, an electronic tuning receiver using a voltage variable reactance element in a tuning circuit is known.

In this type of electronic tuning receiver, tracking errors occur due to the characteristics of voltage variable reactance elements such as voltage variable capacitance diodes used in the high frequency tuning circuit and local oscillation circuit.

[0004] When a tracking error occurs in this way,
Variations in reception sensitivity occur, resulting in problems such as, for example, broadcasting stopping at an undesirable broadcast frequency during automatic tuning.

Therefore, in the past, variable inductance coils, trimmer capacitors, etc. were provided in the high frequency tuning circuit and local oscillation circuit, and tracking errors were eliminated by adjusting the variable inductance coils, trimmer capacitors, etc. during the manufacture of electronically tuned receivers. I'm trying to keep it small.

[0006] In addition, automatic tuning receivers generally detect a high frequency signal level at which practical reception quality can be obtained, and further accurately detect intermediate frequencies, so that the sweep can be stopped during automatic tuning. I have to.

[0007]

[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, since it is necessary to make adjustments to reduce tracking errors when manufacturing the receiver, it is necessary to arrange the tuning circuit at a location where adjustment is easy. The problem was that the degree of freedom in design was reduced due to restrictions.

Furthermore, since the adjustment work is performed manually, the adjustment accuracy is insufficient and the time required for adjustment is long, resulting in poor efficiency.

Furthermore, detection of the high-frequency signal level necessary for the sweep stop operation during automatic tuning requires adjustment on each receiver to correct for variations in receiver sensitivity, and many receivers This was an issue during production.

0010

[Means for Solving the Problems] In view of the above points, the present invention provides an electronically tuned receiver using a voltage variable reactance element in a tuning circuit, which supports an arbitrarily selected frequency within a reception band. storage means for storing information regarding the voltage supplied to the voltage variable reactance element that minimizes the tracking error at the frequency; and a storage means for controlling the reception frequency and determining whether the reception frequency is the frequency stored in the storage means. If the reception frequency is the frequency stored in the storage means, the information stored in the storage means is supplied to the voltage variable reactance element, and the reception frequency is the frequency stored in the storage means. When different, information regarding the voltage to be supplied to the voltage variable reactance element at the reception frequency is obtained based on information corresponding to a frequency stored in the storage means near the reception frequency, and the information is supplied to the voltage variable reactance element. It is characterized by comprising a control means.

The present invention is also characterized in that the storage means is configured to store information regarding the high frequency signal level for performing a sweep stop operation during automatic channel selection.

0012

[Operation] According to the present invention, when tuning, it is determined whether the received frequency and the frequency stored in the storage means match, and when both frequencies match, the information stored corresponding to the frequency is transferred to the voltage variable reactance. The signal can be received with minimal tracking error.
Further, when the reception frequency and the frequency stored in the storage means are different, information regarding the voltage supplied to the voltage variable reactance element at the reception frequency is based on information corresponding to a frequency stored in the storage means near the reception frequency. This information is then supplied to the voltage variable reactance element, thereby making it possible to receive the information with less tracking error.

Further, according to the present invention, information regarding the high frequency signal level for performing the sweep stop operation during automatic channel selection is stored in the storage means, so that the sweep stop level can be easily set. .

[0014]

Embodiment FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, 1 is an antenna, 2 is an antenna tuning circuit including a voltage variable capacitance diode, 3 is a high frequency amplifier circuit including a voltage variable capacitance diode, and 4 is a local oscillation circuit.
The LL circuit includes a voltage controlled oscillator (VCO) 5 that includes a voltage variable capacitance diode and outputs a local oscillation signal, and this VCO.
A programmable frequency divider 6 that divides the output signal from the CO5 by N, a phase comparator 8 that compares the output signal from the programmable frequency divider 6 with an oscillation signal from the reference oscillation circuit 7, and this phase comparator. The low-pass filter 9 is supplied with an output signal from the VCO 8 and supplies a control voltage to the VCO 5 based on the output signal. 10 is a high frequency amplifier circuit 3
11 is an intermediate frequency amplification circuit that amplifies the intermediate frequency signal from the mixing circuit 10; 12 is an intermediate frequency amplification circuit from the intermediate frequency amplification circuit 11; 13 is a stereo demodulation circuit for stereo demodulating the detected signal from the detection circuit 12; 14 is a detection circuit for detecting an intermediate frequency signal of
15 is a level detection circuit that detects the level of the intermediate frequency signal and outputs a signal corresponding to the level, and 15 is a first circuit that converts the output signal from the level detection circuit 14 into a digital signal.
The AD conversion circuit 16 is a control circuit which outputs frequency division ratio data to the programmable frequency divider 6 constituting the PLL circuit 4 and is supplied with a digital signal from the AD conversion circuit 15. Consists of. 17 is a second AD conversion circuit that converts the signal output from the low-pass filter 9 constituting the PLL circuit 4 into a digital signal; 18 is a memory that stores digital information regarding the voltage supplied to the variable capacitance diode; 19 is a key input section for inputting signals to the control circuit 16 for issuing channel selection commands, etc.;
20 is a first DA conversion circuit that converts the digital information supplied from the control circuit 16 into an analog signal (DC voltage) and supplies it to the variable capacitance diode provided in the high frequency amplifier circuit 3; 21 is a first DA conversion circuit supplied from the control circuit 16; The second DA converts the digital information into an analog signal (DC voltage) and supplies it to the variable capacitance diode provided in the antenna tuning circuit 2.
It is a conversion circuit.

[0015] The memory 18 stores information on the supply voltage to the variable capacitance diode provided in the antenna tuning circuit and the high frequency amplification circuit, which minimizes the tracking error at an arbitrarily selected frequency within the reception band. Associated digital information is stored corresponding to the frequency.

The operation of storing information in the memory 18 will be explained.

First, the circuit is designed so that the voltage supplied to the variable capacitance diode of the antenna tuning circuit 2 and the high frequency amplifier circuit 3 is approximately the same as the voltage supplied to the variable capacitance diode of the VCO 5 within the reception band. Set each constant.

Next, a high frequency signal with a small to medium electric field strength is supplied as an antenna input so that the level detection circuit 14 can detect the level. It is assumed that the frequency of this high-frequency signal is changed when adjusting the reception frequency of the receiver.

When the receiver is controlled to tune to an arbitrary frequency F within the reception band by operating the key input section 19,
The control circuit 16 supplies frequency division ratio data corresponding to the frequency F to the programmable frequency divider 6 of the PLL circuit 4, and
The oscillation frequency of CO5 is controlled to be F+FIF or F-FIF. Here, FIF is the frequency of the intermediate frequency signal.

When the VCO 5 locks to its oscillation frequency, the second AD conversion circuit 17 converts the control voltage to the VCO 5 into a digital signal and supplies it to the control circuit 16.
The control circuit 16 transmits this digital signal to the first and second DA
is supplied to the conversion circuit, and furthermore, at this time, the first AD conversion circuit 1
The digital information regarding the received electric field strength supplied from 5 is stored in the memory 18.

Next, the value of the digital signal supplied to the first DA conversion circuit 20 is fixed, and the value of the digital signal supplied to the second DA conversion circuit 21 is changed from the previously set value to the + side and - side. By slightly changing the value of the digital signal from the first AD conversion circuit 15 (i.e., the received electric field strength), the value of the second DA conversion circuit 21 when the output value from the first AD conversion circuit 15 becomes the maximum is determined. and stores it in the memory 18 in association with the reception frequency.

Thereafter, the value of the digital signal supplied to the second DA conversion circuit 21 is fixed to the value stored in the memory 18 by the above operation, and the value of the digital signal supplied to the first DA conversion circuit 20 is fixed in the same manner as described above. Slightly change the value to the + and - sides. As a result, the value from the first DA converter circuit 20 when the output of the first AD converter circuit 15 becomes maximum is determined, and this value is combined with the previously stored receiving frequency and the second DA converter circuit 20.
It is stored in the memory 18 in association with the value of 1.

The above operation is performed for each arbitrarily selected frequency within the reception band, and the values of the second DA conversion circuit and the first DA conversion circuit are stored in the memory 18 in association with the respective frequencies at that time.

For example, as shown in FIG. 2, five frequencies (F1, F2, F3, F4, F5) are selected within the reception band, the above operation is performed for each frequency, and the correction data (D
1, D2, D3, D4, D5) are stored in the memory 18.

Next, the reception operation in the present invention will be explained.

Now, when the preset key of the key input unit 19 is operated to receive broadcast station A (frequency F3), for example, the control circuit 16 is operated to receive broadcast station A (frequency F3).
The frequency dividing ratio data corresponding to
It is controlled to oscillate at the frequency of F, and it is determined whether the specified frequency is the frequency stored in the memory 18 or not. In this case, since the frequency is stored, the value of the first DA conversion circuit 20 and the value of the second DA conversion circuit 21 stored in the memory 18 corresponding to this frequency are read out, and the values of the first DA conversion circuit and the second DA conversion circuit are supply

[0027] In this way, the tracking error is automatically set to the minimum state, and reception can be performed with good reception sensitivity.

[0028] Broadcasting station B (frequency F6, F1<F
6<F2), the control circuit 16 transmits frequency division ratio data corresponding to broadcast station B to the programmable frequency divider 6.
to supply PLL circuit 4 to F6-FIF or F6+
It is controlled to oscillate at the frequency of the FIF, and it is determined whether the specified frequency is the frequency stored in the memory 18 or not. In this case, since it is not stored, the correction data (D1 and D2 in this case) corresponding to the frequencies located above and below the received frequency among the frequencies stored in the memory 18 are read out, and, for example, After calculating the correction data at the reception frequency by taking the average of both, the calculated correction data is sent to the first DA conversion circuit 2.
0 and the second DA conversion circuit 21.

Therefore, in this case as well, a state with less tracking error is automatically set, and reception can be achieved with good reception sensitivity.

By the way, in the above embodiment, the case where it is applied to an FM receiver has been explained, but it goes without saying that it can also be applied to an AM receiver, and the number of frequencies stored in the storage means is limited to five. It's not something you can do.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the embodiment shown in FIG. 3, when compared with the block diagram shown in FIG.
Only locations that directly supply are added.

Next, the operation of the embodiment shown in FIG. 3 will be explained. Note that since the operation in FIG. 3 is basically the same as the operation in FIG. 1, a description of the operations that have already been described will be omitted.

[0033] Antenna tuning circuit 2 and high frequency amplification circuit 3
After adjusting the above method to minimize the tracking error, set the sweep stop level during automatic channel selection. In this case, a high frequency signal corresponding to a desired high frequency signal level at which the sweep is to be stopped is supplied as an antenna input from a signal generator or the like. Then, the intermediate frequency signal level at that time is detected by the level detection circuit 14, and the first
It is supplied to the control circuit 16 via the AD conversion circuit 15, and the digital information regarding the received electric field strength supplied from the first AD conversion circuit 15 at this time is stored in the memory 18.

Next, the receiving operation will be explained.

Now, when the automatic sweep key of the key input section 19 is operated to perform an automatic sweep operation, it is determined whether the high frequency signal level at each sweep frequency is equal to or higher than a predetermined sweep stop level. . That is, information regarding the intermediate frequency signal level corresponding to the desired high frequency signal level at which the sweep is to be stopped is read from the memory 18, and the digital signal regarding the intermediate frequency signal level read from the memory 18 and the intermediate frequency signal level from the intermediate frequency amplifier circuit 11 are read from the memory 18. A digital signal related to the intermediate frequency signal level at each sweep frequency obtained through the level detection circuit 14 and the AD conversion circuit 15 is compared in the control circuit 16, and the intermediate frequency signal level at each sweep frequency is stored in the memory 18. It is determined whether the intermediate frequency signal level is higher than a stored predetermined intermediate frequency signal level (sweep stop level).

If the intermediate frequency signal level at each sweep frequency is equal to or higher than a predetermined sweep stop level, furthermore, in order to more accurately stop the automatic sweep operation, the intermediate frequency signal level is sent directly from the intermediate frequency amplifier circuit 11 to the control circuit 16. The control circuit 16 determines whether the intermediate frequency of the input intermediate frequency signal is accurate. As a result of the above judgment, the sweep operation during automatic channel selection is stopped only when two judgment conditions are simultaneously satisfied: the intermediate frequency signal level (high frequency signal level) is equal to or higher than a predetermined level, and the intermediate frequency is accurate. .

Furthermore, in the embodiment of FIG. 3, information regarding the intermediate frequency signal level corresponding to the desired high frequency signal level at which the sweep is to be stopped is stored in the memory 18, but this is generally performed by intermediate frequency amplification. The level detection circuit for the intermediate frequency signal is built into the integrated circuit containing the circuit.
This is to take advantage of this. Therefore, a circuit for detecting the high frequency signal level may be separately provided, and information regarding the desired high frequency signal level at which the sweep should be stopped may be obtained from the high frequency signal level detecting circuit and stored in the memory.

[0038]

According to the present invention, there is provided an electronically tuned receiver using a voltage variable reactance element in a tuning circuit, in which the tracking error at an arbitrarily selected frequency within the reception band is reduced. storage means for storing information regarding the supply voltage to the voltage variable reactance element that minimizes the voltage, and controlling the reception frequency;
It is determined whether the receiving frequency is the frequency stored in the storage means, and when the reception frequency is the frequency stored in the storage means, the information stored in the storage means is supplied to the voltage variable reactance element. , when the reception frequency is different from the frequency stored in the storage means, information regarding the voltage supplied to the voltage variable reactance element at the reception frequency is obtained based on information corresponding to a frequency stored in the storage means near the reception frequency. In addition, since the information is provided with a control means for supplying the information to the voltage variable reactance element, it is possible to always receive the information with minimal tracking error. Further, since the tracking error can be adjusted electronically, the adjustment accuracy is improved, and restrictions on component placement can be reduced, and the degree of freedom in design is improved.

Furthermore, the present invention is configured such that the storage means stores information regarding the high frequency signal level for performing the sweep stop operation during automatic tuning, so that the adjustment of the sweep stop level during automatic tuning is possible. becomes easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of an electronically tuned receiver of the present invention.

FIG. 2 is a diagram for explaining the present invention.

FIG. 3 is a block diagram showing another embodiment of the electronically tuned receiver of the present invention.

[Explanation of symbols]

2 Antenna tuning circuit 3
High frequency amplifier circuit 14 Level detection circuit 16 Control circuit

Claims (2)

[Claims] 1. An electronically tuned receiver using a voltage variable reactance element in a tuning circuit, wherein the voltage corresponds to an arbitrarily selected frequency within a reception band and minimizes the tracking error at the frequency. a storage means for storing information regarding the voltage supplied to the variable reactance element; and a storage means for controlling the reception frequency and determining whether the reception frequency is a frequency stored in the storage means, and the reception frequency is stored in the storage means. When the frequency is
The information stored in the storage means is supplied to the voltage variable reactance element, and when the reception frequency is different from the frequency stored in the storage means, information corresponding to a frequency stored in the storage means near the reception frequency. An electronically tuned receiver comprising control means for obtaining information regarding the voltage supplied to the voltage variable reactance element at the receiving frequency based on the above, and supplying the information to the voltage variable reactance element. 2. The electronically tuned receiver according to claim 1, wherein the storage means is configured to store information regarding a high frequency signal level for performing a sweep stop operation during automatic channel selection.