JPH021962Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a PLL synthesizer type electronically tuned radio receiver, and particularly to an ANT (antenna) or RF (high frequency) radio receiver including a variable capacitance diode.
In an electronically tuned radio receiver that uses a control signal from a PLL synthesizer-type oscillation circuit to tune each stage of the tuning circuit, the characteristics of each variable capacitance diode placed in the tuning circuit are determined when selecting a station. The present invention relates to an electronically tuned radio receiver equipped with a control means that automatically adjusts each tuning circuit to an optimal tuning state, including compensation for variations.

[Conventional technology and problems]

FIG. 1 is a block diagram of the main parts of a conventional electronically tuned radio receiver. In the same figure, 1 is
RF amplifier circuit, 2 is ANT tuning circuit, 3 is RF tuning circuit, 4 is mixer circuit, 5 is oscillation circuit (VCO),
6 is an oscillation tank circuit, 7 is an IF (intermediate frequency) circuit,
Reference numeral 8 represents a PLL circuit, 9 a low-pass filter, 10 a signal line for supplying an oscillation signal A, and 11 a signal line for supplying a control signal B.

The ANT tuning circuit 2, the RF tuning circuit 3, and the oscillation tank circuit 6 are each of an electronic tuning type including a variable capacitance diode, and FIG. 2 shows the circuit configuration of the ANT tuning circuit 2 as a typical example. In the figure, 12 is an antenna coil, 13 is a trimmer capacitor, 14 is a variable capacitance diode, and 15 is a control signal supply resistor, and the dashed line blocks indicate components common to other circuits 3 and 6. be.

Oscillation signal A output from oscillation circuit 5 is applied to PLL circuit 8 from signal line 10 . On the other hand,
The output signal of the PLL circuit 8 has a DC component extracted by a low-pass filter 9, and is sent to the signal line 1 as a control signal B.
1 is taken out.

This control signal B is transmitted from the oscillation circuit 5 to the oscillation tank circuit 6 via the PLL circuit 8 and the low-pass filter 9.
PLL coupled to variable capacitance diode 14 inside
This is a control signal for the feedback loop, and is used to control the oscillation frequency of the oscillation circuit 5 to the optimum point.
4 and are used to tune each to the receiving frequency.

However, these ANT tuning circuits 2 and RF
Since the tuning circuit 3 is not included in the above-described PLL loop, the control of the control signal B to these circuits 2 and 3 is open-loop control. Therefore, in the variable capacitance diode 14 of circuits 2 and 3,
In order to be able to take the optimum value for the control signal B, it was necessary to use one with characteristics carefully selected in advance, and further to adjust the operating characteristics using the trimmer capacitor 13.

However, even if the characteristics of the variable capacitance diode are carefully selected and adjusted using a trimmer as described above, these only allow adjustment at a small number of points within the operating range; It was not possible to obtain sufficient adjustment within the operating range.

[Purpose and main points of the invention]

The purpose of this invention is to relax the characteristics selection criteria for variable capacitance diodes in conventional electronically tuned radio receivers, or eliminate the need for selection itself, and also to eliminate the need for complicated adjustments using trimmers, thereby almost eliminating the adjustment process during manufacturing. The objective is to make this possible and improve reception performance.

Therefore, in the present invention, at the beginning of the tuning operation during reception, the setting voltage of the variable capacitance diode of each tuning circuit is individually varied within a certain range, the corresponding change in the IF signal level is checked, and each tuning is determined from the maximum value. The above object is achieved by providing means for determining the optimum value for the set voltage of the variable capacitance diode of the circuit and holding the optimum value during subsequent reception operations.

[Example of idea]

The present invention will be described in detail below using examples.

FIG. 3 is a block diagram of an embodiment of the present invention.
The structure is based on the conventional example shown in FIG. In Figure 3, 1 is an RF amplifier circuit, 2 is an ANT tuning circuit, 3 is an RF tuning circuit, 4 is a mixer circuit, and 5
is the oscillation circuit (VCO), 6 is the oscillation tank circuit, and 7 is the oscillation tank circuit.
IF circuit, 8 is PLL circuit, 9 is low-pass filter, 1
0 is a signal line for oscillation signal A, 11 is a signal line for control signal B, 16 is an A/D converter, 17 is a controller, 18 and 19 are D/A converters, 20
21 is an arithmetic unit, 22 is a signal line for the signal meter signal C output from the IF circuit 7, 23 is a signal line for the digitally converted signal meter signal D, and 24 and 25 are respectively for the ANT tuning circuit 2.
Signal lines 26 and 27 for digital control signals E and F generated by the controller 17 to control the RF tuning circuit 3 are obtained by converting the digital control signals E and F into analogs by D/A converters 18 and 19, respectively. The signal lines 28 and 29 for control signals G and H are connected to control signals G and H and control signal B, respectively.
and signal lines of control signals (B+G) and (B+H) obtained by combining the signals in computing units 20 and 21, and 30 represents a control signal I given to the PLL circuit 8 for tuning to a certain frequency. Note that the single line in the figure indicates an analog signal line, and the double line indicates a digital signal line.

The process of generating the control signal B from the oscillation signal A to control the oscillation circuit 5 is the same as that of the conventional example explained in FIG. 1, so the explanation will be omitted.

In the embodiment of the present invention, the control signal for each variable capacitance diode of the ANT tuning circuit 2 and the RF tuning circuit 3 is a control signal E generated by the controller 17 provided according to the present invention based on the control signal B described above. .
Signals (B+G) and (B+
H).

The signal meter signal C taken out from the IF circuit 7 represents the level of the IF signal.
Therefore, when the ANT tuning circuit 2 or the RF tuning circuit 3 is adjusted to the optimum state, the signal C should take the maximum value.

Therefore, in order to obtain the levels of the control signals E and F that give the optimum adjustment state of each tuning circuit 2 and 3, the controller 17 sequentially sends the control signals E and F from the computing units 20 and 21 to each of the tuning circuits 2 and 3. , control signals (B+G) and (B+H) that change stepwise within a certain range as shown in FIG. 4 are applied.
Note that t _p to t _o in the figure represent the time points at which the level changes. The controller generates a signal meter signal C from each of these two stepped control signals.
The level that maximizes is detected, and this level is then continued to be supplied as the optimum control signal to each tuning circuit 2, 3.

FIG. 5 shows the internal configuration of the controller 17. Reference numeral 31 in the figure is a memory that stores the values of the digital signal meter signal D corresponding to each level of the stepwise control signal described above. Reference numeral 32 denotes a maximum value detection unit, which detects the level (or the change time t _p to t _o ) corresponding to the maximum value in the signal meter signal data stored in the memory. Reference numeral 33 is a stepwise signal generation section, which has a fixed timing (t _p
to t _o ), and a digital signal that changes stepwise with a constant level difference is generated. Reference numeral 34 denotes an interface section for supplying the digital signal outputted from the stepped signal generation section 33 to the signal line 24 or 25. 35 is a main control unit for controlling each of these elements 31 to 34 and the PLL circuit 8. Note that such a controller 17 can be easily configured using a microprocessor.

FIG. 6 is an explanatory diagram of the operation of the embodiment shown in FIG. 3. The operation will be described below in accordance with the sequential steps shown.

Step The controller 17 via the signal line 30
A control signal I is supplied to the PLL circuit 8 to set a required tuning frequency. Here, if the IF frequency is i, the control signal B is generated from the PLL circuit 8 and the low-pass filter 9 and given to the oscillation circuit 5 so that the oscillation frequency of the oscillation signal A becomes -i. At this stage, the control signals E and F are controlled by the controller 1.
7, the control signals supplied to the ANT tuning circuit 2 and the RF tuning circuit 3 are only B, respectively.

Steps The controller 17 outputs a stepwise control signal E in digital format only to the signal line 24. This control signal E is converted by the D/A converter 18 into an analog control signal G that changes stepwise. This control signal G is combined with the control signal B in the arithmetic unit 20 and becomes a control signal (B+G).
It is supplied to the ANT tuning circuit 2. Note that only the control signal B continues to be supplied to the RF tuning circuit 3 as is. Corresponding to each stepped level of the control signal (B+G), the IF signal level of the IF circuit 7 changes, and, for example, a signal meter signal C as shown in the lower part of the figure is output. Each level of the signal C is converted into a digital signal by the A/D converter 16 as described above, and is stored as the control signal D in the memory 31 (FIG. 5) in the controller 17. The controller 17 detects the maximum value (referred to as P ₁ ) as described above, and sets the value P ₁ to
The corresponding level E' in the control signal E that gives the signal is selected, held, and output to the signal line 24. In this way, the control signal ((B+G)') that brings the ANT tuning circuit 2 into the optimum tuning state is set.

Steps The controller 17 then outputs a stepwise control signal F in digital format to the signal line 25 to perform control similar to the stepwise control described above. In this way, the signal meter signal C to the RF tuning circuit 3
The maximum value (denoted as P ₂ ) of is detected, and the level of the corresponding control signal (denoted as F') is fixed. As a result, a control signal ((B+H)') is set to bring the RF tuning circuit 3 into the optimal tuning state.

Stairs A radio reception operation is performed using the control signals B', (B+G)', and (B+H)' obtained from the above steps.

By the above operation, each tuning circuit and oscillation circuit are always controlled at any set tuning frequency.
It can be automatically adjusted to the optimum condition for each individual.

If the step-like level change width of the control signals (B+G) and (B+H) controlled by the controller 17 is set appropriately, even if there is considerable variation in the characteristics of the variable capacitance diode, they can be almost the same without adjusting the trimmer. If you can achieve high quality reception performance and further adjust the trimmer,
It becomes possible to deal with variations in characteristics over a wider range.

[Effect of idea]

As described above, according to the present invention, a high-performance electronically tuned radio receiver including multiple tuning circuits can be easily adjusted without having to select the characteristics of variable capacitance diodes, and with almost no adjustment. It can be manufactured as is, and when in use, all tuning circuits can be automatically tuned with high precision to any tuning frequency, making it possible to always receive good radio reception. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example of an electronically tuned radio receiver, Fig. 2 is a circuit diagram of its ANT tuning circuit, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 shows the voltage applied to the tuning circuit. FIG. 5 is a detailed configuration diagram of the controller, and FIG. 6 is an explanatory diagram of the operation. In the figure, 1 is an RF amplifier circuit, 2 is an ANT tuning circuit,
3 is an RF tuning circuit, 4 is a mixer circuit, 5 is an oscillation circuit, 6 is an oscillation tank circuit, 8 is a PLL circuit, 9 is a low-pass filter, 16 is an A/D converter, 17 is a controller, 18 and 19 are D/ A converter,
20 and 21 represent arithmetic units.

Claims (1)

[Scope of utility model registration request] An oscillation circuit each including a variable capacitance diode and a plurality of tuned circuits such as an ANT stage or an RF stage, and detecting the oscillation signal of the oscillation circuit to control the set voltage of each of the variable capacitance diodes, and oscillating the oscillation circuit. and a PLL circuit that controls the frequency to a predetermined value and tunes the plurality of tuning circuits.
In a PLL synthesizer type electronically tuned radio receiver, a detector for detecting the level of an IF signal and a tuning frequency are set in the above PLL circuit, and a tuning frequency is set in the above-mentioned PLL circuit, and the tuning frequency is set in sequence for each variable capacitance diode of the plurality of above-mentioned tuning circuits. The set voltage is changed within a predetermined level range, and the above IF corresponding to the change is applied.
An electronic tuning system characterized by comprising: a controller that examines the signal level detector output, determines the optimal setting voltage for each variable capacitance diode to maximize the IF signal level, and supplies it as the setting voltage. model radio receiver.