JPH04359542A - Method of wiring semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a semiconductor integrated circuit having multi-layer wiring layers. After manufacturing a chip, a part of the wiring is corrected using FIB, laser CVD, etc. on the chip, and repairs are performed to accommodate logic changes. This paper relates to wiring technology during chip manufacturing to facilitate this processing.

0002

2. Description of the Related Art After manufacturing a semiconductor integrated circuit chip, a technique for modifying part of the wiring on the chip to change the logic uses FIB, laser CVD, etc., as described in Japanese Patent Application Laid-Open No. 62-229956. It is reported that it will.

[0003] After manufacturing a semiconductor integrated circuit chip, a part of the wiring on the chip is modified using FIB, laser CVD, etc. to facilitate processing when repairing in response to logic changes. As for the wiring technology at the time, JP-A-0
As described in 2-15657, a technique has been reported in which the yield of processing is improved by pulling up the wiring pattern and providing a detour section for the wiring pattern and performing repairs at this location.

0004

[Problems to be Solved by the Invention] The above-mentioned prior art merely describes a technique in which the wiring pattern is pulled up to the logic wiring layer closest to the LSI surface, a detour is provided in the wiring pattern, and repairs are performed at this location. ing. However, some LSIs have a power supply wiring layer on top of the logic wiring layer, and further have power supply terminals and input/output terminals. In this case, there is a problem that even if the wiring pattern is brought up to the upper layer, power supply wiring, power supply terminals, input/output terminals, etc. become obstacles to processing, making it impossible to process, or even if processing is possible, the yield decreases. Ta.

The present invention takes into consideration the power supply wiring, power supply terminals, input/output terminals, etc., thereby reducing cutouts in the power supply wiring as much as possible during repair, improving processing yield, and furthermore, making the wiring physically repairable. The aim is to increase

[0006]

[Means for Solving the Problems] The following invention is provided as a means for achieving the above object.

The first invention is that when a logic signal wiring pattern whose logic is allowed to be changed by FIB, laser CVD, etc. is pulled up to the logic signal wiring layer closest to the surface of the LSI, there is an obstacle to processing in the air above the wiring. The wiring pattern is pulled up by selecting a pulling location so that the wiring pattern includes a location where there are no power terminals, input/output terminals, power wiring, etc.

[0008] The second invention is for a logic signal wiring pattern that allows logic changes by FIB, laser CVD, etc.
When a detour part is provided in a part of the wiring pattern adjacent to the wiring pattern or in a part of the wiring pattern to extend the distance between the wiring patterns, there are no power terminals or input terminals in the air above the detour part that become obstacles to processing. The present invention is characterized in that a detour location is selected so as to include a location where there are no output terminals, power supply wiring, etc., and the detour is performed at this location.

[0009] A third aspect of the invention is to take obstacles into consideration when selecting a wiring pattern pull-up location and a wiring pattern detour location.
The feature is that obstacles that can be processed by FIB, such as power supply wiring, and obstacles that are extremely difficult to process, such as power supply terminals and input/output terminals, are considered in different levels as different selection conditions.

[0010] The fourth invention is to raise the wiring pattern and detour the wiring pattern for the purpose of considering repairability for wiring for which there is no place that satisfies the conditions when selecting a wiring pattern lifting location and wiring pattern detouring location. is characterized by not being carried out.

[0011]

[Operation] According to claim 1 of the present invention, the logic signal wiring pulled up to the logic signal wiring layer closest to the LSI surface is connected to the FI
B. When processing with laser CVD, there are no power terminals, input/output terminals, power wiring, etc. that would be obstacles to processing above the wiring, so there is no need to process such as cutouts to remove obstacles. be. Furthermore, it is possible to avoid situations where repairs are abandoned due to obstacles.

According to claim 2 of the present invention, in the logic signal wiring pattern, a logic signal wiring pattern in which a detour part is provided between adjacent wiring patterns to extend the interval between each wiring pattern is connected to an FIB at the detour part. When processing by laser CVD, there are no power terminals, input/output terminals, power wiring, etc. that would be obstacles to processing above this detour, so there is no need to process such as cutouts to remove obstacles. . Furthermore, it is possible to avoid situations where repairs are abandoned due to obstacles.

According to claim 3 of the present invention, the power supply terminal, input/output terminal, and power supply wiring are treated as obstacles of different levels. For example, power supply terminals and input/output terminals are 100% prohibited, and power supply wiring is permitted only if there is no corresponding location. This has the effect of easing the conditions and making it possible to allocate more wiring to repairable wiring areas.

According to claim 4 of the present invention, for wiring that cannot be repaired due to the existence of an obstacle above the wiring pattern pulling up place or the wiring pattern detouring place, the wiring pattern can be pulled up or the wiring pattern can be detoured. By not performing any processing, extra wiring channels are used to remove bad elements that obstruct the pulling up or detour of other wiring, or generate unnecessary through holes and patterns that reduce yield. be.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1(a) shows a front view of the LSI as seen from above, and FIG. 1(b) shows a cross-sectional view. For example, as shown in Figure 1, LS
A power supply wiring layer, power supply terminals, input/output signal terminals, etc. are present on the surface of I. And below that there are three wiring layers, two layers,
There is one layer. For example, FIB, L by laser CVD
Since SI repair is performed from above the chip, it is easier to process the wiring layer closest to the LSI surface (layer 3 in Figure 1), so a portion of the wiring is raised to layer 3 as shown in Figure 2. . Furthermore, as a measure to prevent contact with adjacent wiring, excessive cutting, etc. during processing, a process is performed in which a part of the wiring is provided with an expanded distance from the adjacent wiring, as shown in FIG. The processing shown in FIGS. 2 and 3 is described in Japanese Patent Laid-Open No. 02-15657. However, in order to actually cut the wiring that has been pulled up to three layers, the power supply wiring, power supply terminals, input/output signal terminals, etc. above the wiring become obstacles. However, the power supply wiring, power supply terminals, and input/output signal terminals do not cover the entire surface.
There are places, such as the point 101 in FIG. 1, where neither exists. If processing is performed from this location, JP-A-63-1
There is no need to cut out the power supply wiring with the FIB as described in No. 57438, and processing can be performed directly. Also, if the only obstacle is the power supply wiring, it can be solved with a cutout, but if there is a power supply terminal or input/output signal terminal above it, the FI
Processing using B becomes difficult, and if all the wiring to be processed is below the power supply terminal, processing will be abandoned, resulting in the problem that logic cannot be changed. In this way, if the processing shown in Figures 2 and 3 is performed at a location that satisfies condition 101 (the wiring layer closest to the LSI surface and where there are no power supply wiring, power supply terminals, or input/output signal terminals in the sky), ,1
00% processing is possible, which has the effect of reducing processing time during processing and improving yield. In this example, power supply wiring, power supply terminals, and input/output signal terminals are used as examples of obstacles, but if there are any other obstacles to processing, it is possible to obtain the same effect by avoiding them. be. Furthermore, as described above, there are obstacles that can be dealt with by cutting out the FIB, and obstacles that are difficult to deal with, such as power supply terminals and input/output signal terminals. If these obstacles are treated as equivalent obstacles, there will be only a few percent of the area on the surface of the LSI where there are no obstacles, and all the logic signal wiring that is allowed to change logic will be allocated to this area using the above method. is almost impossible. Therefore, the above obstacles will be treated as obstacles at different levels. As shown in FIG. 4, first, the processes of claims 1 and 2 are performed taking into account all obstacles such as power supply wiring, power supply terminals, and input/output signal terminals. When searching for this area, if the search range is set to the entire area of the chip, the length of detour wiring to the area may become enormous, causing several problems such as wiring delay. In order to keep this within the limit value, a search area is provided that matches the limitations of each semiconductor integrated circuit, and the search is performed within this range. For the wiring for which a corresponding area is not found, the power supply wiring is then removed from the obstruction, and the processing according to claims 1 and 2 is performed in which the power supply terminal and the input/output signal terminal are taken into consideration as the obstruction. By removing the power supply wiring from obstacles, the area can be expanded by several tens of percent, making it possible for almost all wiring to meet the requirements, and making repairs possible by making notches. Furthermore, for wiring that fails to satisfy the above conditions, these processes are not performed because it is difficult to repair the wiring even if the wiring is pulled up to an upper layer or the wiring spacing is expanded. This prevents wasted use of wiring channels and reduces the number of wiring and through holes, thereby preventing factors that reduce yield during initial LSI manufacturing. The above embodiment has been explained on the premise that the wiring is pulled up to the logic wiring layer closest to the LSI surface, but if the processing accuracy of the repair equipment makes it possible to easily repair the lower layer or even lower layer,
It will be readily understood that all that has been said above is also applicable regarding the pulling up to that layer.

Next, an example of an algorithm for lifting a wiring pattern in a target area will be explained with reference to FIG. First, a search is made to see if there is an area above the wiring 501 of interest that satisfies condition 101. In FIG. 5, an area 502 satisfies condition 101. If the corresponding area does not exist in the sky, the search will be performed in the vicinity of the wiring. Next, if the wiring 501 is a one-layer wiring, a required length of wiring is allocated to the area 502 of three layers. At this time, it is necessary to pass through two layers for pulling up, so it is necessary to consider the wiring area of the two layers. Although this example is an example in which the wiring pattern is shaped after the wiring is performed, it is also possible to perform the wiring in consideration of the initial wiring. For example, as shown in FIG. 6, when wiring terminals 601 and 602, a region 603 that satisfies condition 101 is formed by these two points.
04 and preferentially assign and route the third-layer wiring 605 there. As described above, by adding conditions to the conventional automatic wiring process, it is possible to perform the processes of claims 1 to 4.

As described above, according to the present invention, by wiring the wiring pattern during the initial design of the LSI in consideration of repair obstacles on the LSI surface, it is possible to reduce the repair processing time and improve the feasibility of repair. be.

[0019]

Effects of the Invention According to claims 1 and 2 of the present invention,
FIB, laser CVD, etc. are used to create a logic signal wiring pattern in which a detour part is provided between the logic signal wiring pattern pulled up to the logic signal wiring layer closest to the LSI surface and the adjacent wiring pattern to extend the interval between the wiring patterns. When machining, there are no power terminals, input/output terminals, power wiring, etc. that would be obstacles to machining above the wiring, so machining such as notches to remove obstacles is not required, reducing machining time and cutting. This has the effect of preventing a decrease in yield due to chipping. Furthermore, it has the effect of avoiding situations where repairs are abandoned due to obstacles.

According to claim 3 of the present invention, by treating power terminals, input/output terminals, and power wiring as obstacles of different levels, for example, power terminals, input/output terminals are 100% prohibited, and power wiring is prohibited at the relevant location. It will be allowed only if there is no. This eases the conditions, makes it possible to allocate more wiring to repairable wiring areas, and has the effect of improving the possibility of implementing logic changes through repair.

According to claim 4 of the present invention, for wiring that cannot be repaired due to the presence of an obstacle in the air above the wiring pattern pulling up place or the wiring pattern detouring place, the wiring pattern can be pulled up or the wiring pattern can be detoured. Not performing this process has the effect of eliminating the use of extra wiring channels that interfere with pulling up and detouring other wiring, and the generation of unnecessary through holes and patterns that reduce yield. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a front view and a cross section of an LSI chip.

FIG. 2 is a wiring diagram.

FIG. 3 is an expanded view of adjacent wiring intervals.

FIG. 4 is a processing flowchart according to claim 3;

FIG. 5 is a schematic diagram of a pull-up wiring processing method.

FIG. 6 is a schematic diagram of a pull-up wiring processing method.

Claims (4)

[Claims] [Claim 1] After manufacturing a semiconductor integrated circuit chip, a part of the wiring is corrected on the chip using FIB (focused ion beam), laser CVD (chemical vapor deposition), etc. to correspond to logic changes. When carrying out this process, it is a wiring method during chip manufacturing to facilitate this processing, and the logic signal wiring pattern that allows logic changes by FIB, laser CVD, etc. is raised to the logic signal wiring layer closest to the LSI surface. When placing the wiring, the wiring pattern is pulled up by selecting a pulling location so that the wiring pattern includes places where there are no power terminals, input/output terminals, power wiring, etc. that would be obstacles to processing above the wiring. A semiconductor integrated circuit wiring method. [Claim 2] After manufacturing a semiconductor integrated circuit chip, a part of the wiring on the chip is modified using FIB, laser CVD, etc. to facilitate repair in response to logic changes. FIB is a wiring method during chip manufacturing.
, for a logic signal wiring pattern whose logic is allowed to be changed by laser CVD, etc., a detour part is provided in a part of the wiring pattern adjacent to the wiring pattern or in a part of the wiring pattern to extend the interval between the wiring patterns. When installing, there are power supply terminals, input/output terminals, and
A semiconductor integrated circuit wiring method characterized in that a detour location is selected so as to be a detour section including a location where there is no power supply wiring, etc., and a detour is performed at this detour location. [Claim 3] Obstacles that can be processed by FIB, such as power supply wiring, power supply terminals, and input/output terminals are considered in consideration of obstacles when selecting the wiring pattern pull-up location in claim 1 and the wiring pattern detour location in claim 2. A semiconductor integrated circuit wiring method characterized in that obstacles that are extremely difficult to process are considered in different levels as different selection conditions. [Claim 4] When selecting a wiring pattern pulling location as claimed in claim 1 and a wiring pattern detour location as claimed in claim 2, for wiring for which there is no location that satisfies the conditions, the wiring pattern is pulled up for the purpose of considering repairability; A semiconductor integrated circuit wiring method characterized in that a detour of a wiring pattern is not performed.