JP2007088178A - Method for arranging double-via cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for arranging a double-via cell where a larger metallic region is obtained in the circumferential part of via holes, while preventing the reduction of a wiring density in metal wiring. <P>SOLUTION: Layout data, after terminating a multi-layer metal wiring process using a single-via cell in the layout design of a semiconductor integrated circuit, are read so as to calculate an interval between the single-via cell and the adjacent metal wiring. The interval is collated with design reference so as to determine whether replacement into the double-via cell is possible or not. When the replacement is possible, the double-via cell with the widest metallic region in the circumference of the via holes is selected from among the plurality of kinds of double-via cells which are stored, in a double-via cell library with different width of the metallic region in the circumference of the via holes. Then, the selected via cell is arranged in place of the single-via cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit layout process, and more particularly, to a method for arranging double via cells connecting different metal wiring layers.

  With the progress of nanometer technology, it is necessary to introduce a so-called DFM (Design for Manufacturing) method in consideration of manufacturing yield at each stage of designing a semiconductor integrated circuit.

  One of the factors that reduce the manufacturing yield of semiconductor integrated circuits is electromigration and stress migration that occur in vias connecting between metal wiring layers. As a countermeasure, it has been known that a double via that uses two via holes, which has conventionally been used only at one connection location, is effective (see, for example, Patent Document 1).

  In the layout process of a semiconductor integrated circuit, when a via hole is arranged, a via cell in which the via hole and a metal layer around the via hole are formed as one cell is arranged. When arranging the double via, a double via cell in which two via holes and a metal layer in the peripheral portion are arranged in one via cell is used. In contrast, a conventional via cell having only one via hole is called a single via cell.

  In addition, the reliability of the metal wiring is improved as the metal region around the via hole is increased. Therefore, the production yield can be improved as the metal region around the via hole of the double via cell is increased.

However, the use of a double via cell with a wide metal area around the via hole is in a trade-off relationship with the wiring density of the metal wiring, and all the vias of the semiconductor integrated circuit are connected to the metal area around the via hole. When a wide double via cell is used, there is a problem that the wiring density is lowered and the chip size is increased.
JP 2005-26390 A (page 13, FIG. 10)

  Accordingly, an object of the present invention is to provide a method for arranging a double via cell having a metal region as wide as possible around the via hole while preventing a reduction in the wiring density of the metal wiring.

  According to one aspect of the present invention, after completion of a multi-layer metal wiring process using a single via cell in a layout design of a semiconductor integrated circuit, the single via cell is replaced with the single via cell. There is provided a double via cell arrangement method characterized by arranging a double via cell in which a width of a metal region around a via hole is changed in accordance with an interval between adjacent metal wirings.

  According to another aspect of the present invention, a plurality of types of double via cells having different widths of metal regions around via holes are prepared in advance, and single via cells in the layout design of a semiconductor integrated circuit are prepared. After the multilayer metal wiring process used is completed, the width of the metal region around the via hole becomes the largest among the plurality of types of double via cells according to the distance from the metal wiring adjacent to the single via cell. A double via cell placement method is provided, wherein a double via cell is selected and placed in place of the single via cell.

  According to still another aspect of the present invention, for the layout data of a semiconductor integrated circuit in which a multi-layer metal wiring is performed using a single via cell, a metal wiring adjacent to the single via cell; A single via from a double via cell library storing a plurality of types of double via cells having different widths of a metal region around a via hole based on the interval. Selecting a double via cell replaceable with the cell; selecting a double via cell having the widest metal region around the via hole from the selected double via cell; Replacing the single via cell with the selected double via cell, and arranging the double via cell. There is provided.

  According to yet another aspect of the present invention, after the multi-layer metal wiring process using a single via cell in the layout design of a semiconductor integrated circuit is completed, the single via cell is replaced with a double via. Provided is a method for arranging a double via cell, characterized in that the cell is arranged and the width of the metal region around the via hole of the double via cell is changed in accordance with the distance from the adjacent metal wiring. .

  According to still another aspect of the present invention, for the layout data of a semiconductor integrated circuit in which a multi-layer metal wiring is performed using a single via cell, a metal wiring adjacent to the single via cell; And a step of determining whether the metal region around the via hole can be replaced with a double via cell having a minimum width on a design standard based on the interval. Replacing the single via cell determined to be replaceable with the double via cell, calculating a residual interval between the replaced double via cell and the adjacent metal wiring; Increasing the width of the metal region around the via hole of the double via cell within a range in which the residual interval satisfies a design standard. Method of arranging a double-via cell to is provided.

  According to the present invention, it is possible to arrange a double via cell in which the metal region in the peripheral portion of the via hole is made as wide as possible while preventing a reduction in the wiring density of the metal wiring.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of a functional block configuration for performing double via cell placement processing by the double via cell placement method according to the first embodiment of the present invention.

  The double via cell placement processing by the double via cell placement method of the present embodiment is executed using, for example, the EDA tool 100 used for the layout design of the semiconductor integrated circuit.

  Further, as a database to be read into the EDA tool 100, layout data 200 after completion of the multi-layer metal wiring process using a single via cell, a minimum distance between the single via cell and the metal wiring, a minimum space between the metal wirings, and the like And a double via cell library 400 in which a plurality of types of double via cells having different widths of metal regions around the via hole are stored.

  The EDA tool 100 includes a layout data reading unit 1 that reads layout data 200 from a database, a single via cell extraction unit 2 that extracts a layout position of a single via cell from the read layout data 200, and a single via. The distance calculation unit 3 for calculating the distance between the single via cell and the adjacent metal wiring based on the cell arrangement position data and the distance between the adjacent metal wiring and the design standard 300 are collated. From the double via cell library 400 when the replacement to the double via cell is possible, and when the replacement to the double via cell is possible, it is determined whether the replacement to the double via cell is possible. Double via cell selection part 5 that selects all replaceable double via cells, and whether it is in the selected double via cell A double via cell selection unit 6 that selects a double via cell having the widest metal region around the via hole, and a double via cell that replaces the single via cell with the selected double via cell. And a replacement processing unit 7.

  The layout data in which the single via cell is replaced with the double via cell by the double via cell replacement processing unit 7 is output from the EDA tool 100 as the replacement processed layout data 500.

  FIG. 2 is a pattern diagram showing an example of a double via cell stored in the double via cell library 400. Here, an example of seven types of double via cells (double via cells A to G) in which the peripheral region width of the via hole 11 of the metal 12 covering the via hole 11 is different is shown.

  Of these, the cell width of the double via cell A is the narrowest and the cell width is W1. The width of the metal region around the via hole 11 of the double via cell A is t1 on both the left and right sides.

  In contrast, in the double via cell B, the width of the metal region around the right via hole 11 is t2 (t2> t1) wider than the double via cell A, and the double via cell C is in the left via hole. The metal region width around 11 is t2, and the double via cell D has the metal region width around the via hole 11 t2 on both the left and right sides.

  In the double via cell E, the width of the metal region around the right via hole 11 is t3 (t3> t2) wider than the double via cell D, and the double via cell F is around the left via hole 11. In the double via cell G, the metal region width around the via hole 11 is t3 on both the left and right sides.

  FIG. 3 is a flowchart showing a processing flow of the double via cell arrangement method according to the first embodiment of the present invention.

  With reference to the flowchart shown in FIG. 3, the method for arranging the double via cells of this embodiment will be described with reference to the layout diagrams shown in FIGS. Further, the double via cell to be arranged is the one shown in FIG.

  When the double via cell placement processing is started using the placement method of this embodiment, first, layout data after the completion of the multi-layer metal wiring process using the single via cell is read from the database (step S01). .

  Next, the read layout data is searched to search for a single via cell, and the arrangement position of the first found single via cell is extracted from the layout data (step S02).

  Further, the arrangement position of the metal wiring adjacent to the single via cell is extracted from the layout data, and the interval between the single via cell and the adjacent metal wiring is calculated (step S03).

  Subsequently, the calculated interval between adjacent metal wirings is checked against a design standard related to layout design, and it is determined whether or not this single via cell can be replaced with a double via cell. Specifically, it is assumed that the single via cell is replaced with the double via cell A having the narrowest cell width among the double via cells shown in FIG. Judgment is made based on whether the design criteria can be satisfied (step S04).

  FIG. 4 shows an example of the determination process in step S04.

  When the distance between the single via cell 70 and the adjacent metal wiring 13 as shown in FIG. 4A is d1, as shown in FIG. Assume that cell A is replaced. Since the cell width of the double via cell A is W1, in this case, the metal space between the double via cell A and the adjacent metal wiring 13 is (d1-W1). Therefore, it is verified whether the metal space (d1-W1) is equal to or larger than the minimum metal space S on the design standard. In the example of FIG. 4B, since (d1−W1) ≧ S, in this case, it is determined that the single via cell 70 can be replaced with a double via cell.

  On the other hand, when the distance between the single via cell 71 and the adjacent metal wiring 13 as shown in FIG. 4C is d2, the single via cell 71 is doubled as shown in FIG. Assuming that the via cell A is replaced, the metal space between the double via cell A and the adjacent metal wiring 13 is (d2-W1). In the example of FIG. 4B, since (d2-W1) <S, in this case, it is determined that the single via cell 71 cannot be replaced with a double via cell.

  Returning to the flowchart of FIG. 3, if it is determined in step S04 that replacement with a double via cell is possible (YES), all the replaceable double via cells are obtained from the double via cell library. Selected (step S05).

  That is, in step S04, the possibility of replacement with the double via cell using the double via cell A having the minimum cell width W1 is determined. If there is a margin in the metal space with the adjacent metal wiring 13, Replacement with a double via cell having a large cell width is also possible. Therefore, in step S05, when the single via cell is replaced, all the double via cells in which the metal space with the adjacent metal wiring is equal to or larger than the minimum metal space on the design standard are double via cell cells. Select from the library.

  Subsequently, a double via cell having the widest metal region around the via hole is selected from the selected double via cells (step S06).

  FIG. 5 shows an example of double via cell selection in step S06.

  FIG. 5A shows an example in which the double via cell B shown in FIG. 2 is selected, and FIG. 5B shows an example in which the double via cell F shown in FIG. 2 is selected. In any example, the double via cell in which the width of the metal region around the via hole is the widest among the double via cells in which the space on the design standard with the adjacent metal wirings 13A and 13B is the minimum metal space S or more. A cell is selected.

  Returning to the flowchart of FIG. 3, when a double via cell having the widest metal region around the via hole is selected in step S06, the single via cell in the layout data is selected. (Step S07).

  This completes the processing for one single via cell. Therefore, it is checked whether or not extraction of all single via cells on the layout data has been completed (step S08).

  If it is determined in step S04 that the replacement with the double via cell is impossible (NO), the process proceeds to step S08.

  If it is determined in step S08 that the extraction of the single via cell has not been completed (NO), the process returns to step S02, and the subsequent steps are repeated.

  If it is determined in step S08 that the extraction of the single via cell has been completed (YES), the double via cell placement processing by the placement method of this embodiment is terminated.

  According to the present embodiment, a single via cell replaceable with a double via cell can be replaced while maintaining the wiring position of the metal wiring routed by the multilayer metal wiring process using the single via cell. Therefore, the wiring density of the metal wiring when the double via cell is used can be kept the same as that when the metal wiring is performed using the single via cell.

  In addition, since the metal region around the via hole of the double via cell to be replaced can be made as wide as possible within the design criteria, the reliability around the via hole can be improved, and the manufacturing yield of the semiconductor integrated circuit can be reduced. Can be prevented.

  FIG. 6 is a block diagram showing an example of a functional block configuration for performing double via cell placement processing by the double via cell placement method according to the second embodiment of the present invention.

  Similar to the first embodiment, the double via cell placement processing by the double via cell placement method of the present embodiment can also be executed by using the EDA tool 100 used for the layout design of the semiconductor integrated circuit.

  In this embodiment, as the database read into the EDA tool 100, the layout data 200 after the completion of the multi-layer metal wiring process using the single via cell, the minimum distance between the single via cell and the metal wiring, and the interval between the metal wirings are used. A design standard 300 relating to a layout that defines a minimum space or the like is used.

  In this embodiment, unlike the first embodiment, the double via cell used in the arrangement of the double via cell has a metal region width around the via hole that is the minimum dimension on the design standard, that is, the cell width is minimum. Use only one type.

  The EDA tool 100 includes a layout data reading unit 51 that reads layout data 200 from a database, a single via cell extraction unit 52 that extracts an arrangement position of a single via cell from the read layout data 200, and a single via. The interval calculation unit 53 for calculating the interval between the single via cell and the adjacent metal wiring based on the cell arrangement position data, and the interval between the adjacent metal wiring and the design standard 300 are collated. A replacement determination unit 54 for determining whether or not replacement with a double via cell is possible, and when replacement with a double via cell is possible, a single via cell is replaced with a double via cell.・ Replacement processing unit 55 for replacing a cell with a double via cell and a cell between the replaced double via cell and an adjacent metal. When the width of the metal region around the via hole of the double via cell is increased within a range in which the metal space between the adjacent metal wiring and the adjacent metal that satisfies the design standard satisfies the design criteria, the via hole is calculated. And a peripheral metal region width increase processing unit 57.

  The layout data that has been processed by the via hole peripheral metal region width increase processing unit 57 is output from the EDA tool 100 as replacement processed layout data 550.

  FIG. 7 is a flowchart showing a processing flow of the double via cell arrangement method according to the second embodiment of the present invention. The arrangement method of the double via cell according to this embodiment will be described with reference to this flowchart.

  When the double via cell placement processing is started using the placement method of this embodiment, first, layout data after the completion of the multi-layer metal wiring process using the single via cell is read from the database (step S51). .

  Next, the read layout data is searched to search for a single via cell, and the arrangement position of the first found single via cell is extracted from the layout data (step S52).

  Further, the arrangement position of the metal wiring adjacent to the single via cell is extracted from the layout data, and the interval between the single via cell and the adjacent metal wiring is calculated (step S53).

  Subsequently, the calculated interval between adjacent metal wirings is checked against a design standard related to layout design, and it is determined whether or not this single via cell can be replaced with a double via cell. Specifically, it is assumed that the single via cell is replaced with a double via cell, and even in this case, the determination is made based on whether or not the design criteria regarding the minimum metal space can be satisfied (step S54).

  If it is determined in step S54 that replacement with a double via cell is possible (YES), the single via cell on the layout data is replaced with a double via cell (step S55).

  At this time, since the replaced double via cell has the smallest cell width, there is a possibility that the metal space with the adjacent metal has a margin with respect to the design standard. Therefore, the remaining distance from the adjacent metal wiring after the single via cell is replaced with the double via cell is calculated (step S56).

  If there is a margin in the remaining interval, the metal region width around the via hole of the replaced double via cell is increased within a range in which the remaining interval satisfies the minimum metal space on the design standard (step S57).

  This completes the processing for one single via cell. Therefore, it is checked whether or not extraction of all single via cells on the layout data has been completed (step S58).

  If it is determined in step S54 that replacement with a double via cell is impossible (NO), the process proceeds to step S58.

  If it is determined in step S58 that the single via cell extraction has not been completed (NO), the process returns to step S52, and the subsequent steps are repeated.

  If it is determined in step S58 that the extraction of the single via cell has been completed (YES), the double via cell placement processing by the placement method of the present embodiment is terminated.

  FIG. 8 shows an example in which double via cells are arranged by the arrangement method of this embodiment.

  FIG. 8A shows a case where the distance from the adjacent metal wiring 13 is calculated by the process of step S53 of the same flowchart with respect to the single via cell 70 extracted by the process of step S52 of the flowchart shown in FIG. Shows an example of a layout whose interval is d10.

  8B is determined to be replaceable in step S54 in the flowchart shown in FIG. 7, and the single via cell 70 shown in FIG. 8A is changed to the cell width W10 by the process in step S55 in the same flowchart. FIG. 6 is a diagram showing an example in which a double via cell 80 is replaced.

  Here, in step S54 of the flowchart of FIG. 7, a value (W10−d10) obtained by subtracting the cell width W10 of the double via cell 80 from the distance d1 between the single via cell 70 and the adjacent metal wiring 13 is a design standard. Whether or not the single via cell 70 can be replaced with the double via cell 80 having the cell width W10 is determined depending on whether or not it is equal to or larger than the minimum metal space S.

  In this example, since (W10−d10) ≧ S, it is determined that it is possible to replace the single via cell 70 with the double via cell 80 having the cell width W10, and the layout data is processed by the subsequent processing of step S55. The upper single via cell 7 is replaced with a double via cell 80.

  FIG. 8C shows an example in which the metal region width around the via hole of the double via cell 80 is increased by the process of step S57 in the flowchart shown in FIG. The width of the metal metal region around the via hole of the double via cell 80 is such that the remaining distance r10 between the double via cell 80 and the adjacent metal wiring 13 satisfies the minimum metal space S on the design standard (r10 ≧ s). Additional metal 14 indicates the increased metal area.

  Also in the method of this embodiment, similarly to the method of Embodiment 1, a single via cell that can be replaced while maintaining the wiring position of the metal wiring wired by the multilayer metal wiring process using the single via cell is doubled.・ Because it is replaced with a via cell, the wiring density of the metal wiring when using a double via cell can be kept the same as when using a single via cell, and the replacement double -The metal region around the via hole of the via cell can be made as wide as possible within the design criteria.

  Further, according to this embodiment, since only one type of double via cell is prepared in advance, the amount of design data can be reduced.

FIG. 3 is a block diagram illustrating an example of a functional block configuration for performing double via cell placement processing by the double via cell placement method according to the first embodiment of the present invention; FIG. 5 is a pattern diagram showing an example of a double via cell used in the arrangement of the double via cell by the double via cell arrangement method according to the first embodiment of the present invention. 5 is a flowchart showing a processing flow of a method for arranging double via cells according to the first embodiment of the present invention. FIG. 5 is a layout diagram for explaining a method for arranging double via cells according to the first embodiment of the present invention. FIG. 5 is a layout diagram for explaining a method for arranging double via cells according to the first embodiment of the present invention. The block diagram which shows the example of a structure of the functional block which performs the arrangement process of a double via cell by the arrangement method of the double via cell concerning Example 2 of the present invention. 9 is a flowchart showing a processing flow of a method for arranging double via cells according to the second embodiment of the present invention. FIG. 6 is a layout diagram illustrating an example in which double via cells are arranged by a double via cell arrangement method according to a second embodiment of the present invention.

Explanation of symbols

1, 51 Layout data reading unit 2, 52 Single via cell extraction unit 3, 53 Interval calculation unit with adjacent metal wiring 4, 54 Replacement determination unit 5 for double via cell 5 Double via cell selection unit 6 Double via cell selection unit 7, 55 Replacement processing unit 56 for double via cell 56 Remaining interval calculation unit 57 with adjacent metal wiring Via hole peripheral metal region increase processing unit 11 Via hole 12 Metal 13, 13A, 13B Adjacent metal wiring 14 Additional metal 70, 71 Single via cell 80 Double via cell

Claims (5)

  After the completion of the multi-layer metal wiring process using single via cells in the layout design of a semiconductor integrated circuit, the single via cell is replaced and the distance from the metal wiring adjacent to the single via cell is determined. And arranging a double via cell in which the width of the metal region around the via hole is changed.   A plurality of types of double via cells having different widths in the metal region around the via hole are prepared in advance, and after the multi-layer metal wiring process using the single via cell in the layout design of the semiconductor integrated circuit, the single A double via cell having the widest metal region around the via hole is selected from the plurality of types of double via cells according to the distance from the metal wiring adjacent to the via cell, and the single via is selected. A method for arranging a double via cell, wherein the cell is replaced with a cell. For the layout data of a semiconductor integrated circuit in which multi-layer metal wiring is performed using a single via cell, calculating an interval between the single via cell and the adjacent metal wiring;
Based on the interval, a double via cell that can be replaced with the single via cell from a double via cell library storing a plurality of types of double via cells having different widths of the metal region around the via hole. Selecting a via cell;
Selecting a double via cell having the widest metal region around the via hole from the selected double via cell;
Replacing the single via cell with the selected double via cell.   After the completion of the multilayer metal wiring process using the single via cell in the layout design of the semiconductor integrated circuit, a double via cell is arranged in place of the single via cell, and the via hole of the double via cell is arranged. A method for arranging a double via cell, wherein the width of a peripheral metal region is changed in accordance with an interval between adjacent metal wirings. For the layout data of a semiconductor integrated circuit in which multi-layer metal wiring is performed using a single via cell, calculating an interval between the single via cell and the adjacent metal wiring;
Determining whether the metal region around the via hole can be replaced with a double via cell having a minimum width according to a design standard based on the spacing; and
Replacing the single via cell determined to be replaceable with the double via cell;
Calculating a residual interval between the replaced double via cell and an adjacent metal wiring;
And a step of increasing a width of a metal region around the via hole of the double via cell within a range in which the remaining interval satisfies a design standard.

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