JPH0434980A - Semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture an SOI-MOSFET in lessened substrate floating effect by a method wherein a part of the insulating film provided for separating the SOI-MOSFET is opened to provide the body contact for leading-out the surplus carrier. CONSTITUTION:The surplus carrier as a hole in this NMOSFET generated by the collision ionization in the high field region at the interface between a channel region 8 and a drain region 10 runs into a well region 11 beneath insulating films 5 for separation passing through the channel region 8 beneath a gate electrode 5. At this time, the surplus carrier is led out of the system since the well region 11 is connected to a wiring layer 15 for body through the intermediary of a body contact 7. Accordingly, the hole can not be accumulated in the channel region 8 so as to lessen the so-called substrate floating effect. Through these procedures, the excellent transistor characteristics such as the restraint of the kink effect causing the constriction in the Id-Vd characteristics when the SOI film of an SOI-MOSFET is thicker and the deterioration in the breakdown strength between S/D when the SOI film is thinner can be displayed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS transistor formed in a semiconductor layer on an insulating substrate.
(Metal Oxide Sem1conduct
or) type field effect transistor (rso 1-M
03FETJ), in particular, it relates to improving the withstand voltage between the source and drain.

[Conventional technology]

Figure 5 is a plan view of a conventional So I-MOSFET, Figure 6 is a plan view of a conventional So I-MOSFET.
The figure is a cross-sectional view of a conventional So I-MOSFET. An insulator 112 is formed on a silicon substrate 1 , and a silicon layer 3 is formed on an insulator layer 2 . Silicon N
3, a low p-type impurity concentration (for example, 10
A channel region 8 having a high n-type impurity concentration (for example, 10I9-10"a toms/cj) is formed, and a source region 9 and a drain region 10 having a high n-type impurity concentration (for example, 10I9-10"a toms/cj) are formed. They are formed in contact with one side and the other side of the channel region 8.

A gate dielectric thin film 4 is formed on the channel region 8 , and a gate electrode 5 is formed on the dielectric thin film 4 . Silicon layer 3 and gate electrode 5 are covered with interlayer insulating film 12 . A contact hole 13 is formed in the glabella insulating film 12, and a conductor 1 corresponding to the contact hole is formed.
4 is formed.

In the So I-MOSFET configured as described above, when a positive voltage is applied to the gate electrode 5, n-conductivity type carriers (electrons) are attracted to the upper layer part of the p-type channel region 8, and the upper layer part is inverted to the same n conductivity type as the source region 9 and drain region 10. therefore,
Current can flow between source region 9 and drain region 10. Further, since the concentration of n-type carriers attracted to the upper layer of the channel region 8 changes depending on the gate voltage, the amount of current flowing through the channel region 8 can be controlled by the gate voltage.

This is the operating principle of MOSFET.

[Problem to be solved by the invention]

If the silicon layer is relatively thick (e.g., approximately 5000 nm thick), applying a gate voltage will cause the SOI-MOS F E
When T is activated, carriers are accelerated within the channel region 8 at high speed. The carriers accelerated in the channel region 8 generate electron-hole pairs near the drain region 10 by collision ionization. These generated electrons flow into the n+ type drain region 10, but the holes are accumulated in the channel region 8 and increase the potential.
This increases the channel current and causes an undesirable kink effect on the drain voltage versus drain current curve. This kink effect, for example,
E-Electron Device Letter Volume 9 2.
pp. 97-99 1988 (IEEE Electron
Device Letter, Vol, 9+ No.
, 2+pp, 97-99.1988).

On the other hand, a thin film SO■-MOSFET with a very thin (e.g. 500-1500 nm thick) silicon layer 3
is a normal SoI-MOSF with a thick silicon layer 3
It has superior properties compared to ET. For example, the entire thin channel region 8 is made into a depletion layer by applying a voltage to the gate electrode 5, and the potential is also controlled by the gate electrode. The short channel effect, in which the gate threshold voltage becomes abnormally low when the length is short, is reduced.

However, when the entire channel region 8 is completely depleted, the potential within the channel region 8 is
higher than in SFET. therefore,
In addition to lowering the electrical barrier between the source region 9 and the channel region 8, if the holes generated by the aforementioned impact ionization are temporarily accumulated in the channel region 8, the potential within the channel region 8 further increases. However, electrons are rapidly injected from the source region 9 into the channel region. That is,
Thin film Sol-MOSFETs have a problem in that the withstand voltage between the source and drain tends to be low. This is shown in FIG. The kink effect when the SOI layer is thick and the reduction in breakdown voltage between the source and drain when the SOI layer is thin are both caused by the fact that the channel region is electrically floating (referred to as the substrate floating effect).

In view of the above conventional problems, an object of the present invention is to provide an SOI-MOSFET with improved substrate floating effect.

[Means to solve the problem]

The MOS FET semiconductor device according to the present invention is an SOI
- A part of the insulating film provided for MOSFET isolation is opened to provide a body contact for extracting excess carriers.

[Effect]

In the body contact provided in the isolation insulating film in this invention, surplus carriers generated in the channel region of the transistor are extracted from the body contact portion through the well region. Therefore, S/
D It is possible to suppress a decrease in breakdown voltage or the occurrence of a kink effect.

〔Example〕

FIG. 1 shows a So 1-MO5FE according to an embodiment of the present invention.
2 is a sectional view taken along the line XX in FIG. 1, and FIG. 3 is a sectional view taken along the line YY in FIG.

This embodiment is similar to the conventional semiconductor device except for the following points, so the same reference numerals are given and the explanation thereof will be omitted. An isolation insulating film 6 is used for isolation of the SOI-MOSFET, and under the isolation insulating film 6, a P-type impurity having the same conductivity type as the channel region is present, for example, 10" to 10".
A well region 11 into which "atom's/aJ" is introduced is formed.

Further, a part of the isolation insulating film 6 is opened and connected to the body wiring layer 15 via the body contact 7.

Next, the operation will be explained.

Excess carriers generated by impact ionization in the high electric field region at the boundary between the channel region 8 and the drain region 10, here N
Since it is a MOSFET, the holes pass through the channel region 8 under the gate electrode 5 and reach the well region 11 under the isolation insulating film 6.
flows to Here, since the well region 11 is connected to the body wiring layer 15 via the body contact 7, it is pulled out from here.

Therefore, holes are not accumulated in the channel region 8, and the so-called substrate floating effect is reduced.

Therefore, the kink effect and S
The decrease in breakdown voltage between 870 and 870 that occurs when the OI film is thin is suppressed, and excellent transistor characteristics as shown in FIG. 4 are obtained.

Further, the body contact 7 may be provided in common to a plurality of transistors, and there is almost no need for an increase in area.

Although NMOSFET was described in the above embodiment, the same effect can be obtained with PMOSFET only by having the conductivity reversed.

Further, although a silicon layer was used as the semiconductor layer in the above embodiment, it goes without saying that similar effects can be obtained using any semiconductor material.

〔Effect of the invention〕

As described above, according to the present invention, So I-MOSF
In ET, an isolation insulating film is used to isolate transistors, and a body contact is provided in the well region by penetrating the isolation insulating film, making it possible to extract excess carriers generated in the channel region under the gate electrode of the transistor. This has the effect of improving the kink effect due to the substrate floating effect and the decrease in breakdown voltage between 870 and 870 mm.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line XX in FIG. 1, FIG. 3 is a cross-sectional view taken along the Y-Y line in FIG. 1, and FIG. Id, - of a thin film SOI-MOS FET as a semiconductor device according to an embodiment of the present invention
Vd characteristic diagram, FIG. 5 is a plan view showing a conventional semiconductor device,
Figure 6 is a sectional view taken along line A-A in Figure 5, and Figure 7 is a conventional thin film S.
o It is an Id-Vd characteristic diagram of I-MOSFET. In the figure, 1 is a silicon substrate, 2 is an insulator layer, 3 is a silicon layer, 4 is a dielectric thin film, 5 is a gate electrode, 6 is an isolation insulating film, 7 is a body contact, 8 is a channel region, and 9 is a source 10 is a drain region, 11 is a well region, 12 is an insulating film between eyebrows, 10 is a drain region, 11 is a well region, 12 is an interlayer insulating film, 13 is a contact hole, 14 is a wiring layer, 15 is a body wiring layer . In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a MOSFET semiconductor device formed on a semiconductor layer on an insulator, a semiconductor layer formed on an insulator substrate, and a gate electrode formed on the semiconductor layer with a dielectric thin film sandwiched therebetween. a channel region of a first conductivity type provided under the gate electrode; a source region and a drain region of a second conductivity type provided with the channel region under the gate electrode sandwiched therebetween; and a source region and a drain region of a second conductivity type provided in the semiconductor layer. a well region of a first conductivity type provided under the isolation insulating film; a body contact provided by opening the isolation insulating film; and a body contact connected to the body contact. 1. A semiconductor device comprising a wiring layer.