JPH0434792A - Dram control system - Google Patents

Abstract

PURPOSE:To reduce the interruption of a page access caused by refresh by adding a refresh management function to a DRAM controller, and refreshing collectively in these idle hours when there is no access to the DRAM before the refresh request generated periodically. CONSTITUTION:A refresh management means 4 is provided with the DRAM controller to count the number of the request and execution of the refresh. When judging no access to the DRAM is present thereon before the refresh request generated periodically by the refresh management means 4, the plural numbers of refresh are performed at a time, and high-speed access control is preferentially executed without performing the refresh even when the refresh request is generated as much as the refresh performed in advance. Thus, the efficiency of a control system can be improved by reducing the confliction between the access and the refresh and reducing the interruption of the page access caused by the insertion of a refresh cycle.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dynamic RAM control method using a high-speed access mode, which can reduce contention with refresh and improve system efficiency of a control system. .

[Conventional technology]

Dynamic RAM (DRAM) consists of two elements: a capacitive element for charge storage and a MOSFET for charge input/output control. Storage information is represented by the charge accumulated in the capacitive element, but leakage current of the MOSFET and semiconductor substrate The accumulated charge decays over time due to recombination at the surface. For this reason, a refresh operation is required to update the stored information at regular intervals.

In normal DRAM, RA S (row addr
essstrobe) and CA S (column
When an external clock signal (address 5trobe) is provided, first a row address is applied, and then RAS is input, the address signal is taken internally and latched as a row address. Applying to the bin and inputting CAS,
Column addresses are latched in the same way. By using this method, the number of bottles can be reduced and the package can be made smaller.

After selecting a specific row by inputting a row address and connecting all the memory cells in that row to the bit line group, by accessing the bit line group consecutively, the memory cells in the same row can be accessed consecutively. , a fast access mode has been developed. In the page mode, it is possible to repeatedly input a CAS and a column address to successively access memory cells in the same row one after another. That is, since input of the row address and RAS can be omitted except at the beginning, high-speed access is possible.

Furthermore, in the static column mode, CAS input is further omitted, and as soon as the column address is determined, access to the corresponding memory cell is executed. By changing only the column address, different memory cells can be accessed one after another.

In this way, in these high-speed access methods, if accesses within the same page are made consecutively, row address control is not required for the second and subsequent accesses, and the memory cycle can be sped up accordingly.

FIG. 5 is a block diagram of a conventional DRAM access control mechanism, and FIG. 6 is a block diagram of a conventional DRAM access control mechanism. 1 is a detailed block diagram of a DRAM controller in FIG.

In FIG. 5, a microprocessor 10 issues an access command to a DRAM 12 to a DRAM controller 11 by executing a program.

As shown in FIG. 6, the DRAM controller 11 includes a row address comparison section 1, a memory control section 2, and a refresh timer 3 between the host side interface i/f and the memory side interface i/f. .

The row address comparison section holds the row address of the previous cycle, compares the row addresses of consecutive cycles, and transmits the result to the memory control section 2. In the memory control unit 2, if the access is within a page, the RAS
In the case of an off-page access in which the RAS is held active and the column address is controlled, the RAS is made inactive once and the RAS precharge time is maintained before memory access is started. On the other hand, if there is a refresh request from the refresh timer 3, refresh is performed with priority regardless of whether the page is inside or outside.

These matters are described, for example, in "Electronic Information and Communication Handbook" Volume 1, published by Ohmsha Co., Ltd., March 30, 1988, pp. 887-892.

[Problems to be Solved by the Invention] As mentioned above, in the conventional high-speed access method, if accesses within the same page are consecutive, row address control is not required for the second and subsequent accesses, so I was able to speed up memory cycles.

However, (a) even when accesses within the same page are continuous, if a refresh cycle enters in the middle, the row address must be specified again after the refresh is completed, so that cycle is not a normal access cycle. same amount of time is required. In other words, the refresh cycle has been a major factor that impairs the effectiveness of high-speed access.

Furthermore, in the (b) high-speed access method, since the microprocessor 10 does not output information in advance as to whether the next access will be inside or outside the page, this is determined after the address is determined in the next cycle. Therefore, at the page change, RAS was made inactive after the address was determined, and memory access was started after holding the RAS precharge time, so normal access
The problem was that it took longer than the cycle.

There is a demand for reducing page switching loss time when accessing sequential addresses.

The first object of the present invention is to solve the above-mentioned conventional problem (a), reduce contention between access and refresh, reduce interruption of page access due to refresh cycle insertion, and improve system efficiency of the control system. The object of the present invention is to provide a RAM control method that can be improved.

Further, a second object of the present invention is to solve the conventional problem (b) above, and when accessing sequential addresses,
It is an object of the present invention to provide a RAM control method capable of eliminating loss time during page switching and improving system efficiency of a control system.

[Means to solve the problem]

In order to achieve the above object, the DRAM control method of the present invention provides: (a) the DRAM controller is provided with refresh management means for counting the number of refresh requests and refresh executions; If it is determined that there is no access to the DRAM earlier, refresh is performed multiple times at once, and even if a refresh request is generated for the refresh performed earlier, the refresh is not performed.
The feature is that high-speed access control is prioritized and executed. (b) The DRAM controller is provided with a page end notice means that monitors column addresses, detects a page end, and foretells this, and the page end notice means indicates that the next column address to be accessed is When the maximum value is detected, the in-page access is terminated without waiting for the next cycle's row address comparison by forewarning that the next cycle will be an out-of-page access. It has characteristics.

[For production]

In the present invention, (a) D having a high-speed access function;
A refresh management function is added to the RAM controller, and the DRA
If there is no access to M, refresh is performed all at once during this free time, and even if a refresh request occurs, the refresh is not performed and the access is given priority by the amount of refresh performed earlier. This makes it possible to reduce interruptions in page access due to refreshes. (b) DRAM with high-speed access function
By adding a page end warning function to the controller and monitoring the column address, when it detects that the column address is at its maximum value, it announces that the next cycle will be an access outside the page, and starts the next cycle. The page access ends without waiting for comparison with the row address of .

This allows the page change timing to be accelerated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a DRAM controller showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment differs from the conventional system shown in FIG. 4 in that a refresh management section 4 is provided between a memory control section 2 and a refresh timer 3. The refresh management unit 4 counts up in response to a refresh request from the refresh timer 3, and the memory control unit 2
It has a built-in up/down counter that counts down when it refreshes.

If refresh is performed only by a refresh request from the refresh timer 3, the count value of the up/down counter will repeat +1 and -1. However, in this embodiment, even if there is no refresh request from the refresh timer 3, refresh is performed if there is no access to the DRAM, so in this case the count value of the up-drain counter decreases.

Furthermore, in this embodiment, even if there is a refresh request from the refresh timer 3, if the count value is not the maximum value, refresh may not be performed while continuous access is being continued.

In this case, the count value of the up/down counter increases.

By setting the initial count value to the maximum, priority can be given to access even if there is a refresh request from the refresh timer 3 by the amount of refresh performed first. Furthermore, if the count value is the minimum,
Even if the DRAM is not accessed, there is no need to perform additional refresh if no refresh is performed.

FIG. 3 is a sequence chart of the up/down counter in the first embodiment.

On the vertical axis in Figure 3, when there is a refresh request from refresh timer 3, the up/down counter goes +
When the DRAM controller 2 increments by 1 and refreshes, the up/down counter decrements by -1. m is the maximum count value, and 0 is the minimum count value. The vertical axis is the elapsed time, and T is the refresh cycle.

(2) shows the operation of the counter when refresh is performed for each refresh request, and (2) shows the operation of the counter when there is no access or when refresh is performed all at once based on this embodiment. Furthermore, the diagonally shaded portion indicates a period in which there is continuous access within the same page.

First, in the case of ■, there is a refresh request before the refresh cycle has elapsed, so the DRAM controller performs the refresh, and then when one hour has passed,
Since there is a refresh request, refresh is performed each time. In this case, the counter value becomes a pulse waveform that is repeatedly generated. Therefore, in this case, even if there is an access to the same page during the hatched period, a refresh will be inserted in the middle, so it is necessary to specify the row address again at the point marked with ○, resulting in high-speed access. Instead, it takes the same amount of time as a normal access cycle.

On the other hand, when refresh is performed all at once as in this embodiment (case ◯), refresh is performed three times in succession at the time when a refresh request is first made. The process can be performed continuously until the maximum value m is reached. Next, refresh is performed once when a refresh request is received after 3T. In FIG. 3, it is not necessary to perform refresh for a period that is three times the refresh cycle, so even if there is continuous access within the same page in the shaded area during that period, there is no fear that refresh will be interrupted.

FIG. 2 is a block diagram of a DRAM controller showing a second embodiment of the present invention.

In Fig. 2, compared to the conventional Fig. 4, the page
An end notice section 5 is newly provided.

The page end notification unit 5 compares the column address at the time of memory access with the maximum value of the column address, and transmits the result to the memory control unit 2.

If the column address is not the maximum value, the memory control unit 2 compares the row address of the next cycle as usual.
This determines whether the page access continues or not.
If the address is the maximum value, we expect the page access to end in that memory cycle. That is, in this case, the DRAM controller 2 performs RAS precharge by inactivating the RAS before the end of the next cycle, without waiting for the row address comparison of the next cycle. In this way, by speeding up RAS precharging, it is possible to reduce page switching loss time when sequential addresses are accessed.

FIG. 4 is an operation flowchart of the second embodiment of the present invention.

The page end notification unit 5 determines whether the column address at the time of memory access is the maximum value or not, and the result is transmitted to the memory control unit 2 (step 101).
). If there is no notice of the page end, the row address comparator 1 compares the row address of the next cycle as usual (step 102), and determines whether the page access continues (step 103). Then, the result is transmitted to the memory control section 2. In the memory control unit 2,
If it is an off-page access, RAS is once made inactive (step 105), the RAS precharge time is maintained (step 106), and then memory access is started (step 107). Then, when the next access command comes from the microprocessor 10, which is a host device (step 10B), the process returns to step 101.
Go back and repeat the same action. If there is no access command, the process ends.

In this example, after the page end is confirmed, the RA
If S is made inactive and RAS precharge is performed, the time will be delayed, so the page end notification unit 5 compares in advance to determine whether or not it is the page end. If it is the page end, RAS is made inactive by the end of that cycle without waiting for the next cycle's row address comparison (step 105), and RAS precharge is performed (step 10).
6). Immediately after RAS precharge, memory access begins (step 107). By accelerating RAS precharging, the loss time for page switching is reduced accordingly.

[Effects of the Invention] As explained above, according to the present invention, refresh, which is a factor that impairs the effectiveness of high-speed access, is managed, so contention between access and refresh is reduced, and page access due to refresh cycle insertion is reduced. It is possible to reduce the number of interruptions and improve the efficiency of the control system. Furthermore, by monitoring column addresses, it is possible to eliminate loss time when switching pages during sequential address access, and this also makes it possible to improve the efficiency of the control system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a DRAM controller showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a DRAM controller according to a second embodiment of the present invention.
A configuration diagram of the RAM controller, FIG. 3 is an operation sequence chart of the up/down counter of the refresh management section in FIG. 1, and FIG. 4 is a diagram of the DRAM in FIG. 2.
FIG. 5 is a block diagram of a conventional memory system, and FIG. 6 is a configuration diagram of a conventional DRAM controller. 1: Row address comparison section, 2: Memory control section, 3: Refresh timer, 4: Refresh management section, 5:
Page end notice section, 10; microprocessor,
11: DRAM controller, 12: DRAM, 13:
bus. Figure Figure Figure Figure

Claims (2)

[Claims] (1) A DRAM that is read and written by a microprocessor, and a DRAM that performs high-speed access control in page mode or static column mode.
In a DRAM control system having a controller, the DRAM controller is provided with refresh management means for counting the number of refresh requests and refresh executions, and the refresh management means is configured to access the DRAM before a refresh request that is periodically generated. When it is determined that there is no refresh, the refresh is performed multiple times at once, and even if a refresh request is generated for the refresh performed earlier, the high-speed access control described above is executed with priority without performing the refresh. DRAM control method. (2) A DRAM that is read and written by a microprocessor, and a DRAM that performs high-speed access control in page mode or static column mode.
In a DRAM control method having a controller, the DRAM controller is provided with a page end notice means for detecting a page end by monitoring column addresses and foretelling this, and the page end notice means performs the following steps. When it is detected that the column address to be accessed is the maximum value, the next cycle's row address is
A DRAM control method characterized by terminating intra-page access without waiting for address comparison.