JPH04334061A - Thin film transistor matrix and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix and a method of manufacturing the same. In recent years, thin film transistor (TFT) matrices have come to be used as driving elements for liquid crystal displays (LCDs), electroluminescence, and the like. Such a TFT matrix contains hundreds of thousands of TFTs, and there is a strong demand for ease of manufacture and improvement in manufacturing yield.

0002

[Prior Art] FIG. 4 is a plan view of a conventional staggered TFT matrix, and FIGS. 1 is a glass substrate, 2 is a Cr film, 3 is a SiO2 layer, 6 is a data bus line, 7 is a drain electrode, 8 is a source electrode, 9 is a contact layer, 10 is an active semiconductor layer, 1
1 and 12 are gate insulating layers, 13 is a gate electrode, and 14 is a gate bus line.

The conventional example will be explained below with reference to these figures. First, a transparent insulating substrate 1 such as a glass plate
A Cr film is deposited on the substrate and patterned to form a light shielding film 2.

[0004] SiO2 is used as an insulating layer of the light shielding film 2 on the entire surface.
After forming layer 3, an ITO layer and an n+ type a-Si layer are deposited. The ITO layer and the n+ type a-Si layer are patterned to form a drain electrode 7, a source electrode 8, and a pixel electrode 15.

An i-type a-Si layer and a SiNx layer covering the entire surface are successively deposited, and these and the n+-type a-Si layer are collectively patterned to form a contact layer 9, an active semiconductor layer 10, and a gate insulating layer 11.

After that, since the ITO layer alone has too high bus line resistance for large screens, a metal such as Al is deposited and patterned to form a low resistance data bus line 6 connected to the drain electrode 7. . In this case, Al
The film thickness is required to be about 6000 Å, although it depends on the width of the bus line.

After forming the SiNx layer 12 which also serves as a gate insulating layer between the gate bus line and the data bus line, a metal such as Al is deposited on the entire surface and patterned to form the gate electrode 13 and connection thereto. A gate bus line 14 is formed.

Although the TFT matrix is completed in this way, this conventional structure has the following problems. That is, the Al film thickness of the data bus line 6 needs to be about 6000 Å, and if the SiNx layer 12 on top of it is too thick, it will deteriorate the TFT characteristics, so it is limited to about 3000 Å at most. If a short circuit occurs between bus lines 14 or gate bus line 1
There is a problem in that a disconnection occurs at a step between line 4 and data bus line 6.

[0009]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention solves the problem of short-circuiting occurring between the data bus line 6 and the gate bus line 14, or disconnection of the gate bus line 14 at a step between the data bus line 6 and the data bus line 6. It is an object of the present invention to provide a TFT matrix structure that does not occur and a method for manufacturing the same.

0010

[Means for solving the problem] FIGS. 1(a) and 1(b) are cross-sectional views of the TFT matrix of the embodiment, and FIGS. 2(a)-
(f) is a process-order cross-sectional view showing an example; FIG. 3(a);
(b) is a cross-sectional view for explaining the flattening process of the data bus line.

[0011] The above problem is solved by a transparent insulating substrate 1, a transparent insulating layer 3 covering the transparent insulating substrate 1, and a surface of the transparent insulating layer 3 whose surface height is approximately equal to the height of the surface of the transparent insulating layer 3. A plurality of parallel data bus lines 6 are embedded so as to be parallel to each other, and source lines are sequentially stacked on the transparent insulating layer 3.
Drain electrodes 7 and 8, active semiconductor layer 10, gate insulating layers 11 and 12, gate electrode 13, and a plurality of parallel gate bus lines 14 perpendicular to the plurality of parallel data bus lines 6 via insulating layer 12. The solution is provided by a thin film transistor matrix characterized in that it has.

[0012] Furthermore, a transparent insulating layer 3 is formed on the transparent insulating substrate 1.
After etching the transparent insulating layer 3 using a mask 4 having a plurality of parallel grooves on the transparent insulating layer 3 to form an opening 5 in the transparent insulating layer 3. , a second step of filling the openings 5 with a metal layer to form a plurality of parallel data bus lines 6 whose surface heights are approximately equal to the height of the surface of the transparent insulating layer 3; A third step is to deposit a semiconductor layer over the entire surface and pattern it to form a drain electrode 7 and a source electrode 8.
and a fourth step of forming an active semiconductor layer 10 extending from above the transparent insulating layer 3 between the source electrodes 8 onto the drain electrode 7 and the source electrode 8 on both sides;
a fifth step of forming a gate insulating layer 12 that covers and extends over the entire surface of the active semiconductor layer 10; and depositing a metal layer on the gate insulating layer 12 and patterning it to form a gate electrode 13 on the active semiconductor layer 10; and a sixth step of forming a plurality of parallel gate bus lines 14 connected to the gate electrode 13 and perpendicular to the plurality of parallel data bus lines 6 via the gate insulating layer 12, The problem is solved by a method of manufacturing a thin film transistor matrix in which the first step to the sixth step are performed in this order.

[0013] Also, after etching the transparent insulating layer 3 using a mask 4 having a plurality of parallel grooves on the transparent insulating layer 3 and forming an opening 5 in the transparent insulating layer 3, the opening 5 is etched. A metal layer is deposited on the entire surface so that the height of the surface of the metal layer in which 5 is embedded is approximately equal to the height of the surface of the transparent insulating layer 3, the metal layer on the mask 4 is removed together with the mask 4, and the opening is performed. A second step of melting and smoothing the burrs 6a of the metal layer generated around the periphery of the hole 5 by irradiating light to form a plurality of parallel data bus lines 6 embedded in the transparent insulating layer 3. The present invention is solved by a method for manufacturing a thin film transistor matrix having the following.

[0014]

[Operation] According to the present invention, the data bus line 6 is embedded in the transparent insulating layer 3, and the height of the surface thereof is approximately equal to the height of the surface of the transparent insulating layer 3, so that the data bus line 6 is embedded in the transparent insulating layer 3, and the gate insulating layer 12 is placed above the data bus line 6. The gate bus lines 14, which are orthogonal to each other, are formed flat, so that short circuits between the gate bus lines 14 and the data bus lines 6 and disconnections of the gate bus lines 14 do not occur. Therefore, the manufacturing yield of the TFT matrix is increased.

[0015]

Embodiment FIGS. 2(a) to 2(f) are step-by-step cross-sectional views showing an embodiment, and are sectional views taken along the line A-A corresponding to the cross-section taken along the line A-A in FIG. Embodiments of the present invention will be described below with reference to these figures.

FIG. 2(a) A Cr film 2 is deposited to a thickness of 1000 Å on a glass substrate 1 as a reference transparent insulating substrate by sputtering, and patterned to leave it under the active semiconductor layer and data bus line. do. The Cr film 2 under the active semiconductor layer becomes a light shielding film,
The Cr film 2 below the data bus line serves as an etching stopper.

FIG. 2(b) A SiO2 layer 3 is placed as a transparent insulating layer on the entire reference surface, and plasma C
It is deposited to a thickness of 6000 Å by the VD method, and a resist is applied thereon to form a resist mask 4 that opens a plurality of parallel grooves in the data bus line formation area. S using the resist mask 4 as a mask and using a hydrofluoric acid etching solution.
The iO2 layer 3 is etched to form an opening 5. At this time, the Cr film 2 serves as an etching stopper.

FIG. 2(c) Al is deposited as a data bus line forming metal over the entire surface by reference sputtering, and the openings 5 are filled. Al is also deposited on the resist mask 4. By peeling off the resist mask 4 and lifting off the Al on it at the same time, S
A data bus line 6 embedded in the iO2 layer 3 is formed. At this time, the height of the data bus line 6 is SiO2
The height is approximately equal to the height of the surface of layer 3.

FIG. 2(d) A transparent conductor such as ITO is deposited on the entire surface as a source/drain metal to a thickness of 500 Å using the reference sputtering method.
Subsequently, n+ a-Si is deposited to a thickness of 500 Å. The ITO layer and n+ a-Si are etched using a resist mask to form an ITO drain electrode 7 and source electrode 8, and an n+ a-Si contact layer 9 thereon. Drain electrode 7 is connected to data bus line 6
formed so as to be electrically connected to the

FIG. 2(e) A 500 Å thick a-Si layer and a 500 Å thick SiNx layer are successively deposited by the reference plasma CVD method. A resist is applied on top of it, and it is patterned to form a resist mask. Using the resist mask as a mask, a SiNx layer is formed using a CF4-based etching gas.
The -Si layer and the n+a-Si layer are etched to form a gate insulating layer 11, an active semiconductor layer 10, and a contact layer 9. In this way, the TFT elements are separated.

FIG. 2(f) A Si layer with a thickness of 2500 Å is deposited on the entire surface by the reference plasma CVD method.
A Nx layer is deposited to form a gate insulating layer 12. This gate insulating layer 12 also serves as an interlayer insulating layer at the intersection of the data bus line 6 and the gate bus line.

Thereafter, Al was deposited to a thickness of 6000 Å on the entire surface by sputtering, and it was patterned to form a gate electrode 13 on the top of the active semiconductor layer 10 and connect it to the gate electrode 13 via the gate insulating layer 12. A plurality of parallel gate bus lines 14 orthogonal to the data bus line 6
form.

FIGS. 1(a) and 1(b) are cross-sectional views of the TFT matrix completed in this way.
FIG. 2 is a cross-sectional view taken along line B-B including the intersection of gate bus line 14 and gate bus line 14;

As shown in FIG. 1(b), since the surface of the data bus line 6 is formed at the same height as the surface of the SiO2 film 3, the gate bus line 14 also has a height at the intersection with the data bus line 6. It is formed flat and will not be short-circuited or disconnected with the data bus line 6 at the intersection.

[0025] During the manufacturing process, by sputtering,
When Al for data bus line formation is deposited on the entire surface, the openings 5 are filled, and the Al on the resist mask 4 is lifted off, it may not be completely flattened depending on the shape of the resist mask 4 and the conditions for forming the Al film. Al burrs may be formed on the periphery of the opening 5.

FIGS. 3A and 3B are diagrams for explaining the data bus line flattening process at that time. Figure 3
(a) shows the state in which Al burrs 6a are generated, (b)
2 shows a state in which the Al burr 6a is melted and reflowed by irradiating it with a laser beam, and the corners are made gentle and almost flat.

When a glass substrate with a softening point lower than the melting point of Al (660° C.) is used as the transparent insulating substrate 3, light is momentarily irradiated to keep the glass substrate below the softening point, and the opaque Al Light is absorbed only in that part, and the Al burr 6a is reflowed. Laser as a light source,
A halogen lamp or the like can be used. Further, this planarization treatment can be performed even after the source/drain electrodes are formed if the source/drain electrodes are transparent.

[0028]

As explained above, according to the present invention, since the height of the surface of the data bus line 6 is approximately equal to the height of the surface of the insulating layer 3, the gate bus line 14 crosses the data bus line 6. It is also formed flat with the insulating layer 12 interposed therebetween, so that there will be no short-circuiting or disconnection with the data bus line 6 at the intersections.

The present invention has the effect of improving the manufacturing yield of TFT matrices and contributes to improving the yield of liquid crystal display panels.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a TFT matrix of an example.
(a) is a sectional view taken along line AA, and (b) is a sectional view taken along line BB.

FIGS. 2(a) to 2(f) are process-order sectional views showing an example.

FIGS. 3(a) and 3(b) are cross-sectional views for explaining flattening processing of data bus lines.

FIG. 4 is a plan view of a conventional staggered TFT matrix.

FIG. 5 is a cross-sectional view of a conventional staggered TFT matrix, in which (a) is a cross-sectional view taken along line AA, and (b) is a cross-sectional view taken along line B-B.

[Explanation of symbols]

1 is a transparent insulating substrate, the glass substrate 2 is a light shielding film and an etching stopper, the Cr film 3 is a transparent insulating layer, the SiO2 layer 4 is a mask, and the resist mask 5 has an opening 6 as a data bus. The line 6a is a burr, the Al burr 7 is a drain electrode, the ITO layer 8 is a source electrode, the ITO layer 9 is a contact layer, the n+ a-Si layer 10 is an active semiconductor layer, and the a- The Si layer 11 is a gate insulating layer and SiNx layer 12 is an insulating layer and is a gate insulating layer and is a SiNx layer 13 is a gate electrode 14 is a gate bus line 15 is a pixel electrode

Claims (3)

[Claims] 1. A transparent insulating substrate (1), a transparent insulating layer (3) covering the transparent insulating substrate (1), and a surface height of the transparent insulating layer (3) such that the transparent insulating layer (3) 3) A plurality of parallel data bus lines (6) embedded so as to be approximately equal to the height of the surface, and the transparent insulating layer (3)
Source/drain electrodes (7, 8) stacked sequentially on top
, active semiconductor layer (10), gate insulating layer (11, 12
), a thin film transistor matrix comprising a gate electrode (13) and a plurality of parallel gate bus lines (14) orthogonal to the plurality of parallel data bus lines (6) via an insulating layer (12). . 2. A first step of forming a transparent insulating layer (3) on a transparent insulating substrate (1);
) The transparent insulating layer (3) is etched using a mask (4) having a plurality of parallel grooves thereon to form an opening (5) in the transparent insulating layer (3). 5) is embedded with a metal layer so that the surface height is the transparent insulating layer (3)
The second step is to form a plurality of parallel data bus lines (6) approximately equal to the height of the surface, and the drain electrode (6) is formed by depositing a transparent conductor on the entire surface and patterning it.
7) and a third step of forming a source electrode (8), and depositing a semiconductor layer over the entire surface and then patterning it to form the transparent insulating layer between the drain electrode (7) and the source electrode (8). (3) The drain electrodes on both sides from above (
7) and a fourth step of forming an active semiconductor layer (10) extending over the source electrode (8), and forming a gate insulating layer (12) covering the active semiconductor layer (10) and extending over the entire surface. a fifth step of forming a gate electrode (13) on the active semiconductor layer (10) by depositing a metal layer on the gate insulating layer (12) and patterning it; a sixth step of forming a plurality of parallel gate bus lines (14) connected to the plurality of parallel data bus lines (6) and orthogonal to the plurality of parallel data bus lines (14) via the gate insulating layer (12); A method for manufacturing a thin film transistor matrix, characterized in that the first step to the sixth step are performed in this order. 3. The transparent insulating layer (3) is coated using a mask (4) having a plurality of parallel grooves on the transparent insulating layer (3).
) to form holes (5) in the transparent insulating layer (3).
), a metal layer is deposited on the entire surface so that the height of the surface of the metal layer filling the opening (5) is approximately equal to the height of the surface of the transparent insulating layer (3), and then the mask (4) is formed.
The upper metal layer is removed together with the mask (4), and the burrs (6a) of the metal layer formed around the periphery of the opening (5) are melted and smoothed by irradiation with light, and the transparent insulation is removed. 3. The method of manufacturing a thin film transistor matrix according to claim 2, characterized in that it comprises a second step of forming a plurality of parallel data bus lines (6) embedded in the layer (3).