JPH0433390A - Mounting on electronic circuit board - Google Patents
Mounting on electronic circuit boardInfo
- Publication number
- JPH0433390A JPH0433390A JP14023890A JP14023890A JPH0433390A JP H0433390 A JPH0433390 A JP H0433390A JP 14023890 A JP14023890 A JP 14023890A JP 14023890 A JP14023890 A JP 14023890A JP H0433390 A JPH0433390 A JP H0433390A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- electronic circuit
- insertion hole
- lead
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003780 insertion Methods 0.000 claims abstract description 40
- 230000037431 insertion Effects 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 239000011521 glass Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000002844 melting Methods 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 26
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 7
- 238000010292 electrical insulation Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000007650 screen-printing Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、電子部品等が実装された混成集積回路基板
またはプリント配線基板等の第１の電子回路基板にリー
ドフレームを嵌装し、該リードフレームを第２の電子回
路基板に形成された挿入孔に挿通し、半田付等をするこ
とにより、前記第１の電子回路基板を第２の電子回路基
板に実装する電子回路基板の実装方法に間し、さらに詳
細には、前記第１の電子回路基板に嵌装されたフレーム
リードと、第２の電子回路基板の挿入孔近傍に形成され
た導体パターンとを絶縁保護して、該第１の電子回路基
板を第２の電子回路基板に実装する電子回路基板の実装
方法に関するものである。Detailed Description of the Invention (Industrial Application Field) The present invention is directed to a first electronic circuit board, such as a hybrid integrated circuit board or a printed wiring board, on which electronic components, etc. are mounted, and which is fitted with a lead frame. A method for mounting an electronic circuit board in which the first electronic circuit board is mounted on a second electronic circuit board by inserting a lead frame into an insertion hole formed in a second electronic circuit board and performing soldering or the like. More specifically, the frame leads fitted into the first electronic circuit board and the conductor pattern formed in the vicinity of the insertion hole of the second electronic circuit board are insulated and protected. The present invention relates to an electronic circuit board mounting method for mounting one electronic circuit board onto a second electronic circuit board.
（従来の技術）
電子機器の高機能化にともなって、搭載される電子部品
も多種多様となっており、該電子機器を小型化に構成す
るために、例えば電気回路の一機能ブロックを混成集積
回路化した電子回路基板を他の電子回路基板に実装する
ということが行われている。(Prior Art) As electronic devices become more sophisticated, the number of electronic components mounted on them is becoming more diverse.In order to make electronic devices more compact, for example, one functional block of an electric circuit is mixed and integrated. 2. Description of the Related Art A circuitized electronic circuit board is mounted on another electronic circuit board.
上記の電子回路基板を他の電子回路基板に実装した例を
、第３図（ａ）、 （ｂ）を参照しながら説明する。An example in which the above electronic circuit board is mounted on another electronic circuit board will be described with reference to FIGS. 3(a) and 3(b).
アルミナ等の材質を有する第１の電子回路基板１には、
厚膜スクリーン印刷焼成法等を繰返すことにより、第１
基板の電極ランド５、第１基板の導体パターン１１及び
厚膜抵抗（図示省略）等が形成されている。The first electronic circuit board 1 made of a material such as alumina has
By repeating the thick film screen printing firing method, etc., the first
An electrode land 5 on the substrate, a conductor pattern 11 on the first substrate, a thick film resistor (not shown), etc. are formed.
該第１の電子回路基板ｌに形成された部品搭載ランド（
図示省略）には、受動及び能動等の第１基板の電子部品
１３が半田実装されている。A component mounting land (
(not shown), electronic components 13 of the first board, such as passive and active components, are soldered-mounted.
また、良導体よりなるストッパ部付フレームリード１６
は、該ストッパ部付フレームリード１６の本体より幅広
なるストッパ部１６ｃと嵌着部１６ａとが成型加工され
ている。In addition, the frame lead 16 with a stopper part made of a good conductor is
A stopper portion 16c and a fitting portion 16a, which are wider than the main body of the frame lead 16 with a stopper portion, are molded.
該ストッパ部付フレームリード１６の嵌着部１６ａは、
前記第１の電子回路基板１に形成された第１基板の電極
ランド５に嵌装されるとともに、第１基板の半田７によ
り半田付されている。The fitting portion 16a of the frame lead 16 with a stopper portion is
It is fitted into the electrode land 5 of the first substrate formed on the first electronic circuit board 1, and is soldered with the solder 7 of the first substrate.
一方、アルミナ等の材質を有するとともに、ストッパ部
付フレームリード１６が挿入される挿入孔４が貫通形成
された第２の電子回路基板２には、厚膜スクリーン印刷
焼成法等を繰返すことにより、第２基板の電極ランド６
、第２基板の導体パターン１２及び厚膜抵抗（図示省略
）等が形成されている。On the other hand, the second electronic circuit board 2, which is made of a material such as alumina and has an insertion hole 4 through which the frame lead 16 with a stopper part is inserted, is formed by repeating a thick film screen printing method or the like. Electrode land 6 on the second substrate
, a conductor pattern 12 of the second substrate, a thick film resistor (not shown), etc. are formed.
該第２の電子回路基板２に形成された部品搭載ランド（
図示省略）には、受動及び能動等の第２基板の電子部品
１４が半田実装されている。A component mounting land (
(not shown), electronic components 14 of the second board, such as passive and active components, are soldered and mounted.
前記第１の電子回路基板ｌに嵌装さ、れなストッパ部付
フレームリード１６は、該ストッパ部付フレームリード
１６のストッパ部１６ｃが第２の電子回路基板２に当接
されるまで挿入孔４に挿通される。The frame lead 16 with a curved stopper part fitted into the first electronic circuit board l is inserted into the insertion hole until the stopper part 16c of the frame lead with a stopper part 16 comes into contact with the second electronic circuit board 2. 4 is inserted.
従って、第１の電子回路基板ｌが、第２の電子回路基板
２に対し、ストッパ部高さＨを有して搭載される。Therefore, the first electronic circuit board 1 is mounted on the second electronic circuit board 2 with the stopper height H.
しかる後、ストッパ部付フレームリード１６と、第２の
電子回路基板２に形成された第２基板の電極ランド６と
が、第２基板の半田８により半田付される。Thereafter, the frame lead 16 with the stopper portion and the electrode land 6 of the second substrate formed on the second electronic circuit board 2 are soldered with the solder 8 of the second substrate.
さらに、ストッパ部付フレームリード１６は、第２基板
の半田８により半田固定された半田付部１６ｂを残して
、先方部が切断除去されている。Furthermore, the front part of the frame lead 16 with a stopper part is cut and removed, leaving the soldered part 16b fixed by the solder 8 of the second board.
上記のようにして、第１の電子回路基板１を、第２の電
子回路基板２に実装した場合、該第２の電子回路基板２
に成型された挿入孔４の近傍に形成された第２基板の導
体パターン１２と、ストッパ部付フレームリード１６と
が、該ストッパ部付フレームリード１６のストッパ部高
さＨの間隔を有していることにより、電気的に絶縁され
ており、該第２の電子回路基板２の面上における高密度
設計に対応している。When the first electronic circuit board 1 is mounted on the second electronic circuit board 2 as described above, the second electronic circuit board 2
The conductive pattern 12 of the second substrate formed near the insertion hole 4 formed in the shape of the frame lead 16 with a stopper part has an interval equal to the height H of the stopper part of the frame lead 16 with a stopper part. As a result, it is electrically insulated and supports high-density design on the surface of the second electronic circuit board 2.
また、前記ストッパ部付フレームリード１６と異なるフ
レームリードを使用して、第１の電子回路基板ｌを、第
２の電子回路基板２に実装する他の従来例を、第４図（
ａｌ、 （ｂ）並びに第５図を参照しながら説明する
。Another conventional example in which the first electronic circuit board 1 is mounted on the second electronic circuit board 2 using a frame lead different from the frame lead 16 with the stopper part is shown in FIG.
This will be explained with reference to al, (b) and FIG.
なお、先の従来例と同一の部分には、同一符号を付する
ことにより説明を省略する。Note that the same parts as in the prior art example are given the same reference numerals and the explanation thereof will be omitted.
良導体よりなるフレームリード３は、一方が折曲される
ことにより、嵌着部３ａが形成される。The frame lead 3 made of a good conductor is bent at one end to form a fitting portion 3a.
該フレームリード３の嵌着部３ａは、第１の電子回路基
板１に嵌装されて、第１基板の半田７により半田固定さ
れている。The fitting portion 3a of the frame lead 3 is fitted onto the first electronic circuit board 1 and fixed by solder 7 on the first board.
該フレームリード３の他方は、第２の電子回路基板２に
貫通形成された挿入孔４に挿通され、第２基板の半田８
により半田付されている。The other end of the frame lead 3 is inserted into an insertion hole 4 formed through the second electronic circuit board 2, and is connected to the solder 8 of the second board.
It is soldered by.
この際、フレームリード３が、該挿入孔４の直径より幅
広なるストッパ部を有しておらず、第２の電子回路基板
２の上面に、嵌着部３ａの底部が当接するまで、該フレ
ームリード３を挿通することができる。At this time, the frame lead 3 does not have a stopper part wider than the diameter of the insertion hole 4, and the frame lead 3 does not have a stopper part wider than the diameter of the insertion hole 4, and the frame lead 3 does not have a stopper part wider than the diameter of the insertion hole 4. The lead 3 can be inserted therethrough.
しかし、該フレームリード３の嵌着部３ａと、該第２の
電子回路基板２の挿入孔４の近傍に形成された第２基板
の導体パターン１２とが接触して電気的に短絡を起こす
恐れがある。However, there is a risk that the fitting portion 3a of the frame lead 3 and the conductive pattern 12 of the second board formed near the insertion hole 4 of the second electronic circuit board 2 may come into contact and cause an electrical short circuit. There is.
このため、第５図に示すように、第２の電子回路基板２
に形成された第２基板の導体パターン１２の、殊に挿入
孔４の近傍部に、絶縁テープｌＯを添付することにより
、嵌着部３ａと第２基板の導体パターン１２との電気的
絶縁を行っている。Therefore, as shown in FIG.
By attaching an insulating tape IO to the conductor pattern 12 of the second substrate formed on the second substrate, especially in the vicinity of the insertion hole 4, electrical insulation between the fitting portion 3a and the conductor pattern 12 of the second substrate can be achieved. Is going.
また、前記絶縁テープ１０の代わりに、非結化ガラスを
ペースト状に混練した非結晶化ガラスを厚膜スクリーン
印刷焼成法により、第２基板の導体パターン１２に被覆
するか、或いはシルク印刷法により、ソルダレジストを
第２基板の導体パターン１２に被覆することによりフレ
ームリード３と電気的に絶縁する方法が採られることも
ある。Further, instead of the insulating tape 10, the conductive pattern 12 of the second substrate may be coated with a non-crystallized glass obtained by kneading non-crystallized glass into a paste by a thick film screen printing method, or by a silk printing method. Alternatively, a method may be adopted in which the conductor pattern 12 of the second substrate is electrically insulated from the frame lead 3 by coating it with a solder resist.
（発明が解決しようとする課題）
しかしながら、上記従来の電子回路基板の実装方法によ
れば、第１の電子回路基板１を第２の電子回路基板２に
実装する際に、ストッパ部１６ｃを有するストッパ部付
フレームリード１６を使用して、該ストッパ部付フレー
ムリード１６と、第２の電子回路基板２の挿入孔４の近
傍に形成された第２基板の導体パターン１２との電気的
短絡を防止しているため、前記ストッパ部１６ｃのスト
ッパ部高さＨだけ第１の電子回路基板１の実装高さが高
くなるという問題点があった。(Problem to be Solved by the Invention) However, according to the conventional electronic circuit board mounting method described above, when mounting the first electronic circuit board 1 on the second electronic circuit board 2, the stopper portion 16c is not provided. The frame lead 16 with a stopper part is used to prevent an electrical short circuit between the frame lead 16 with a stopper part and the conductor pattern 12 of the second board formed near the insertion hole 4 of the second electronic circuit board 2. Therefore, there is a problem in that the mounting height of the first electronic circuit board 1 becomes higher by the stopper height H of the stopper part 16c.
また、第１の電子回路基板ｌの実装高さを抑えるために
、ストッパ部のないフレームリード３を使用した場合、
該フレームリード３と、第２の電子回路基板２の挿入孔
４近傍に形成された第２基板の導体パターン１２とを電
気的に絶縁するために、該第２基板の導体パターン１２
に絶縁保護用の絶縁テープｌＯを添付しなければならな
いという問題点があった。Furthermore, in order to reduce the mounting height of the first electronic circuit board l, if frame leads 3 without a stopper part are used,
In order to electrically insulate the frame lead 3 and the conductor pattern 12 of the second board formed near the insertion hole 4 of the second electronic circuit board 2, the conductor pattern 12 of the second board is
There was a problem in that an insulating tape 1O for insulation protection had to be attached to the insulator.
さらに、第２の電子回路基板２の挿入孔４近傍に形成さ
れた第２基板の導体パターン１２に、非結晶ガラスまた
は、ソルダレジスト等の絶縁部材を形成しても、該非結
晶ガラス並びにソルダレジストの電気的絶縁耐力等が十
分とはいえず、フレームリード３と、該第２基板の導体
パターン１２とが電気的短絡を起こす恐れがあるという
問題点があった。Furthermore, even if an insulating member such as amorphous glass or solder resist is formed on the conductive pattern 12 of the second substrate formed near the insertion hole 4 of the second electronic circuit board 2, the amorphous glass and solder resist The electrical dielectric strength of the frame lead 3 and the conductor pattern 12 of the second substrate are not sufficient, and there is a problem that an electrical short circuit may occur between the frame lead 3 and the conductor pattern 12 of the second substrate.
本発明は、上記事情に鑑みてなされたものであり、第１
の電子回路基板を第２の電子回路基板に実装する際のフ
レームリードのストッパ部高さをな（するとともに、該
フレームリードが挿通される挿入孔の近傍に形成された
第２基板の導体パターンを、電気的絶縁耐力の十分な絶
縁保護部材を使用して被覆することにより、該フレーム
リードと第′２基板の導体パターンとの電気的絶縁を行
った電子回路基板の実装方法を提供するものである。The present invention has been made in view of the above circumstances, and is
The height of the stopper part of the frame lead when mounting the electronic circuit board on the second electronic circuit board (and the conductor pattern of the second board formed near the insertion hole through which the frame lead is inserted) Provided is a method for mounting an electronic circuit board in which the frame lead and the conductor pattern of the '2nd board are electrically insulated by covering the frame lead with an insulating protection member having sufficient electrical dielectric strength. It is.
（課題を解決するための手段）
上記目的を達成するために、この発明は、少なに電子部
品が実装された第１の電子回路基板のフレームリードを
、第２の電子回路基板に形成された挿入孔に挿通するこ
とにより、該第１の電子回路基板を第２の電子回路基板
に実装する電子回路基板の実装方法において、前記第１
の電子回路基板のリードフレームが挿通される第２の電
子回路基板の挿入孔近傍に形成された導体パターンに、
該リードフレームと導体パターンとの絶縁を行う絶縁部
材を被覆し、該第１の電子回路基板のリードフレームを
第２の電子回路基板の挿入孔に挿通することにより、前
記第１の電子回路基板を第２の電子回路基板に実装する
ことにより、上記目的を達成するものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides frame leads of a first electronic circuit board on which a few electronic components are mounted, which are formed on a second electronic circuit board. In the electronic circuit board mounting method, the first electronic circuit board is mounted on a second electronic circuit board by inserting the first electronic circuit board into an insertion hole.
A conductive pattern formed near the insertion hole of the second electronic circuit board into which the lead frame of the electronic circuit board is inserted,
The first electronic circuit board is covered with an insulating member that insulates the lead frame and the conductor pattern, and the lead frame of the first electronic circuit board is inserted into the insertion hole of the second electronic circuit board. The above object is achieved by mounting the electronic circuit board on the second electronic circuit board.
また、本発明は、前記第１の電子回路基板に嵌装された
リードフレームに対して、第２の電子回路基板の挿入孔
近傍に形成された導体パターンを絶縁する絶縁部材に、
高融点系の結晶化ガラスペーストを使用したことにより
、上記目的を達成するものである。The present invention also provides an insulating member that insulates a conductive pattern formed near the insertion hole of the second electronic circuit board from the lead frame fitted to the first electronic circuit board.
The above object is achieved by using a high melting point crystallized glass paste.
くとも一つのフレームリードが嵌装されるととも（作用
）
本発明においては、第１の電子回路基板を第２の電子回
路基板に実装する際に使用するフレームリードが、第２
の電子回路基板に形成された挿入孔の直径よりも幅広な
るストッパ部を有しておらず、第１の電子回路基板に嵌
装されたフレームリードの嵌着部まで、該フレームリー
ドを挿入孔に挿通可能となっており、第１の電子回路基
板の実装高さを最も低背にすることができるとともに、
該挿入孔の近傍に形成された第２基板の導体パターンを
、電気的絶縁耐力に優れ、且つ化学的に安定した結晶化
ガラスをペースト状に混線した絶縁保護用結晶化ガラス
にて被覆しているため、該第２基板の導体パターンを、
前記フレームリードより電気的に絶縁することができる
。In the present invention, when at least one frame lead is fitted, the frame lead used when mounting the first electronic circuit board to the second electronic circuit board is fitted to the second electronic circuit board.
It does not have a stopper part wider than the diameter of the insertion hole formed in the first electronic circuit board, and the frame lead is inserted into the insertion hole until it reaches the fitting part of the frame lead fitted in the first electronic circuit board. The mounting height of the first electronic circuit board can be made the lowest, and
The conductor pattern of the second substrate formed in the vicinity of the insertion hole is covered with an insulation-protecting crystallized glass which has excellent electrical dielectric strength and is made of chemically stable crystallized glass mixed in paste form. Therefore, the conductor pattern of the second substrate is
It can be electrically insulated from the frame lead.
（実施例〉 本発明の実施例を、図面に基いて詳細に説明する。(Example> Embodiments of the present invention will be described in detail based on the drawings.
第１図は本発明に係わる電子回路基板の実装方法の実施
例を示す要部拡大断面図、第２図（ａ）〜（ｃ）は絶縁
保護用結晶化ガラスの形成手順を示す一部平面図が示さ
れている。FIG. 1 is an enlarged cross-sectional view of a main part showing an embodiment of the electronic circuit board mounting method according to the present invention, and FIGS. 2(a) to (c) are partial plane views showing the procedure for forming a crystallized glass for insulation protection. A diagram is shown.
第２図（ａ）に示すように、アルミナ等の材質を有する
第２の電子回路基板２２には、同一ピッチ且つ一列をな
して挿入孔２４が貫通形成されている。As shown in FIG. 2(a), insertion holes 24 are formed through a second electronic circuit board 22 made of a material such as alumina and arranged at the same pitch and in a line.
該第２の電子回路基板２２の挿入孔２４の近傍には、電
子機器の小型化に伴って高密度パターン化した第２基板
の導体パターン３２が、例えばＡｇ／Ｐｄ（銀パラジウ
ム）ペーストを、厚膜スクリーン印刷し、１５０℃、１
０分乾燥し、８５０℃、１０分焼成することにより形成
されている。In the vicinity of the insertion hole 24 of the second electronic circuit board 22, the conductor pattern 32 of the second board, which has been patterned with high density in accordance with the miniaturization of electronic devices, is coated with, for example, Ag/Pd (silver palladium) paste. Thick film screen printing, 150℃, 1
It is formed by drying for 0 minutes and baking at 850°C for 10 minutes.
次に、第２図（ｂ）に示すように、挿入孔２４の近傍の
第２基板の導体パターン３２を被覆するように、絶縁保
護用結晶化ガラス３０が、例えば、はうけい酸鉛ガラス
等の高融点系の結晶化ガラス（結晶化ガラス９０％、非
結晶化ガラス１０％）ペーストを厚膜スクリーン印刷し
、１５０℃、１０分乾燥し、８５０℃、１０分焼成する
ことにより形成されていさらに、第２図（Ｃ）に示すよ
うに、挿入孔２４を除く第２の電子回路基板２２の上面
には、保護ガラス３５が、例えば非結晶化ガラスペース
トを厚膜スクリーン印刷し、１５０℃、１０分乾燥し、
５３０℃、３分焼成することにより形成されている。Next, as shown in FIG. 2(b), an insulating protective crystallized glass 30, such as lead silicate glass, is applied so as to cover the conductor pattern 32 of the second substrate near the insertion hole 24. It is formed by thick film screen printing of high melting point crystallized glass (90% crystallized glass, 10% amorphous glass) paste, dried at 150℃ for 10 minutes, and baked at 850℃ for 10 minutes. Furthermore, as shown in FIG. 2(C), a protective glass 35 is formed on the upper surface of the second electronic circuit board 22 excluding the insertion hole 24 by thick film screen printing of, for example, amorphous glass paste. ℃, dry for 10 minutes,
It is formed by firing at 530°C for 3 minutes.
前記第２の電子回路基板２２の反対面には、上面と同様
の厚膜スクリーン印刷焼成法を繰返すことにより、第２
基板の電極ランド２６、厚膜抵抗（図示省略）等が形成
されている。The opposite side of the second electronic circuit board 22 is coated with a second layer by repeating the same thick film screen printing and baking method as for the top side.
An electrode land 26 of the substrate, a thick film resistor (not shown), etc. are formed.
さらに、前記第２の電子回路基板２２には、図示しない
部品搭載ランドが形成され、該部品搭載ランドに受動及
び能動等の電子部品（図示省略）が実装されている。Furthermore, a component mounting land (not shown) is formed on the second electronic circuit board 22, and passive and active electronic components (not shown) are mounted on the component mounting land.
一方、第１図に示すように、アルミナ等の材質を有する
第１の電子回路基板２１には、厚膜スクリーン印刷焼成
法等を繰返すことにより、第１基板の電極ランド２５、
第１基板の導体パターン３１及び厚膜抵抗（図示省略）
等が形成されている。On the other hand, as shown in FIG. 1, the electrode lands 25 and
Conductor pattern 31 and thick film resistor (not shown) on the first substrate
etc. are formed.
該第１の電子回路基板２１に形成された部品搭載ランド
（図示省略）には、受動及び能動等の電子部品（図示省
略）が半田実装されている。Passive and active electronic components (not shown) are soldered onto component mounting lands (not shown) formed on the first electronic circuit board 21 .
また、良導体よりなるフレームリード２３は、一方が折
曲されて嵌着部２３ａが形成されている。Further, one end of the frame lead 23 made of a good conductor is bent to form a fitting portion 23a.
該フレームリード２３の嵌着部２３ａは、第１の電子回
路基板２１の第１基板の電極ランド２５に嵌装されて、
第１基板の半田２７により半田固定されている。The fitting portion 23a of the frame lead 23 is fitted into the electrode land 25 of the first substrate of the first electronic circuit board 21,
It is soldered and fixed by solder 27 on the first board.
該フレームリード２３の他方は、前記挿入孔２４に、嵌
着部２３ａの底部と、前記保護ガラス３５とが当接する
まで挿通され、第２基板の半田２８により、第２の電子
回路基板２２に形成された第２基板の電極ランド２６に
半田付されている。The other side of the frame lead 23 is inserted into the insertion hole 24 until the bottom of the fitting part 23a and the protective glass 35 come into contact, and is connected to the second electronic circuit board 22 by the solder 28 of the second board. It is soldered to the electrode land 26 of the formed second substrate.
しかる後、フレームリード２３は、第２基板の半田２８
により半田固定された半田付部２３ｂを残して、先方部
が切断除去されている。After that, the frame lead 23 is connected to the solder 28 of the second board.
The front part is cut and removed, leaving the soldered part 23b fixed by soldering.
上記のようにして、第１の電子回路基板２１が、第２の
電子回路基板２２に実装されている。The first electronic circuit board 21 is mounted on the second electronic circuit board 22 as described above.
この際、フレームリード２３が、該挿入孔２４の直径よ
り幅広なるストッパ部を有しておらず、第２の電子回路
基板２２の上面に形成された保護ガラス３５に、該嵌着
部２３ａが当接するまで、該フレームリード２３が挿通
されており、従って第１の電子回路基板２１の実装高さ
を最も低背にすることができる。At this time, the frame lead 23 does not have a stopper portion wider than the diameter of the insertion hole 24, and the fitting portion 23a is attached to the protective glass 35 formed on the upper surface of the second electronic circuit board 22. The frame lead 23 is inserted until the first electronic circuit board 21 comes into contact with the first electronic circuit board 21, so that the mounting height of the first electronic circuit board 21 can be made the lowest.
また、第２の電子回路基板２２の挿入孔２４近傍の第２
基板の導体パターン３２上に絶縁保護用結晶化ガラス３
０が形成されているため、該第２の電子回路基板２２に
実装された第１の電子回路基板２１に嵌装されたフレー
ムリード２３より、前記第２基板の導体パターン３２の
電気的絶縁保護を十分に行うことができる。Further, the second electronic circuit board 22 near the insertion hole 24
Crystallized glass 3 for insulation protection is placed on the conductor pattern 32 of the substrate.
0 is formed, the electrical insulation protection of the conductor pattern 32 of the second board is better than the frame lead 23 fitted to the first electronic circuit board 21 mounted on the second electronic circuit board 22. can be carried out satisfactorily.
（発明の効果）
本発明に係わる電子回路基板の実装方法は、上記のよう
に構成されているため、以下に記載するような効果を有
する。(Effects of the Invention) Since the electronic circuit board mounting method according to the present invention is configured as described above, it has the following effects.
（Ａｌ第１の電子回路基板に嵌装されたフレームリード
が、第２の電子回路基板に形成された挿入孔の直径より
幅広なるストッパ部を有していないため、該第１の電子
回路基板を第２の電子回路基板に実装する実装高さを最
も低背にすることができ、電子回路機器の小型化に寄与
することができるという優れた効果を有する。(Since the frame lead fitted into the Al first electronic circuit board does not have a stopper portion wider than the diameter of the insertion hole formed in the second electronic circuit board, the first electronic circuit board This has an excellent effect in that the mounting height for mounting the second electronic circuit board on the second electronic circuit board can be made the lowest, contributing to miniaturization of electronic circuit devices.
（Ｂ）また、第２の電子回路基板の挿入孔近傍に形成さ
れた第２基板の導体パターンを被覆するように、絶縁保
護用結晶化ガラスが形成されているため、該第２基板の
導体パターンと、第１の電子回路基板に嵌装されたフレ
ームリードとが、電気的に短絡することがなくなるため
、信頼性の高い電子機器を供給することができるという
優れた効果を有する。(B) Also, since the insulation protection crystallized glass is formed to cover the conductor pattern of the second board formed near the insertion hole of the second electronic circuit board, the conductor pattern of the second board is formed. Since the pattern and the frame lead fitted to the first electronic circuit board are not electrically short-circuited, there is an excellent effect that a highly reliable electronic device can be provided.
（Ｃ１さらに、第２基板の導体パターンを、フレームリ
ードより電気的に保護する絶縁保護用結晶化ガラスを厚
膜スクリーン印刷焼成法により形成しているため、絶縁
テープ等を該第２基板の導体パターンに添付するという
煩雑な作業を削除することができ、電子回路の組立を容
易ならしめるという優れた効果を有する６(C1 Furthermore, since the insulating protective crystallized glass that electrically protects the conductor pattern of the second board from the frame lead is formed by a thick film screen printing and firing method, insulating tape etc. It has the excellent effect of making it easier to assemble electronic circuits by eliminating the complicated work of attaching them to patterns6.
第１図は本発明に係わる電子回路基板の実装方法の実施
例を示す要部拡大断面図、
第２図（ａ）〜（ｃ）は絶縁保護用結晶化ガラスの形成
手順を示す一部平面図、
第３図（ａ）、 （ｂ）は従来の電子回路基板の実装
方法を示す側面図、
第４図（ａ）、 （ｂ）は他の従来の電子回路基板の
実装方法を示す側面図、
第５図は他の従来の電子回路基板の実装方法を示す要部
拡大側面図である４
２１・・・第１の電子回路基板、
２２・・・第２の電子回路基板、
２３・・・フレームリード、
２４・・・挿入孔、３０・・・保護ガラス、３０・・・
絶縁保護用結晶化ガラス。FIG. 1 is an enlarged sectional view of the main part showing an embodiment of the electronic circuit board mounting method according to the present invention, and FIGS. 2(a) to (c) are partial plane views showing the procedure for forming the crystallized glass for insulation protection. Figures 3(a) and 3(b) are side views showing a conventional electronic circuit board mounting method, and Figures 4(a) and (b) are side views showing another conventional electronic circuit board mounting method. FIG. 5 is an enlarged side view of main parts showing another conventional electronic circuit board mounting method. 4 21. First electronic circuit board. 22. Second electronic circuit board. ... Frame lead, 24... Insertion hole, 30... Protective glass, 30...
Crystallized glass for insulation protection.
Claims (2)
ともに電子部品が実装された第１の電子回路基板のフレ
ームリードを、第２の電子回路基板に形成された挿入孔
に挿通することにより、該第１の電子回路基板を第２の
電子回路基板に実装する電子回路基板の実装方法におい
て、前記第１の電子回路基板のリードフレームが挿通さ
れる第２の電子回路基板の挿入孔近傍に形成された導体
パターンに、該リードフレームと導体パターンとの絶縁
を行う絶縁部材を被覆し、該第１の電子回路基板のリー
ドフレームを第２の電子回路基板の挿入孔に挿通するこ
とにより、前記第１の電子回路基板を第２の電子回路基
板に実装することを特徴とする電子回路基板の実装方法
。(1) By inserting the frame lead of the first electronic circuit board, on which at least one frame lead is fitted and electronic components are mounted, into the insertion hole formed in the second electronic circuit board, In the electronic circuit board mounting method of mounting a first electronic circuit board on a second electronic circuit board, the lead frame of the first electronic circuit board is formed near the insertion hole of the second electronic circuit board through which the lead frame is inserted. The conductive pattern is coated with an insulating member that insulates the lead frame and the conductive pattern, and the lead frame of the first electronic circuit board is inserted into the insertion hole of the second electronic circuit board. A method for mounting an electronic circuit board, comprising mounting a first electronic circuit board on a second electronic circuit board.
ームに対して、第２の電子回路基板の挿入孔近傍に形成
された導体パターンを絶縁する絶縁部材に、高融点系の
結晶化ガラスペーストを使用したことを特徴とする請求
項１記載の電子回路基板の実装方法。(2) High-melting point crystallization is applied to an insulating member that insulates a conductor pattern formed near the insertion hole of the second electronic circuit board with respect to the lead frame fitted to the first electronic circuit board. 2. The method of mounting an electronic circuit board according to claim 1, wherein a glass paste is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14023890A JPH0433390A (en) | 1990-05-30 | 1990-05-30 | Mounting on electronic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14023890A JPH0433390A (en) | 1990-05-30 | 1990-05-30 | Mounting on electronic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0433390A true JPH0433390A (en) | 1992-02-04 |
Family
ID=15264124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14023890A Pending JPH0433390A (en) | 1990-05-30 | 1990-05-30 | Mounting on electronic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0433390A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110321A (en) * | 2000-09-29 | 2002-04-12 | Kyocera Corp | Ceramic heater and wafer heating device using the same |
-
1990
- 1990-05-30 JP JP14023890A patent/JPH0433390A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110321A (en) * | 2000-09-29 | 2002-04-12 | Kyocera Corp | Ceramic heater and wafer heating device using the same |
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