JPH0433377A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively form a microscopic diffused region having a size of 1.0mum or less on the sidewall of a cut part such as a U-shaped groove, etc., in high yield by forming the groove by totally three times cutting steps, and forming an oxide film in the bottom of a third groove with nonoxidative films formed on the sidewalls of the first to third grooves as masks. CONSTITUTION:An operating layer of an n<-> type layer 2 is grown on an n<+> type Si substrate 1, and an oxide film 5 is then formed. Then, with the part except a cut region as a mask the film 5 is removed and the layer 2 is cut. An oxide film 5 is formed on the cut part, and the film 5 in the cut bottom and the layer 2 in the bottom are etched. A thin oxide film 52 is formed only on the sidewall of the cut part, and a cutting depth is further added by third cutting. An Si3N4 film 9 is formed only on the sidewall. Then, with the film 9 as a mask a thermal oxide film 59 is formed in the bottom of the cut part by a selectively oxidizing method. When the film 9 of the sidewall is removed, a gate diffusing window is opened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a high-speed, low-power semiconductor device, and in particular, it relates to a method for manufacturing a semiconductor device with high speed and low power consumption. The present invention relates to a processing technology related to a process of forming a diffusion region with a size of , and opening a contact hole.

[Prior Art] The recent development of semiconductor devices has been remarkable, with the goal of achieving high speed, low power consumption, high efficiency, and high integration density.
C, memory, etc. have been proposed. It is easier to control dimensions in the thickness direction than in the planar direction, and a three-dimensional structure is required to meet the demands for ultra-high density such as 64M bit dynamic RAM. Various semiconductor devices have been proposed that require processing techniques for vertical surfaces. In particular, static induction type semiconductor devices such as static induction transistors (hereinafter referred to as SITs) have basically excellent characteristics by forming gates on sidewalls cut perpendicularly from the semiconductor substrate surface. Furthermore, it is known that it is suitable for high-frequency, high-speed operation. Second
The figure is an example of a cross-sectional view of a notched gate type SIT.
The i-substrate 1 is the drain, the n- layer 2 is the channel, the p" region 3 is the gate, the n+ region 4 is the source, and the gate electrode 6 is formed on the oxide film 5, so that there is no contact between the source and the gate. Since the capacitance and gate-to-be-rein capacitance can be reduced and the conversion conductance g can be increased, it is suitable for high-efficiency operation in the microwave to submillimeter wave band. 7 is a source electrode.

However, in a semiconductor device having a cut from the semiconductor surface, processing such as forming a diffusion window or contact hole on the side wall surface of the cut is almost impossible using photolithography technology, which is the basis of conventional planar processing technology. Ta.

[Problems to be Solved by the Invention] A technique for forming a diffusion window and a contact window on the side wall surface of a notch in a semiconductor device having the above-mentioned notch (U-shaped groove) is disclosed in Japanese Patent Publication No. 62-32632. , and Japanese Patent Publication No. 01-031309 have been proposed. Figures 3(a) to (j) show the N channel S shown in the above-mentioned Japanese Patent Publication No. 82-32632.
This is an IT manufacturing process.

(1> As shown in Figure 3(a), n”s becomes the drain
An n-layer (impurity density 10'8/cIn3) is formed by epitaxial growth on an i-substrate (impurity density 10'8/cIn3)
014/cff13)2 is grown to a thickness of about 10-100 m, and then an oxide film 5 of about 1 μm is formed by thermal oxidation or the like. Next, a resist film 8 such as 0MR83 is selectively formed in a portion other than the area to be cut using a photolithography technique.

(2) As shown in FIG. 3(b), the oxide film 5 is removed using the resist 8 as a mask, and the n- layer 2 is cut to a depth of approximately 3 μ-. In this case, it is desirable that the side surfaces of the cut portion be almost perpendicular to the surface of the n-layer 2, and it is also desirable that the bottom surface be nearly flat, but the best way to do this is by alkaline etching so that the sides are perpendicular. Plasma etching, sputter etching, etc., which also make the bottom surface flat, are examples. For example, to perform plasma etching, select the crystal plane of the n゛ substrate 1 to be the (111) plane, align the mask direction to the <110> direction, and first coat the oxide film 5 with C3F8 gas O, 1 Torr.
Plasma etch with pcp3 gas 0.05
~0. If the n-layer 2 is plasma-etched instead of using LTorr, it is possible to cut into a shape having side surfaces (wall surfaces) perpendicular to the surface of the n-layer 2 and a flat bottom surface. followed by 0
□Remove the resist 8 using gas plasma.

(3) As shown in FIG. 3(c), an oxide film 5 of about 5000λ is formed on the cut portion by thermal oxidation or the like. At this time, the oxide film 5 on the surface of the n-layer 2 formed in step 1 is 1.1
It increases to about μAkebono.

(4) As shown in FIG. 3(d), the oxide film 5 on the bottom surface is cut by directional plasma etching, sputter etching, etc.
have sex with In this case, the oxide film 5 on the side surface (wall surface) remains due to the directivity, and the oxide film 5 on the surface of the n-layer 2 has a thickness of 8000λ.
decrease to a certain degree. Subsequently, the n-layer 2 on the cut bottom surface is plasma etched to a depth of about 1.5 μm. For example, to perform plasma etching, H5 oxide is C3F s D, 1T
The n-layer 2 is etched with PC130,05~0.
It can be formed by etching with ITorr.

(5) As shown in Figure 3(e), Si3 is formed by CVD etc.
Form N4@9 with a thickness of about 1000λ.

(6) As shown in Figure 3(f), the bottom surface is cut by directional plasma etching, sputter etching, etc.
5i3N411' on the surface of i3N4 film 9 and n- layer 2;+
have sex with S i 3N a JI! 9 will remain only on the cut side (wall surface). For example, to perform plasma etching, C3F80.02~0.05
It can be formed by etching with Torr.

(7) As shown in FIG. 3(g), approximately 5000λ of oxide 1II59 is formed on the cut bottom surface by thermal oxidation or the like. At this time, the cut side where 5i3N4s9 is (
The oxide film 59 is not formed on the wall surface.

The oxide film 5 on the surface of the n-layer 2 increases to about 8,000 layers.

(8) As shown in FIG. 3(h), the oxide film 5 above the region that will become the source is formed on the surface of the n-layer 2 by photolithography.
is removed and the n° region 10 (impurity density ~
1021/cI113 is formed to a depth of about 0.5μ. In this case, As, which has a high masking property in 5L3N4, is used as an impurity source.

(9) As shown in FIG. 3(i), if the Si and N4 films 9 on the cut side (wall surface) are etched by non-directional plasma etching, hot phosphoric acid etching, etc., the openings in the oxide film 5 will be formed. By diffusion, etc., the gate of p+ region 11 is formed by about 1.0 μm from the side surface (end surface).
Form to a depth of ■.

The impurity density of this gate is lower than the impurity density of the n+ region 10, and is suppressed to about 1020 to 10'9/cm3.

Therefore, the n+ region 10 does not need to be masked and the p
``Even if region 11 is formed, there is little effect.

(10) As shown in FIG. 3(j), a metal film such as AI is formed to a thickness of about 1.5 μm by vapor deposition or the like, and is formed on the gate electrode 12 and the source electrode 13 by photolithography. Normal vapor deposition is directional, so it is deposited only on the surface of the n-layer 2 and the bottom surface of the cut, and only the scattered portion is deposited on the side surfaces (walls), so there is no need for photolithography technology. The gate electrode 12 can be easily etched by etching the entire surface.
, the source electrode 13 can also be separated. Note that a metal film is also deposited on the lower surface to form the drain electrode 14.

[Problems to be Solved by the Invention] However, according to the method shown in FIG. 3, the width of the opening as a gate diffusion window in the direction perpendicular to the substrate surface is 1.0
If the size is relatively large, on the order of μ- or more, it is easy to form a p” region 11 on the side wall surface by diffusion as shown in FIG. 3, or the width of the opening as a gate diffusion window is 1.
When the fine dimensions are smaller than 0 μ-, a problem arises in that the p+ region 11 is not sufficiently formed, or is formed only partially. As a result, the gate effectiveness becomes poor and the conversion fundance g decreases. Another drawback was that it would not operate unless a high voltage was applied to the gate. Figure 4 shows the drain current 1d vs. drain voltage Vd characteristic of SIT when the gate diffusion window width on the sidewall is 0.7 μm, but the gate does not work unless a gate voltage of 3 V or more is applied, and it operates effectively as an SIT. I knew not to.

Therefore, according to the manufacturing method shown in FIG. 3, the requirements for power-saving (low power consumption) and high-efficiency junction-type SITs that operate at a power supply voltage of 1.5V and high-frequency junction-type SITs with a cut-off frequency of 10 GHz or higher are achieved. The drawback is that it is extremely difficult to open diffusion windows and contact holes with minute dimensions of 1.0 μm or less.

When the width of the gate diffusion window is less than 1.0 μm, it becomes difficult to open the window because the cross-sectional shape of the second plasma etching in Figure 3(d) is similar to that shown in Figure 5(a), which makes it difficult to open the gate diffusion window at the bottom and side walls. Since the boundaries of the parts are rounded, when selective oxidation is performed, a so-called planar LOCOS (LOCOS: L) is formed, as shown in FIG. 5(b).

cal Oxidation of 5ilic
It was found that this is due to the problem that the bird's beak portion in the (on) process becomes larger and the oxide film 59 enters the lower part of the 5i3N49 more than necessary, resulting in a smaller opening.

Furthermore, it is important to reduce the capacitance between the gate and drain in order to increase the frequency of the junction type SIT, and for this purpose, the oxide film 59
The thicker the better. In order to thicken the oxide film 59, it is desirable that the plasma etching in FIG. 3(d) be as deep as possible, reaching as far as the substrate if possible. However, in highly directional plasma etching to form vertical sidewalls, the lower the pressure of the etching gas, the better; however, as the pressure decreases, the sputtering effect becomes stronger and the etching selectivity between the oxide film and St2 becomes smaller. Therefore, if deep S1 etching was performed under conditions of high directivity, the oxide film 5 would be lost.

The object of the present invention has been made in view of the drawbacks of the conventional processing technology in the direction perpendicular to the surface of the substrate as described above. It is an object of the present invention to provide a method for manufacturing a semiconductor device that operates at low power consumption, high efficiency, and high frequency, which can reliably form a minute diffusion region with high yield.

Another object of the present invention is to provide a new method for reliably opening a diffusion window or a contact hole in the side wall of a cut portion such as a U-shaped groove, even if the directivity of plasma etching is relatively poor. be.

Another object of the present invention is to create a good etching cross-sectional shape with deep and vertical sidewalls without being limited by the trade-off relationship between directivity and selectivity (Si:oxide film) in plasma etching. An object of the present invention is to provide a method for manufacturing a semiconductor device. Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of high frequency operation by thickening the oxide film under the gate electrode.

[Means and effects for solving the problem] In order to achieve this object, in the method according to the present invention, a U-shaped groove is formed with a first cut, the entire surface of this U-shaped groove is oxidized, and then a U-shaped groove is formed.
A process of leaving the oxide film on the side walls of the mold groove and removing only the oxide film at the bottom, followed by a process of making a second cut to a depth equivalent to the diffusion window size, and a process of removing the oxide film on the side wall of the groove formed by the second cut. A step of forming a thin oxide film of about 300 to 1000 layers, a step of making a third cut in succession to the groove formed by the second cut, and a groove formed by the first to third cuts. A step of forming a non-oxidizing film such as a nitride film on the side wall surface of the groove and selectively oxidizing the bottom surface of the groove, and a step of exposing only a predetermined location on the side wall surface by removing the non-oxidizing mask. It is characterized by little coexistence.

[Example] Hereinafter, a method for manufacturing a cut-gate type SIT according to a first example of the present invention will be described with reference to the drawings.

(1) As shown in Figure 1(a), n”S becomes the drain.
An n-layer (impurity density 1013 to 1
An active layer of 0''/(1)3)2 is grown to a thickness of about 5 .mu.m, and then an oxide film 5 of about 1 .mu.l is formed by thermal oxidation or the like.

Next, a resist film 8 such as 0MR83 is selectively formed in a portion other than the cut region by photolithography.

(2) As shown in FIG. 1(b), the oxide film 5 is removed using the resist 8 as a mask, and the n- layer 2 is approximately 0.0. Cut to the depth of the γμ intestine (first cutting step).

In this case, it is desirable that the sides of the part to be cut be almost perpendicular to the surface of the n-layer 2, and it is also desirable that the bottom surface be nearly flat, or alternatively, the method is alkaline etching in which the sides are perpendicular. Plasma etching, sputter etching, etc., which also make the bottom surface flat, are examples. For example, to perform plasma etching, the crystal plane of n+ substrate 1 is (111)
Select the surface and align the direction of the mask to the <110> direction, first plasma-etch the oxide film 5 with C3F8 gas at 0.1 Torr, then use PCII gas and gas at 0.05 to 0.1 Torr.
If you change to Torr and plasma-etch n- layer 2, n-
It is possible to cut into a shape having side surfaces (wall surfaces) perpendicular to the surface of layer 2 and a flat bottom surface. Subsequently, the resist 8 is removed using 02 gas plasma.

(3) As shown in FIG. 1(c), oxide M5 of about 5000λ is formed in the cut portion by thermal oxidation or the like. At this time, the oxide film 5 on the surface of the n-layer 2 formed in step 1 is 1.1
It increases to about μm.

(4) As shown in FIG. 1(d), the oxide film 5 on the bottom surface is cut by directional plasma etching, sputter etching, etc.
have sex with In this case, the oxide film 5 on the side surfaces (wall surfaces) remains due to the directivity, and the oxide film 5 on the surface of the n- layer 2 is reduced to about 6,000 layers.

Subsequently, the cut n-layer 2 on the bottom surface is further plasma etched by about 0.5 μm (second cut). This second
In the notch, the requirement for etching directionality is relaxed, so relatively isotropic etching is sufficient as shown in FIG. 1(d). Therefore, PCl3
The gas pressure may be on the high pressure side of 0.1 to 0.2 Torr, and since the selectivity (Sl/Si 02 ) at this time is extremely high, the oxide film 5 is hardly thinned in the second incision.

(5) As shown in FIG. 1(e), a thin oxide film 52 of 300 to 1000 layers is formed on the entire surface by thermal oxidation, etc., and this thin oxide film 52 is left only on the side wall surface of the cut portion by directional plasma etching. .

(6) As shown in FIG. 1(f), add an additional 0.5μ deep cut by making the third cut.

In order to increase the frequency of SIT, it is desirable to make the third cut approximately 5 .mu.m until it reaches the substrate.

In this case, as shown in FIG. 1h(f), the etching directionality is somewhat poor and isotropic etching may be sufficient, so that the selectivity to the oxide film is increased accordingly and deep etching is possible. In 20g3 plasma etching, if you sacrifice directivity and etch on the high pressure side, the selectivity can be 30.
~50 can be easily achieved. Considering the bird's beak in LOGO3 on the side wall, plasma etching of the third notch is done in two stages, first at a high pressure of 0.1 to 0.2.
Etch with Torr, and when the desired depth is reached, 0
．． If etching is switched to etching at 0.03 to 0.05 Torr, the bottom surface of the notch and the side wall surface will have a nearly perpendicular cross-sectional shape. As mentioned above, if the third cut is about 0.5 μm or less, the gas pressure is 0.03 to 0.05 To from the beginning.
It may be etched with rr.

(7) As shown in Figure 1 (g), 5is is made by CVD etc.
About 1,000 to 1,300 people form the N4 film 9.

(8) As shown in Figure 1 (h), 513N4 only on the side wall surface was removed by directional plasma etching, sputter etching, etc.
The film 9 is left and the rest are removed by etching. Next, this S
Using the i3N4 film 9 as a mask, apply 3000 μm to the bottom of the cut.
A thermal oxide film 59 of ~4000 layers is formed by a selective oxidation method. As shown in Fig. 1(f), an oxide of about 4 to 4.5 μm is deposited in advance by directional electron beam evaporation of SiO2 or S10 before thermal oxidation.
Deposit m. When oxide is deposited on the four parts by the normal vapor deposition method, the oxide is deposited in a trapezoidal shape in the recess, and a gap is created between the sidewall of the recess and the trapezoidal oxide, which can be filled by thermal oxidation.

(9) As shown in FIG. 1(i), an n'' region 10 that will become a source is formed with a thickness of about 0.3 to 0.5 μm on the surface near the center of the convex portion of the n-layer 2 by photolithography. By using 75A s' ion implantation, a source region with an impurity density of about 102Icrn-3 can be easily formed.After the ion implantation, by thermal oxidation, etc., a 3000 to 3500% impurity concentration is formed in the upper part of the source diffusion window. Forms an oxide film on humans.

As a result, the oxide film 59 on the bottom surface of the notch has a density of 5000 to 60%.
It will be 00 people thick.

(10) As shown in FIG. 1(j), if the Sl and N4 films 9 on the sidewalls are removed by non-directional plasma etching, hot phosphoric acid etching, etc., the gate diffusion window will be removed by 0.4 to 0.5 μm. The hole is drilled with a width of . This opening has an impurity density of 5 x l.
Boron is diffused to a depth of about 0.5 μ- from the side wall surface with a Q l of about 8 to 1020 crn-3. After diffusion, if BSG is formed on the surface of the opening, remove it by etching.
Drill a gate contact hole. Next, the oxide film above the source diffusion region 10 is removed by photolithography, a source contact hole is opened, and the gate electrode 12, source electrode 13,
A train electrode 14 is formed.

[Effects of the Invention] According to the present invention, a region of any conductivity type can be selectively provided at any position on the side wall surface of the cut portion of the semiconductor substrate. Furthermore, according to the present invention, in the selective oxidation of the sidewall portion, the so-called bird's beak, which is the digging of the oxide film under the Si and N4 films as a mask, becomes extremely small, so it is possible to control the opening of minute-sized diffusion windows. It can be realized with good performance and reproducibility. Further, according to the present invention, since the U-shaped groove is formed in a total of three cutting steps, nearly vertical sidewalls can be obtained even if the plasma etching directionality in each cutting step is poor. In other words, the directivity and selectivity of plasma etching (S
Although it is known that there is a trade-off relationship between t and 5t02), it is possible to increase the selectivity at the expense of directivity, which allows for deeper etching. Furthermore, according to the present invention, the performance requirements for the plasma etching apparatus are relaxed, so the apparatus can be simple, and as a result, semiconductor devices can be manufactured at low cost and with high yield.

[Brief explanation of the drawing]

FIG. 1 shows an incision cage type SI according to an embodiment of the present invention.
2 is a sectional view showing a conventional notched gate type SIT, FIG. 3 is a sectional view showing a conventional N-channel SIT manufacturing method, and FIG. 5 is a characteristic diagram showing an example of drain current Id-Vd characteristics of a conventional SIT, and FIG. 5 is a cross-sectional view showing an enlarged part of FIG. 3. DESCRIPTION OF SYMBOLS 1... n'''Si substrate, 2... n- layer, 5... oxide film, 59... thermal oxide film, 8... resist film, 9...
...Si. N4 film, 10... n+ region 52... oxide film. Applicant's agent Patent attorney Takehiko Suzue (e) (f) Figure 1-(2) (h) Figure-(3) (a) (f) Figure 2 Figure 2

Claims (2)

[Claims] (1) A first step of digging a first trench in a semiconductor substrate by a first cut and forming an oxide film on the sidewalls of the first trench; Continuing with this, a second step of digging a second trench and forming an oxide film on the side wall of the second trench, and a third incision,
A third step of digging a third groove continuously at the bottom of the second groove, and selectively forming a non-oxidizing film on the side walls of the first to third grooves. A method for manufacturing a semiconductor device, comprising at least a fourth step of forming an oxide film at the bottom of the third trench using an oxidizing film as a mask. (2) Plasma etching in the third step
2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed in steps, first etching at high pressure and then etching at low pressure with good directionality.