JPH04330533A - Central processing unit - Google Patents

Abstract

PURPOSE:To simplify the microprogram in a diagnostic routine and to reduce the capacity of the microprogram by simultaneously and continuously diagnosing plural RAG functions. CONSTITUTION:At the time of RAS function diagnosis, an error branch signal 204 inputted to a microprogram address setting part 13 is kept inactive by the action of an AND gate 17 because of an active test mode signal 202 though an error detection signal 201 of a RAG function part 16 is active. Therefore, the microprogram address setting part 13 indicates the next incremented address without branching to an error processing routine.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit used in information processing systems and the like.

0003

[Background Art] In recent years, in order to improve reliability in central processing units (CPUs), RAS (reliabi...
utility, availability, service
ability) Functions are being enhanced. FIG. 2 shows the configuration of a conventional microprogram central processing unit having such a RAS function section. In the figure, 1 is a control RAM, 2 is an instruction register, 3 is a microprogram address setting section, and 4 is a microprogram type central processing unit. 5 is a decoder, 5 is a test mode register, and 6 is a RAS function section.

The control RAM 1 stores a microprogram, and the microinstruction is loaded into the instruction register 2 using the value indicated by the microprogram address setting section 3 as a read address. The microinstructions loaded into the instruction register 2 are decoded by the decoder 4 and operate each control section.

The RAS function section 6 also performs error detection, and when an error is detected, it activates an error detection signal 101 to the microprogram address setting section 3. When an error is detected by the RAS function section 6, the microprogram address setting section 3 indicates an address to branch to the error handling routine as the next microinstruction address to be executed, and the microinstruction then branches to the error handling routine.

[0006] In the conventional central processing unit having the above configuration,
When diagnosing the RAS function of the RAS function unit 6, the microinstruction first sets a value indicating a test mode in the test mode register 5, so that the RAS function of the RAS function unit 6 can be diagnosed. (In the error detection circuit, an error is intentionally generated.) After that, when a microinstruction that activates the RAS function is executed, the RAS function unit 6 detects that the test mode signal 102 is active and that the RAS
Since the microinstruction signal 103 for operating the function is active, the error detection signal 101 to the microprogram address setting unit 3 is activated.

[0007] The micro program address setting unit 3 is
When the error detection signal 101 becomes active, RA
Upon learning of the error detection by the S function section 6, the address of the next microinstruction to be executed indicates the address at which to branch to the error handling routine. The microinstruction then branches to an error handling routine and diagnoses the RAS function by checking the test mode and the target status flag.

[0008]

However, in the above-mentioned conventional central processing unit, when diagnosing multiple RAS functions, it branches to an error handling routine for each RAS function, resulting in a complicated microprogram and a large capacity. There was a problem with it being too large.

The present invention has been made in response to the above-mentioned conventional circumstances, and has the object of being able to continuously diagnose a plurality of RAS functions at the same time, and simplifying and reducing the size of the microprogram in the diagnostic routine. The aim is to provide a central processing unit that can perform the following tasks.

[Configuration of the invention]

[0011]

[Means for Solving the Problems] That is, the central processing unit of the present invention has a control RAM that stores a microprogram.
a RAS function unit that detects errors; a microprogram address setting unit that controls a microinstruction sequence and branches the microprogram to an error handling routine when an error is detected in the RAS function unit; A test mode register for setting a test mode for testing the RAS functional unit, and means for prohibiting branching to the error handling routine when the test mode register is set to the test mode. It is characterized by

0012

[Operation] In the central processing unit of the present invention having the above configuration, the RAS
During function diagnosis, even if an error is detected in the RAS function section, a branch to the error handling routine is not performed. Therefore, a plurality of RAS functions can be continuously diagnosed simultaneously, and the microprogram in the diagnostic routine can be simplified and its capacity can be reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the central processing unit of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a central processing unit according to an embodiment of the present invention. In the figure, 11 is a control RAM;
12 is an instruction register, 13 is a microprogram address setting section, 14 is a decoder, 15 is a test mode register, 16 is a RAS function section, and 17 is an AND gate.

The control RAM 11 stores a microprogram, and the microprogram address setting section 13
A microinstruction is loaded into the instruction register 12 using the value indicated by as a read address. The microinstructions loaded into the instruction register 12 are decoded by the decoder 14 and operate each control section.

The RAS function section 16 also performs error detection, and when an error is detected, it activates an error detection signal 201 to the microprogram address setting section 13. When an error is detected by the RAS function section 16, the microprogram address setting section 13 indicates an address for branching to the error processing routine as the next microinstruction address to be executed, and the microinstruction then branches to the error processing routine.

Furthermore, when diagnosing the RAS function of the RAS function section 16, the microinstruction first sets a value indicating the test mode in the test mode register 15, so that one RAS function can be diagnosed (intentionally state). It then executes the microinstruction that activates that RAS function. At this time, the target status flag is set in the RAS function unit 16.

The RAS function unit 16 activates the error detection signal 201 when the test mode signal 202 indicating the test mode and the microinstruction signal 203 for operating the RAS function are active. However, since the test mode signal 202 is also active at this time,
The error branch signal 204 input to the microprogram address setting section 13 by the action of the AND gate 17 is
It remains inactive. Therefore, the microprogram address setting unit 13 indicates the next incremented address without branching to the error handling routine.

The next microinstruction sets a value indicating the test mode in the test mode register 15, puts another RAS function in a diagnostic state (intentionally puts it in an error state), and
Execute the microinstruction that activates the AS function. Thereafter, similar operations are repeated for each RAS function. and finally RAS
By checking the status flags in the functional unit 16, all RAS functions are diagnosed.

As described above, in the central processing unit of this embodiment, when diagnosing the RAS function, even if an error is detected in the RAS function section 16, a branch to the error processing routine is not performed. Therefore, a plurality of RAS functions can be continuously diagnosed simultaneously, and the microprogram in the diagnostic routine can be simplified and its capacity can be reduced.

[0021]

[Effects of the Invention] As explained above, according to the central processing unit of the present invention, multiple RAS functions can be continuously diagnosed simultaneously, and the microprogram in the diagnostic routine can be simplified and the capacity can be reduced. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a central processing unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of a conventional central processing unit.

[Explanation of symbols]

11 Control RAM 12 Instruction register 13 Microprogram address setting section 14 Decoder 15 Test mode register 16 RAS function section 17 AND gate

Claims (1)

[Claims] [Claim 1] A control R that stores a microprogram.
an AM, a RAS function unit that detects errors, a microprogram address setting unit that controls a microinstruction sequence and branches the microprogram to an error handling routine when an error is detected in the RAS function unit; A test mode register for setting a test mode for testing the RAS functional unit, and means for prohibiting branching to the error handling routine when the test mode register is set to the test mode. A central processing unit characterized by: