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JPH04326201A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04326201A
JPH04326201A JP3094614A JP9461491A JPH04326201A JP H04326201 A JPH04326201 A JP H04326201A JP 3094614 A JP3094614 A JP 3094614A JP 9461491 A JP9461491 A JP 9461491A JP H04326201 A JPH04326201 A JP H04326201A
Authority
JP
Japan
Prior art keywords
dielectric substrate
transmission line
microstrip transmission
microstrip
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3094614A
Other languages
Japanese (ja)
Inventor
Akira Kumagai
亮 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP3094614A priority Critical patent/JPH04326201A/en
Publication of JPH04326201A publication Critical patent/JPH04326201A/en
Pending legal-status Critical Current

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Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Waveguides (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To reduce the deviation of phases between a microstrip line and a ground plane and to suppress discontinuity by providing microstrip transmission lines to be close to each other and providing a side plane in contact with the ground plane. CONSTITUTION:Dielectric substrates 9 are provided on the input side and output side of a recessed part composed of Cu and provided on the inside bottom of a main body 1 of a package while providing an Au/Ni plating layer on the surface, and a microstrip transmission line 8 and an open stub pattern 10 are provided on the surface of the dielectric substrate 9. Next, a dielectric substrate 2 composed of alumina and a microstrip transmission line 4 are provided through a side wall 2 at the main body 1 of the package, and the inside top is provided in contact with the respective input side and output side end faces of the dielectric substrate 9. In this case, both the ends of the dielectric substrate 3 parallel to the microstrip transmission line 4 is formed while being sandwiched by walls (ground planes) protruded from the side plane of the recessed, part at the main body 1 of the package so as to shield radiation electromagnetic waves.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置に関し、特
に、GaAs電界効果トランジスタ(以下GaAsFE
Tと記す)の入出力整合回路に関する。
[Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to GaAs field effect transistors (hereinafter referred to as GaAsFE).
This invention relates to an input/output matching circuit (denoted as T).

【0002】0002

【従来の技術】従来の半導体装置は、図2(a),(b
)に示すように、パッケージ本体1に設けたGaAsF
ETチップ6の50Ω内部整合回路がチップコンデンサ
7によるキャパシタンス及び金属細線(Au等)のイン
ダクタンスによる集中定数的整合回路と、誘電体基板9
上に設けたマイクロストリップ伝送線路8及びオープン
スタブパターン10による分布定数回路から構成され、
パッケージ本体1の側壁に設けたリード部誘電体基板3
の内側の端部は、パッケージ本体1の側壁と同一面か或
いは、引っ込められて形成されていた。
[Prior Art] A conventional semiconductor device is shown in FIGS. 2(a) and 2(b).
), the GaAsF provided in the package body 1
The 50Ω internal matching circuit of the ET chip 6 is composed of a lumped constant matching circuit using the capacitance of a chip capacitor 7 and the inductance of a thin metal wire (Au, etc.), and a dielectric substrate 9.
It is composed of a distributed constant circuit formed by a microstrip transmission line 8 and an open stub pattern 10 provided on the top,
Lead portion dielectric substrate 3 provided on the side wall of the package body 1
The inner end of the package body 1 was formed flush with the side wall of the package body 1 or recessed.

【0003】0003

【発明が解決しようとする課題】上述した従来の半導体
装置は、パッケージ本体の内部に設けて内部整合回路を
構成する入力側及び出力側の夫々の第1の誘電体基板上
に設けられたマイクロストリップ伝送線路により、伝搬
する電磁波は、パッケージ本体の底面を接地面として、
誘電体と、自由空間に跨って伝搬している。又、パッケ
ージ本体の側壁を貫通する第2の誘電体基板上に設けら
れたマイクロストリップ伝送線路も同様なモードで伝搬
する。
[Problems to be Solved by the Invention] The above-mentioned conventional semiconductor device has a microelectronic semiconductor device provided on first dielectric substrates on each of the input side and output side, which are provided inside the package body and constitute an internal matching circuit. The electromagnetic waves propagating through the strip transmission line are grounded using the bottom of the package body.
It propagates across the dielectric and free space. Furthermore, the microstrip transmission line provided on the second dielectric substrate passing through the side wall of the package body also propagates in a similar mode.

【0004】これらの第1及び第2の誘電体基板の相互
間に隙間があるとマイクロストリップ伝送線路相互間も
必然的に離れ、マイクロストリップ伝送線路と接地面と
に、位相のずれが生じてしまう。従って、特に周波数が
高くなると、波長が短くなる分、位相のずれが顕著にな
り、不連続が発生し、GaAsFETの超高周波帯に於
ける整合状態に影響を与え、特性低下をきたすという問
題点があった。
[0004] If there is a gap between the first and second dielectric substrates, the microstrip transmission lines will inevitably be separated from each other, causing a phase shift between the microstrip transmission line and the ground plane. Put it away. Therefore, especially as the frequency becomes higher, the phase shift becomes more noticeable as the wavelength becomes shorter, causing discontinuity, which affects the matching state of GaAsFETs in the ultra-high frequency band, resulting in characteristic deterioration. was there.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
パッケージ本体の内側底面に設けた凹部内に設けてマイ
クロストリップ伝送線路及びオープンスタブパターンに
よる内部整合回路を有する第1の誘電体基板と、前記パ
ッケージ本体の側壁を貫通するマイクロストリップ伝送
線路を有し且つ内側先端を前記第1の誘電体基板上のマ
イクロストリップ伝送線路と接するように前記第1の誘
電体基板の端面に接して設けた第2の誘電体基板と、前
記第2の誘電体基板のマイクロストリップ伝送線路と平
行な両側面に接して設けた接地面とを備えている。
[Means for Solving the Problems] A semiconductor device of the present invention includes:
A first dielectric substrate having a microstrip transmission line and an internal matching circuit formed by an open stub pattern provided in a recess provided on the inner bottom surface of the package body, and a microstrip transmission line penetrating the side wall of the package body. and a second dielectric substrate provided in contact with an end surface of the first dielectric substrate so that its inner tip is in contact with the microstrip transmission line on the first dielectric substrate; and the second dielectric substrate. It has a microstrip transmission line and ground planes provided in contact with both parallel sides.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0007】図1(a),(b)は本発明の一実施例を
示す平面図及び部分切欠斜視図である。
FIGS. 1(a) and 1(b) are a plan view and a partially cutaway perspective view showing an embodiment of the present invention.

【0008】図1(a),(b)に示すように、Cuか
らなり表面にAu/Niめっき層を設けたパッケージ本
体1の内側底面に設けた凹部内の入力側と出力側に誘電
体基板9を設け、誘電体基板9の表面にマイクロストリ
ップ伝送線路8とオープンスタブパターン10とを設け
る。次に、パッケージ本体1の側壁2を貫通してアルミ
ナからなる誘電体基板2及びマイクロストリップ伝送線
路4を設け、その内側先端を誘電体基板9の入力側及び
出力側の夫々の端面に接して設ける。ここで、マイクロ
ストリップ伝送線路4に平行な誘電体基板3の両端はパ
ッケージ本体1の凹部側面より突出した壁(接地面)に
挾まれて形成され放射電磁波を遮断することができる。 次に、マイクロストリップ伝送線路4の入力端及び出力
端の夫々にリード11を接続する。次に、パッケージ本
体1の内側中央にGaAsFETチップ6をマウントし
、GaAsFETチップ6の入力側と出力側の夫々にチ
ップコンデンサ7をマウントし、GaAsFETチップ
6とチップコンデンサ7との間、チップコンデンサ7と
マイクロストリップ伝送線路8との間、マイクロストリ
ップ伝送線路8とマイクロストリップ伝送線路4との間
の夫々を金属細線で接続し、半導体装置を構成する。
As shown in FIGS. 1(a) and 1(b), a dielectric material is placed on the input side and the output side in a recess provided on the inner bottom surface of a package body 1 made of Cu and having an Au/Ni plating layer on the surface. A substrate 9 is provided, and a microstrip transmission line 8 and an open stub pattern 10 are provided on the surface of the dielectric substrate 9. Next, a dielectric substrate 2 made of alumina and a microstrip transmission line 4 are provided through the side wall 2 of the package body 1, and their inner tips are in contact with the input side and output side end surfaces of the dielectric substrate 9, respectively. establish. Here, both ends of the dielectric substrate 3 parallel to the microstrip transmission line 4 are sandwiched between walls (ground planes) protruding from the side surfaces of the recessed portion of the package body 1, so that radiated electromagnetic waves can be blocked. Next, leads 11 are connected to each of the input end and output end of the microstrip transmission line 4. Next, a GaAsFET chip 6 is mounted at the center inside the package body 1, a chip capacitor 7 is mounted on each of the input side and output side of the GaAsFET chip 6, and the chip capacitor 7 is mounted between the GaAsFET chip 6 and the chip capacitor 7. and the microstrip transmission line 8, and between the microstrip transmission line 8 and the microstrip transmission line 4 are connected by thin metal wires to form a semiconductor device.

【0009】[0009]

【発明の効果】以上説明したように本発明は、パッケー
ジ本体の側壁を貫通して設けたマイクロストリップ伝送
線路を有する誘電体基板の内側の端面を、パッケージ本
体の底面に設けた内部整合用マイクロストリップ伝送線
路を有する誘電体基板の入力端及び出力端の夫々に接し
て設け、且つ側面を接地面に接して設けることにより、
マイクロストリップ線路と接地面との位相のずれを低減
して不連続性を抑制することができるという効果を有す
る。
Effects of the Invention As described above, the present invention provides an internal matching microstrip that is provided on the bottom surface of the package body by connecting the inner end surface of the dielectric substrate having the microstrip transmission line that penetrates the side wall of the package body. By providing it in contact with each of the input end and output end of the dielectric substrate having the strip transmission line, and by providing the side surface in contact with the ground plane,
This has the effect of reducing the phase shift between the microstrip line and the ground plane and suppressing discontinuity.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例を示す平面図及び部分切欠斜
視図。
FIG. 1 is a plan view and a partially cutaway perspective view showing an embodiment of the present invention.

【図2】従来の半導体装置の一例を示す平面図及び部分
切欠斜視図。
FIG. 2 is a plan view and a partially cutaway perspective view showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1    パッケージ本体 2    側壁 3,9    誘電体基板 4,8    マイクロストリップ伝送線路6    
GaAsFETチップ 7    チップコンデンサ 10    オープンスタブパターン 11    リード
1 Package body 2 Side walls 3, 9 Dielectric substrate 4, 8 Microstrip transmission line 6
GaAsFET chip 7 Chip capacitor 10 Open stub pattern 11 Lead

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  パッケージ本体の内側底面に設けた凹
部内に設けてマイクロストリップ伝送線路及びオープン
スタブパターンによる内部整合回路を有する第1の誘電
体基板と、前記パッケージ本体の側壁を貫通するマイク
ロストリップ伝送線路を有し且つ内側先端を前記第1の
誘電体基板上のマイクロストリップ伝送線路と接するよ
うに前記第1の誘電体基板の端面に接して設けた第2の
誘電体基板と、前記第2の誘電体基板のマイクロストリ
ップ伝送線路と平行な両側面に接して設けた接地面とを
備えたことを特徴とする半導体装置。
1. A first dielectric substrate provided in a recess provided on the inner bottom surface of a package body and having an internal matching circuit formed by a microstrip transmission line and an open stub pattern, and a microstrip that passes through a side wall of the package body. a second dielectric substrate having a transmission line and provided in contact with an end surface of the first dielectric substrate so that its inner tip is in contact with the microstrip transmission line on the first dielectric substrate; 1. A semiconductor device comprising: a microstrip transmission line of a second dielectric substrate; and ground planes provided in contact with both parallel sides of the dielectric substrate.
JP3094614A 1991-04-25 1991-04-25 Semiconductor device Pending JPH04326201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3094614A JPH04326201A (en) 1991-04-25 1991-04-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3094614A JPH04326201A (en) 1991-04-25 1991-04-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04326201A true JPH04326201A (en) 1992-11-16

Family

ID=14115128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3094614A Pending JPH04326201A (en) 1991-04-25 1991-04-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04326201A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7560695B2 (en) * 2006-04-11 2009-07-14 Canon Kabushiki Kaisha Detecting apparatus, and detecting method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58190046A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device
JPH0319403A (en) * 1989-06-15 1991-01-28 Matsushita Electron Corp Microwave integrated circuit element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58190046A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device
JPH0319403A (en) * 1989-06-15 1991-01-28 Matsushita Electron Corp Microwave integrated circuit element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7560695B2 (en) * 2006-04-11 2009-07-14 Canon Kabushiki Kaisha Detecting apparatus, and detecting method
US7745791B2 (en) 2006-04-11 2010-06-29 Canon Kabushiki Kaisha Detecting apparatus, and detecting method

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Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19971007