JPH04308957A - computer system - Google Patents

Abstract

PURPOSE:To transfer both bus lines by the same transferring procedure, to easily attain the high speed of a processing speed at a CPU side, to use a low speed equipment at a low speed bus side, and to use an element whose power consumption is reduced, and whose heat is reduced, at a low cost for the low speed equipment by inserting a bus speed converter into a synchronous bus line. CONSTITUTION:This bus speed converter is inserted into a synchronous bus, and the synchronous bus is divided into a high speed bus at a CPU side and a low speed bus at an I/O equipment side. At the time of writing data from the high speed bus side in the low speed bus side, a selector 14 for a high speed bus address latch, and a selector 16 for a high speed bus write data latch, are switched to the high speed bus side, and an address and data are respectively latched by a latch circuit 13 for the high speed bus address, and a latch circuit 15 for the high speed bus write data, when a write signal is inputted. A command signal I/F device 21 frequency-divides a clock from the high speed bus side, and transmits the write signal to the low speed bus side synchronously with it, so that the data can be transmitted through an outputting buffer 17 for the low speed bus to the low speed bus side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system equipped with a device for converting data transfer rates without changing input/output procedures on synchronous bus lines.

0002

[Prior Art] CPU constituting a computer system
, memories, I/O devices, etc., there have conventionally been asynchronous and synchronous types of bus lines.

0003

[Problems to be Solved by the Invention] The asynchronous bus generates a signal indicating completion every time data transfer is completed. Therefore, if the same clock is not used at the transfer source and the transfer destination, there is a possibility that there will be a one-clock difference in clock capture each time, and the transfer speed will not be constant. Furthermore, when the same clock is used, it is difficult to operate the transfer source and transfer destination at optimal speeds. On the other hand, synchronous buses have the disadvantage that they are difficult to use in systems that require long distances because in order to increase the data transfer rate, the speed of the entire synchronous bus must be increased. Additionally, there is a problem in that the power consumption and price of the elements used for transfer increase. In order to cope with the increase in transfer speed, the processing speeds of all elements connected to the same bus must be able to cope with the increase in speed. The purpose of the present invention is to solve each of the above-mentioned drawbacks, and by inserting a bus speed conversion device into the synchronous bus line, data can be transferred using the same transfer procedure on both bus lines, thereby increasing the processing speed on the CPU side. The object of the present invention is to provide a computer system that can be easily configured, and can use low-speed devices on the low-speed bus side, and can use inexpensive elements with low power consumption and low heat generation.

0004

[Means for Solving the Problems] In order to achieve the above object, a computer system according to the present invention installs a bus speed conversion device on a synchronous bus line that connects devices with different processing speeds, and the bus speed conversion device , a high-speed bus side address and data selector for selecting an address signal line and a data signal line of either the high-speed side bus or the low-speed side bus, and address and data signal lines from the address signal line selected by the selector. an address and data latch circuit that temporarily stores data from the high-speed bus, and a low-speed bus output buffer that outputs the data stored in the high-speed bus side data latch circuit to the low-speed bus;
A low-speed bus side address and data selector for selecting the address signal line and data signal line of either the high-speed side bus or the low-speed side bus, and the data stored in the low-speed bus side data latch circuit are connected to the high-speed side bus. an output buffer for the high-speed bus, and controls the selector, latch circuit, and output buffer based on a control signal from the high-speed bus side, and controls the latch circuit according to the frequency-divided output of the clock supplied from the high-speed bus side. It is comprised of a control device that performs data speed conversion between the high-speed bus side and the low-speed bus side by outputting latched data to the circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in more detail below with reference to the drawings and the like. FIG. 1 is a diagram showing an example of a connection of a bus speed conversion device for a computer system according to the present invention. A CPU 1 and a memory 2 are connected to a high-speed synchronous bus (hereinafter referred to as "high-speed bus") 7. On the other hand, I/O devices 4 and 5 and a low-speed memory 6 are connected to a low-speed synchronous bus (hereinafter referred to as "low-speed bus") 8. The bus speed conversion device 3 is connected between the high-speed bus 7 and the low-speed bus 8, and is, for example, a CPU
When writing data from 1 to low-speed memory 6,
After the data is transferred according to a predetermined procedure and the data speed is adjusted by the device 3, the data is stored in the low-speed memory 6 using the same transfer procedure. A similar procedure is used when data is transferred from the low-speed bus 8 side to the high-speed bus 7 side. The speed of the low-speed bus is set to a speed obtained by dividing the clock of the high-speed bus.

FIG. 2 is a diagram showing another example of connection of the bus speed conversion device. Portions with the same reference numerals as in FIG. 1 have the same functions as those portions in FIG. The configuration in which the CPU 1 and memory 2 are connected to the high-speed bus 7 is the same as in the above example. Further, the I/O device 4 is connected to a low-speed bus 8. The high-speed to medium-speed bus speed conversion device 10 is connected between the high-speed bus 7 and the medium-speed bus 9, and the medium-speed bus 9 is connected to a medium-speed I/O device 12. The medium-speed to low-speed bus speed conversion device 11 is connected between the medium-speed bus 9 and the low-speed bus 8. By using a bus speed converter like this, you can adjust the speed between devices with three different speeds and connect to a bus with a speed that matches the processing of each device, allowing you to take advantage of the features of each device. . The medium speed bus 9 and the low speed bus 8 are set to a speed obtained by dividing the clock of the high speed bus 7.

FIG. 3 is a circuit block diagram showing an embodiment of a bus speed conversion device for a computer system according to the present invention. In the figure, the left side is the high-speed bus side, and the right side is the low-speed bus side. The high-speed bus and low-speed bus address signal lines are respectively connected to two inputs of a high-speed bus address latch selector 14. The output of the latch selector 14 is connected to the input of the high-speed bus address latch circuit 13, and the output of the latch circuit 13 is connected to the low-speed bus address signal line. Further, the data signal line of the high-speed bus and the output of the high-speed bus write data latch circuit 15 are respectively connected to two inputs of the high-speed bus data latch selector 16. The output of the latch selector 16 is connected to the input of the high-speed bus address latch circuit 15.
The output of is connected to the input of the low-speed bus output buffer 17. The output of the low-speed bus output buffer 17 is connected to the data signal line of the low-speed bus.

The low-speed bus data signal line and the output of the low-speed bus read data latch circuit 18 are respectively connected to two inputs of a low-speed bus read data latch selector 19. The output of the latch selector 19 is connected to the input of the low-speed bus read data latch circuit 18, and the output of the latch circuit 18 is connected to the input of the high-speed bus output buffer 20. The output of the high-speed bus output buffer 20 is connected to the data signal line of the high-speed bus. The command signal I/F device (control device) 21 is configured to receive read signals, write signals, and clock signals from the high-speed bus side, and output read signals, write signals, and clock signals to the low-speed bus.

First, the case where data is written from the high-speed bus to the low-speed bus side will be explained with reference to FIG. 4(a). A write signal is output from the high-speed bus in synchronization with the clock on the high-speed bus side. This write signal switches the latch selector 16 to the high-speed bus side, and the data on the high-speed bus is latched into the data latch circuit 15. Latching is done at the timing of the high-speed bus clock. At the same time, the command signal I/F device 21 outputs a selector switching signal to switch the latch selector 14 to the high-speed bus side, and the address signal is latched by the address latch circuit 13. The command signal I/F device 21 sends out a ready signal to the high speed side at the next clock. Then, a write signal is output to the low-speed bus side in synchronization with a low-speed clock created by frequency-dividing the clock from the high-speed bus side. This write signal is sent to the output buffer 17, and the data latched in the data latch circuit 15 is read out and sent to the low-speed bus. The command signal I/F device 21 receives a ready signal from the low-speed bus side.

Next, the case where a low-speed bus is read from the high-speed bus side will be explained with reference to FIG. 4(b). A read signal on the high-speed bus side is input to the command signal I/F device 21 in synchronization with the clock on the high-speed bus side. The command signal I/F device 21 outputs a switching signal to switch the high-speed bus address latch selector 14, and latches the address sent from the high-speed bus into the high-speed bus address latch circuit 13. In addition, a read signal for the low-speed bus side is generated in synchronization with a low-speed clock created by dividing the high-speed bus clock, and the low-speed bus read data latch selector 19 is switched to the low-speed bus side, and a ready signal from the low-speed bus side is generated. wait. The command signal I/F device 21 stops generating the read signal when the ready signal from the low-speed bus side is returned. When data is sent from the low-speed bus side, the data is latched by the low-speed bus read data latch circuit 18. The latched data is output to the high-speed bus by the high-speed bus output buffer 20 activated by a read signal on the high-speed bus side. At the same time, the command signal I/F device 21 outputs a ready signal to the high-speed bus side.

[0011]

[Effects of the Invention] As explained above, since the computer system according to the present invention has a bus speed conversion device installed in the synchronous bus line that connects devices with different processing speeds, it has the following various advantages. have First, by inserting a bus speed converter and partitioning the synchronous bus line into a low-speed bus and a high-speed bus, only the CPU side can be easily increased in speed. Additionally, devices that only operate at low frequencies can be connected without slowing down the entire system. Since the high-speed bus is located only on one side of the bus speed converter, wiring design becomes easier and radiation of high-frequency noise is reduced. Devices on the low-speed bus operate at low frequencies, can achieve low power consumption and low heat generation, and can use inexpensive elements. Furthermore, even if the bus speed converter is removed, the computer system can still operate at a lower overall speed. Since it is a synchronous bus, wasteful data transfer can be eliminated by using a transfer procedure that determines the transfer direction of the bus speed converter before the transfer signal becomes valid.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a connection example of a bus speed conversion device for a computer system according to the present invention.

FIG. 2 is a diagram showing another example of connection of a bus speed conversion device.

FIG. 3 is a circuit block diagram showing an embodiment of a bus speed conversion device for a computer system according to the present invention.

FIG. 4 is a timing chart for explaining the speed conversion operation of the bus speed conversion device.

[Explanation of symbols]

1...Central processing unit (CPU) 2...Memory 3...Bus speed converter 4, 5...I/O device 6...Low speed memory 7...High speed bus 8...Low speed bus 9...Medium speed bus 10...High speed-medium speed bus speed Conversion device 11...medium-low speed bus speed conversion device 13...high-speed bus address latch circuit 14...high-speed bus address latch selector 15...high-speed bus write data latch circuit 16...high-speed bus write data latch selector 17, 20... Output buffer 18...Latch circuit for low-speed bus read data 19...Selector for low-speed bus read data latch 21...Command signal I
/F device

Claims (1)

[Claims] 1. A bus speed conversion device is installed on a synchronous bus line that connects devices with different processing speeds, and the bus speed conversion device converts address signal lines and data signals of either a high-speed bus or a low-speed bus. a high-speed bus side address and data selector for selecting a line; an address and data latch circuit for temporarily storing the address from the address signal line selected by the selector and the data from the data signal line; A low-speed bus output buffer that outputs the data stored in the high-speed bus data latch circuit to the low-speed bus, and a low-speed bus that selects the address signal line and data signal line of either the high-speed bus or the low-speed bus. a high-speed bus output buffer that outputs data stored in the low-speed bus side data latch circuit to the high-speed bus; and a selector based on a control signal from the high-speed bus side. The data speed between the high-speed bus side and the low-speed bus side is increased by controlling the latch circuit and the output buffer and outputting the data latched to the latch circuit according to the divided output of the clock supplied from the high-speed bus side. A computer system comprising a control device that performs conversion.