JPH0430454A - Semiconductor device lead frame - Google Patents
Semiconductor device lead frameInfo
- Publication number
- JPH0430454A JPH0430454A JP13672490A JP13672490A JPH0430454A JP H0430454 A JPH0430454 A JP H0430454A JP 13672490 A JP13672490 A JP 13672490A JP 13672490 A JP13672490 A JP 13672490A JP H0430454 A JPH0430454 A JP H0430454A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- lead frame
- semiconductor device
- resin
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000011347 resin Substances 0.000 abstract description 17
- 229920005989 resin Polymers 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000035939 shock Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000003754 machining Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、半導体装置用リードフレームの構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a lead frame for a semiconductor device.
［従来の技術］
従来の半導体装置（以下工Ｃと呼ぶ）用リードフレーム
は、半導体装置取付部（以下グイバットと呼ぶ）が第２
図（α）のようにリードフレーム表面に対して平行であ
りかつ平担であった、そしてダイパッドは通常モールド
封止時における揚力を減退させるため第２図（ａ）のご
とくグイバットをあらかじめプレスにより、リードフレ
ーム表面より下げた状態に加工（以下ダイパッドダウン
と呼ぶ）しである。またその裏面は第２図（α）の様に
均一な物や、第２図（ｂ）の様に穴開加工がなされてい
るもの、第２図（ｃ）の様にデインプル加工、又はスリ
ット加工がなされているものが知られていする。また、
第２図Ｃｄ）の様にダイパッド裏面部分にガラスマット
や補強材を設けるものなどが知られている。[Prior art] In a conventional lead frame for a semiconductor device (hereinafter referred to as process C), the semiconductor device mounting part (hereinafter referred to as guibat) is
As shown in Figure 2(a), the die pad was parallel to and flat with the lead frame surface, and the die pad was usually pressed with a guibat in advance as shown in Figure 2(a) to reduce the lift force during mold sealing. The die pad is processed to be lower than the surface of the lead frame (hereinafter referred to as die pad down). The back side may be uniform as shown in Figure 2 (α), with holes as shown in Figure 2 (b), or dimpled or slit as shown in Figure 2 (c). The processed material is known. Also,
As shown in FIG. 2Cd), a device in which a glass mat or reinforcing material is provided on the rear surface of the die pad is known.
第４図は従来使われている半導体装置用リードフレーム
（以下リードフレームと呼ぶ）の詳細図である。鉄材又
は鋼材で出来たリードフレーム母体をエツチング又はプ
レス加工によりグイバット２、ダムバー５．タブ吊りリ
ード４．インナーリーに’ Ｅ 丁＾々−ＩＩ −Ｌ
” ｔ ｆ−Ｌ？ ｂｒ Ｉ→←〒ネプまたプレス加
工フレームでは、第４図（ｂ）の様にフレーム加工時に
ダイパッドダウンを行うこともある。FIG. 4 is a detailed diagram of a conventionally used lead frame for semiconductor devices (hereinafter referred to as lead frame). By etching or pressing a lead frame base made of iron or steel, the lead frame 2, dam bar 5. Tab hanging lead 4. Innerly ni' E Ding^^-II-L
" t f-L?br I→←〒〒〒〒For press-formed frames, die pad down is sometimes performed during frame processing as shown in Fig. 4(b).
第５図はフレームのダイパッドダウン加工装置の概念図
である。ダイパッドダウン加工は、図の通り上型７，８
を開放し、下型９の凹部にフレームをセクトし、ストリ
ッパー８により金型を押さえ、パンチ７でプレスして加
工を行う。FIG. 5 is a conceptual diagram of a frame die pad down processing apparatus. Die pad down processing is performed using upper molds 7 and 8 as shown in the diagram.
is opened, the frame is sectioned into the recessed part of the lower mold 9, the mold is held down by the stripper 8, and the mold is pressed by the punch 7 to perform processing.
［発明が解決しようとする課題］
第２図（ａ）の様なリードフレームでは第７図（α）の
様に、平担かつ平行なダイパッドな為、ダイパッド及び
ＩＣへ極度の応力が集中した。また、ダイパッド下部が
平担なため樹脂とリードフレームの熱膨張係数の違いか
ら生じる横への応力が熱衝撃時における、樹脂とリード
フレームとの密着性不良や、モールド樹脂へのクラック
の発生の原因となっていた。また、第２図Ｃｂ）、ＣＣ
）、（ｄ）の様なダイパッド裏面部分への穴開加工や、
デインプル加工、スリット加工を施した物、及びグイパ
ント部を保護した物については密着性の向上は見られる
ものの、樹脂モールド加工時にモールド樹脂の流入によ
る揚力のためにグイバットが浮いたり、それらの加工を
施す際の生産コストの増加などがあり、低コストを目指
す大量生産などには不向きであった。[Problem to be solved by the invention] In the lead frame as shown in Fig. 2(a), the die pad is flat and parallel as shown in Fig. 7(α), so extreme stress is concentrated on the die pad and IC. . In addition, since the lower part of the die pad is flat, lateral stress caused by the difference in thermal expansion coefficient between the resin and the lead frame can cause poor adhesion between the resin and the lead frame and cracks in the mold resin during thermal shock. It was the cause. In addition, Fig. 2 Cb), CC
), (d), drilling holes on the back side of the die pad,
Although improvements in adhesion can be seen for items with dimples, slits, and items with protected Guipant parts, the Guibutt may float due to the lifting force caused by the inflow of mold resin during resin mold processing, and these treatments may cause problems. This increases the production cost when applying the method, making it unsuitable for mass production aiming for low costs.
従ってごれらの方法ではこれから益々大型化、薄型化、
低コスト化していく工Ｃの生産方法としては安定した方
法とは言えない。Therefore, with our method, we will continue to use larger, thinner,
It cannot be said that this is a stable method for producing Process C, which is becoming cheaper.
口課題を解決するための手段］
本発明の半導体装置用リードフレームは半導体装置取付
部の外肩部を湾曲させる事を特徴とする［実施例コ
第１図は本発明の詳細な説明するための線図で、以下第
５図、第６図を参照して本発明を説明する。[Means for Solving the Problems] The lead frame for a semiconductor device of the present invention is characterized in that the outer shoulder portion of the semiconductor device mounting portion is curved. The present invention will be described below with reference to FIGS. 5 and 6.
第１図（α）は、本発明の実施例を示すリードフレーム
の平面図でありグイバット部２に半導体素子が搭載され
、その半導体素子はインナーリード部５と導電性細線で
結線される。インナーリード部５はアウターリード部乙
に接続され、アウターリード部６は外枠１と連結されて
いる。第４図（ｈ）は本発明の実施例を示すリードフレ
ームの断面図であり半導体素子はダイパッド部２に搭載
されており、ダイパッド部２は外周部１７部で湾曲され
ている。第５図（α）は本発明で使用するダイパッドダ
ウン加工用金型の概略図であり、（ｂ）はそれにより製
作されたリードフレームの略図である。この外周部の湾
曲加工は第５図（α）にあるような金型を用いてフレー
ムのプレス加工時、又はダイパッドダウン加工時に行わ
れる。第５図（α）に於て１Ｄは下型、１１はパンチ、
１２はストリッパーである。加工方法は従来の方法とほ
ぼ同様に行なうことができ、まず上型を開放して下型に
フレームを配置する、次にストリッパー１２でフレーム
外周部を押さえ、パンチ１１で７＋＋７７ ＋ＩＩ−Ｉ
Ｔ−ｆｌ Ｉｘ”Ａ ／＜ 、、 ｋ Ｊ−ｆｙ ｙ
＋ （Ｍ ＜ ｆｉ２１ （，６）＃（１３））は通常
使用している量とほぼ同量で行う（例えば０．２５ ｍ
ｍ ）ダイパッド湾曲加工高さ（第５図（１，（１４）
）は前記グイバットダウン量よりも低い値（例えば０．
２ ｖａｎ ）で加工を行う。又、前記の様な加工をよ
り円滑に打つためリードフレーム製作時に第５図（ｂ）
の、１５．１６．１７部にあらかじめノツチをつけてお
けばより精密な加工が出来る。FIG. 1(α) is a plan view of a lead frame showing an embodiment of the present invention, in which a semiconductor element is mounted on the lead part 2, and the semiconductor element is connected to the inner lead part 5 with a conductive thin wire. The inner lead part 5 is connected to the outer lead part B, and the outer lead part 6 is connected to the outer frame 1. FIG. 4(h) is a sectional view of a lead frame showing an embodiment of the present invention. A semiconductor element is mounted on a die pad portion 2, and the die pad portion 2 is curved at an outer peripheral portion 17. FIG. 5(α) is a schematic diagram of a mold for die pad down processing used in the present invention, and FIG. 5(b) is a schematic diagram of a lead frame manufactured using the mold. This curving of the outer periphery is performed using a mold as shown in FIG. 5(α) during press processing of the frame or during die pad down processing. In Fig. 5 (α), 1D is the lower mold, 11 is the punch,
12 is a stripper. The processing method can be carried out almost in the same way as the conventional method.First, open the upper mold and place the frame on the lower mold.Next, press the outer periphery of the frame with the stripper 12, and use the punch 11 to remove the 7++77 +II-I.
T-fl Ix”A /< ,, k J-fy y
+ (M < fi21 (,6) #(13)) is performed with approximately the same amount as normally used (for example, 0.25 m
m) Die pad curved height (Fig. 5 (1, (14)
) is a value lower than the amount of guibatdown (for example, 0.
2 van). In addition, in order to perform the above-mentioned machining more smoothly, when manufacturing the lead frame, as shown in Figure 5 (b)
If you make notches in advance on parts 15, 16, and 17, you can perform more precise machining.
第６図は外周部の湾曲加工の拡大図である。湾曲加工角
度１８は５〜９０°で調整する、またタブ吊りリードと
ダイパッドの湾曲部分との挟角１９は５〜９０°の範囲
で調整すると非常に効果的である。FIG. 6 is an enlarged view of the curving process of the outer peripheral portion. It is very effective to adjust the bending angle 18 in the range of 5 to 90 degrees, and to adjust the included angle 19 between the tab suspension lead and the curved portion of the die pad in the range of 5 to 90 degrees.
［発明の効果］
以上詳記した通り、本発明はプレス加工時、又は、ダイ
パッドダウン加工時に付随した工程を設けることのみで
、グイバットと樹脂の密着性を非常に良くすることが出
来る。そしてこの加工を施７ｆ−７レー人ｆ）ス制旦は
筐７ ａ ／ ／ｌ ）ｒ京六トうに横方向及びダイパ
ッド下方向からの、樹脂とリードフレームとの熱膨張係
数差による応力を緩和することが出来る。また、樹脂と
の密着力が高いため通常のリードフレームを使用した場
合に比べ熱衝撃におけるモールド樹脂の耐クラツク特性
が非常に良（なる。[Effects of the Invention] As described in detail above, the present invention can greatly improve the adhesion between Guibat and the resin simply by providing an accompanying step during press processing or die pad down processing. This processing is applied to the housing 7a//l)r to reduce stress due to the difference in thermal expansion coefficient between the resin and the lead frame from the lateral direction and from below the die pad. It can be alleviated. In addition, since the adhesive strength with the resin is high, the crack resistance of the mold resin against thermal shock is much better than when a normal lead frame is used.
また、本発明の半導体装置用リードフレームでは樹脂モ
ールド加工時に於て、第１図（α）の様なダイパッドの
加工により樹脂の流れが第１図（ｈ）の様になめらかに
誘導されダイパッド部の浮きも生じず成形性の良いモー
ルド樹脂封止加工ができる。また、ダイパッド加工はダ
イパッドダウン加工の際に外周部を湾曲させるだけなの
でＭＱｉかつ低コストである。In addition, in the lead frame for a semiconductor device of the present invention, during resin mold processing, the flow of resin is smoothly guided as shown in FIG. 1 (h) by processing the die pad as shown in FIG. 1 (α), and the die pad portion It is possible to perform a mold resin sealing process with good moldability without causing any lifting. In addition, die pad processing is achieved by simply curving the outer periphery during die pad down processing, resulting in MQi and low cost.
第１図（α）、（ｂ）は、本発明を説明するためのリー
ドフレームの平面図及び、断面図。第２図（α）〜Ｃｄ
）は、従来の半導体装置の構造の断面図。第５図は、従
来使用してきたダイノ＜ットダウン加工用金型の概念図
。第４図（α）、（ｂ）は、従来使用してきたリードフ
レームを説明するための平面図、及び断面図。第５図（
αン （ｈ）は本発明で使用するダイパッドダウン用プ
レス金型の概念図。第６図は本発明の半導体装置取付部
の外周部の湾曲加工部分の詳細図。第７図（α）は従来
技術のリードフレームを用いた場合のモールド時におけ
る応力の発生状況を説明するための概念図。第７図（ｂ
）は本発明のリードフレームを用いた場合のモールド時
における応力の発生状況を説明するための概念図。
１・・・−・−・外 枠
２−・−・−ダイパッド
３−一・−・ダムバー
４・・・・・・・・・タブ吊りリード
５・・・−・−・インナーリード
６・−一・−・アウターリード
７−−−−−・パンチ
８・・・−・・・・ストリッパー
９−・−・・・・−下 型
１０−− ・−−−−−下 型
１１ ・・・・・・・・・パンチ
１２・・・・・・・・・ストリッパー
１５−・・・・・・・・ダイパッドダウン量１４・・・
・・・・・・湾曲部高さ
１５−・・・・・・・・湾曲部〜インナーリード折り曲
げ部１６−・・・・・・−・インナーリード折り曲げ部
１７・・・・・・・・・湾曲部折り曲げ部１８・・・・
・・・・・湾曲部角度
１９−−・・・・・・・インナーリード角度以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部（他１名）樹脂の流れ一一
一一−−→
■
図（ｂ）
？
図（ａ）
図（ｂ）
図（○）
図（ｄ）
図
第５図（８）
第 ６ 図
首７図（ａ）
用
図
（ｂ）FIGS. 1(α) and 1(b) are a plan view and a sectional view of a lead frame for explaining the present invention. Figure 2 (α) ~ Cd
) is a cross-sectional view of the structure of a conventional semiconductor device. Figure 5 is a conceptual diagram of a die for conventional cut-down machining using a dyno. FIGS. 4(α) and 4(b) are a plan view and a sectional view for explaining a conventionally used lead frame. Figure 5 (
α (h) is a conceptual diagram of a die pad down press mold used in the present invention. FIG. 6 is a detailed view of the curved portion of the outer periphery of the semiconductor device mounting portion of the present invention. FIG. 7(α) is a conceptual diagram for explaining the state of stress generation during molding when a conventional lead frame is used. Figure 7 (b
) is a conceptual diagram for explaining the stress generation situation during molding when the lead frame of the present invention is used. 1...---Outer frame 2--Die pad 3--Dam bar 4...Tab suspension lead 5--Inner lead 6-- - Outer lead 7 - Punch 8 - Stripper 9 - Lower mold 10 - Lower mold 11 ...Punch 12 ... Stripper 15 - ... Die pad down amount 14 ...
......Curved part height 15-...Curved part to inner lead bent part 16-...Inner lead bent part 17...・Curved part bending part 18...
・・・・・・Curved part angle 19－・・・・・・Inner lead angle or more Applicant: Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) Resin flow 1111--- → ■Figure (b)? Figure (a) Figure (b) Figure (○) Figure (d) Figure 5 (8) Figure 6 Figure 7 (a) Figure (b)
Claims (1)
吊りリード、前記取付部周囲に配された複数リード、及
びそれらを保持する枠部を有する半導体装置用リードフ
レームに於て、 前記半導体装置取付部の外周部を湾曲させる事を特徴と
する半導体装置用リードフレーム。[Scope of Claims] A lead frame for a semiconductor device including at least a semiconductor device mounting portion, a hanging lead that holds the mounting portion, a plurality of leads arranged around the mounting portion, and a frame portion that holds them, A lead frame for a semiconductor device, characterized in that an outer peripheral portion of the semiconductor device mounting portion is curved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13672490A JPH0430454A (en) | 1990-05-25 | 1990-05-25 | Semiconductor device lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13672490A JPH0430454A (en) | 1990-05-25 | 1990-05-25 | Semiconductor device lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430454A true JPH0430454A (en) | 1992-02-03 |
Family
ID=15182016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13672490A Pending JPH0430454A (en) | 1990-05-25 | 1990-05-25 | Semiconductor device lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430454A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110887A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Island exposure type semiconductor device |
-
1990
- 1990-05-25 JP JP13672490A patent/JPH0430454A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110887A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Island exposure type semiconductor device |
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