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JPH04299848A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH04299848A
JPH04299848A JP6482991A JP6482991A JPH04299848A JP H04299848 A JPH04299848 A JP H04299848A JP 6482991 A JP6482991 A JP 6482991A JP 6482991 A JP6482991 A JP 6482991A JP H04299848 A JPH04299848 A JP H04299848A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
lead frame
die stage
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6482991A
Other languages
Japanese (ja)
Inventor
Takuya Kachi
加知 卓哉
Kazuto Tsuji
和人 辻
Yoshiyuki Yoneda
義之 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP6482991A priority Critical patent/JPH04299848A/en
Priority to EP91310135A priority patent/EP0484180A1/en
Publication of JPH04299848A publication Critical patent/JPH04299848A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device whose cost is low, which does not cause any crack in a molding resin, and whose thermal resistance is low. CONSTITUTION:A semiconductor element 4 is mounted on a die stage part 1 at a lead frame which is provided with the following: the die stage part 1 on which the semiconductor element is mounted; an inner lead part 2; and an outer lead part 3. At a semiconductor device in which the semiconductor element 4 and the inner lead part 2 at the lead frame are molded by a resin 6, a heat-dissipating block 7 is bonded so as to come into contact with the rear of a face on which the semiconductor element 4 has been mounted of the die stage part 1 at said lead frame, and a gap 8 is formed between the outer circumferential side face of said heat-dissipating block 7 and the resin 6.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置に関する。詳
しくは、放熱ブロックを用いた低熱抵抗のプラスチック
パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. Specifically, the present invention relates to a low thermal resistance plastic package using a heat dissipation block.

【0002】近年、IC等の半導体集積回路は、ハイパ
ワー及びハイスピード化してきており、それに伴って多
量の熱を発生するようになってきている。従って熱抵抗
の低いパッケージが要求されている。
[0002] In recent years, semiconductor integrated circuits such as ICs have become higher in power and speed, and as a result, a large amount of heat has been generated. Therefore, a package with low thermal resistance is required.

【0003】従来、低熱抵抗のパッケージには主として
熱伝導の良いセラミックパッケージが用いられている。 しかしセラミックパッケージは高価であるため、低価格
のプラスチックパッケージで低熱抵抗とすることが要求
されている。
Conventionally, ceramic packages with good thermal conductivity have been mainly used as packages with low thermal resistance. However, since ceramic packages are expensive, there is a demand for low-cost plastic packages with low thermal resistance.

【0004】0004

【従来の技術】図3に従来の低熱抵抗のプラスチックパ
ッケージを示す。これはダイステージ部1とインナーリ
ード部2とアウターリード部3とを有するリードフレー
ムの、ダイステージ部1に半導体素子4が搭載され、該
半導体素子4の電極とインナーリード部2間がワイヤ5
でワイヤボンディングされ、さらに該半導体素子4とダ
イステージ部1及びインナーリード部2が樹脂6でモー
ルドされ、その一方の面に放熱ブロック7が接合されて
いる。
2. Description of the Related Art FIG. 3 shows a conventional low thermal resistance plastic package. This is a lead frame having a die stage section 1, an inner lead section 2, and an outer lead section 3. A semiconductor element 4 is mounted on the die stage section 1, and a wire 5 is connected between the electrode of the semiconductor element 4 and the inner lead section 2.
Further, the semiconductor element 4, die stage section 1, and inner lead section 2 are molded with resin 6, and a heat dissipation block 7 is bonded to one surface thereof.

【0005】[0005]

【発明が解決しようとする課題】上記従来の低熱抵抗の
プラスチックパッケージでは半導体素子4と放熱ブロッ
ク7との間に樹脂6が介在するため放熱効率は良好とは
言い難い。そこで放熱効率を向上するため、図4に示す
ように半導体素子4を搭載したダイステージ部1の裏面
に直接接触するように放熱ブロック7を設けることが考
えられる。
Problems to be Solved by the Invention In the above conventional plastic package with low thermal resistance, the resin 6 is interposed between the semiconductor element 4 and the heat radiation block 7, so that the heat radiation efficiency cannot be said to be good. Therefore, in order to improve heat dissipation efficiency, it is conceivable to provide a heat dissipation block 7 so as to directly contact the back surface of the die stage section 1 on which the semiconductor element 4 is mounted, as shown in FIG.

【0006】ところが上記方式では放熱ブロック7の周
囲側面と樹脂6が密着しているため、半導体素子4が発
熱した場合、両者の熱膨張率の差による応力が生じ、樹
脂6にクラックが発生するという問題が生ずる。
However, in the above method, since the peripheral side surface of the heat dissipation block 7 and the resin 6 are in close contact with each other, when the semiconductor element 4 generates heat, stress is generated due to the difference in coefficient of thermal expansion between the two, and cracks occur in the resin 6. This problem arises.

【0007】また上記方式の半導体装置の製造方法とし
ては、■リードフレームのダイステージ部1の一方の面
に半導体素子4を、他方の面に放熱ブロック7を接着し
、次いで半導体素子4とリードフレームのインナーリー
ド2間をワイヤボンディングし、その後樹脂モールドす
る方法と、■リードフレームのダイステージ部1に半導
体素子4を搭載し、次いでワイヤボンディングした後に
、ダイステージ部1の裏面に放熱ブロック7を接着し、
その後樹脂モールドする方法とが考えられる。
Furthermore, as a method for manufacturing a semiconductor device of the above type, (1) a semiconductor element 4 is adhered to one surface of the die stage section 1 of a lead frame, a heat dissipation block 7 is adhered to the other surface, and then the semiconductor element 4 and the leads are bonded. A method of wire bonding between the inner leads 2 of the frame and then resin molding. 2. Mounting the semiconductor element 4 on the die stage part 1 of the lead frame, then wire bonding, and then attaching the heat dissipation block 7 to the back surface of the die stage part 1. Glue the
One possible method is to then mold it with a resin.

【0008】ところか上記製造方法において、■のワイ
ヤボンディング前に放熱ブロック7を接着しておく方法
は、ワイヤボンディング時にリードフレームを加熱する
ための熱が放熱ブロック7に遮ぎられるため、リードフ
レームに伝わりにくく、ワイヤボンディングが困難にな
るという問題が生ずる。
On the other hand, in the above manufacturing method, the method (2) in which the heat radiation block 7 is bonded before wire bonding is such that the heat for heating the lead frame during wire bonding is blocked by the heat radiation block 7. A problem arises in that the wire bonding becomes difficult.

【0009】また■のワイヤボンディング後に放熱ブロ
ック7を接着する方法は、ダイステージ部1に放熱ブロ
ック7を接着するとき、リードフレームにサポートバー
で支持されているダイステージ部1が動き、半導体素子
4の電極にボンディングされている25〜38μm程度
の細い金のワイヤ5のネック部に力がかかり、そこが切
断し、歩留りが低下するという問題が生ずる。
[0009] Furthermore, in the method (3) of bonding the heat dissipation block 7 after wire bonding, when the heat dissipation block 7 is bonded to the die stage section 1, the die stage section 1 supported by the support bar on the lead frame moves and the semiconductor element A problem arises in that force is applied to the neck portion of the thin gold wire 5 of about 25 to 38 μm bonded to the electrode 4, and the neck portion is broken, resulting in a decrease in yield.

【0010】本発明は、ローコストで、且つモールド樹
脂にクラックが発生しないようにした低熱抵抗の半導体
装置を実現しようとする。
[0010] The present invention aims to realize a semiconductor device which is low in cost and has low thermal resistance in which cracks do not occur in the molding resin.

【0011】[0011]

【課題を解決するための手段】本発明の半導体装置にお
いては、半導体素子を搭載するダイステージ部と、イン
ナーリード部及びアウターリード部を有するリードフレ
ームの、該ダイステージ部に半導体素子が搭載され、該
半導体素子とリードフレームのインナーリード部が樹脂
にてモールドされて成る半導体装置において、上記リー
ドフレームのダイステージ部の半導体素子が搭載された
面の裏面に接して放熱ブロックが接合され、且つ該放熱
ブロックの外周側面と樹脂との間に間隙が設けられて成
ることを特徴とする。
[Means for Solving the Problems] In the semiconductor device of the present invention, the semiconductor element is mounted on the die stage part of a lead frame having a die stage part on which the semiconductor element is mounted, an inner lead part and an outer lead part. , in a semiconductor device in which the semiconductor element and the inner lead part of the lead frame are molded with resin, a heat dissipation block is bonded in contact with the back surface of the surface on which the semiconductor element is mounted of the die stage part of the lead frame, and It is characterized in that a gap is provided between the outer peripheral side surface of the heat radiation block and the resin.

【0012】また、それに加えて上記放熱ブロックと樹
脂との間隙が50μm乃至 500μmであることを特
徴とする。
In addition, the present invention is characterized in that the gap between the heat dissipation block and the resin is 50 μm to 500 μm.

【0013】また、本発明の半導体装置の製造方法にお
いては、リードフレームのダイステージ部の一方の面に
半導体素子をダイボンディングし、さらに該半導体素子
の電極とリードフレームのインナーリード部との間をワ
イヤボンディングする工程と、上型と下型とよりなる金
型のキャビティ内に、前記リードフレームのダイステー
ジ部を支承する突起と、該突起の表面に開口する真空吸
引孔とが形成された金型を用いて、前記半導体素子及び
リードフレームのインナーリード部を樹脂にてモールド
する工程と、ダイステージ部の半導体素子搭載面の反対
面に、放熱ブロックを、その外周側面と樹脂との間に間
隙ができるように接着する工程とよりなることを特徴と
する。この構成を採ることに依り、ローコストで、且つ
モールド樹脂にクラックが発生しない低熱抵抗の半導体
装置が得られる。
Further, in the method for manufacturing a semiconductor device of the present invention, a semiconductor element is die-bonded to one surface of the die stage portion of the lead frame, and further, a bond is formed between the electrode of the semiconductor element and the inner lead portion of the lead frame. A protrusion for supporting the die stage portion of the lead frame and a vacuum suction hole opening on the surface of the protrusion are formed in a cavity of a mold consisting of an upper die and a lower die. A step of molding the semiconductor element and the inner lead part of the lead frame with resin using a mold, and a step of placing a heat dissipation block on the opposite side of the semiconductor element mounting surface of the die stage part between the outer peripheral side surface and the resin. It is characterized by a step of adhering the material so that a gap is created between the two. By adopting this configuration, it is possible to obtain a semiconductor device that is low in cost and has a low thermal resistance in which no cracks occur in the molding resin.

【0014】[0014]

【作用】半導体素子4を封止したモールド樹脂6と放熱
ブロック7の外周側面との間に間隙8を設けたことによ
り、放熱ブロック7と樹脂6との熱膨張率の差により樹
脂6内に生ずる応力を緩和し、クラックの発生を防止す
ることができる。
[Function] By providing a gap 8 between the mold resin 6 that seals the semiconductor element 4 and the outer peripheral side of the heat radiation block 7, the difference in thermal expansion coefficient between the heat radiation block 7 and the resin 6 causes the inside of the resin 6 to It is possible to alleviate the stress that occurs and prevent the occurrence of cracks.

【0015】また製造時には樹脂モールド後に放熱ブロ
ック7をダイステージ部に接合するようにしたことによ
り、モールド樹脂のポストキュアと放熱ブロックを接着
した接着剤のキュアを同時に行なうことができ、工数が
節減され、またボンディングワイヤの切断もなく、歩留
りが向上し低コストとなる。
Furthermore, by joining the heat dissipation block 7 to the die stage part after resin molding during manufacturing, post-curing of the mold resin and curing of the adhesive bonding the heat dissipation block can be performed simultaneously, reducing man-hours. Furthermore, there is no need to cut the bonding wire, improving yield and reducing costs.

【0016】[0016]

【実施例】図1は本発明の半導体装置の実施例を示す図
である。同図において、1はリードフレームのダイステ
ージ部であり、該ダイステージ部1の一方の面には半導
体素子4がダイボンディングされ、他方の面には放熱ブ
ロック7が接合されている。2はリードフレームのイン
ナーリード部で、該インナーリード部2と半導体素子4
の電極との間は金線等のワイヤ5でワイヤボンディング
されている。3はリードフレームのインナーリード2に
接続しているアウターリードである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of a semiconductor device according to the present invention. In the figure, 1 is a die stage portion of a lead frame, and a semiconductor element 4 is die-bonded to one surface of the die stage portion 1, and a heat dissipation block 7 is bonded to the other surface. 2 is an inner lead part of the lead frame, and the inner lead part 2 and the semiconductor element 4 are connected to each other.
A wire 5 such as a gold wire is used for wire bonding with the electrode. 3 is an outer lead connected to the inner lead 2 of the lead frame.

【0017】そして半導体素子4及びダイステージ部1
とインナーリード部2は樹脂6でモールドされているが
、該樹脂6と放熱ブロック7の外周側面との間には間隙
8が設けられている。なお放熱ブロック7としては熱伝
導の良いAl ,Cu 等の金属又はセラミック等が用
いられる。
[0017] The semiconductor element 4 and the die stage section 1
The inner lead portion 2 is molded with resin 6, and a gap 8 is provided between the resin 6 and the outer circumferential side of the heat radiation block 7. Note that the heat dissipation block 7 is made of metal such as Al or Cu, or ceramic, etc., which has good thermal conductivity.

【0018】このように構成された本実施例は、半導体
素子4からの発熱があった場合、放熱ブロック7と樹脂
6との間に熱膨張率の差があっても、該放熱ブロック7
と樹脂6との間には間隙8があるため、樹脂6は発生す
る応力は緩和される。従って樹脂6おけるクラックの発
生は防止される。
In this embodiment configured as described above, when heat is generated from the semiconductor element 4, even if there is a difference in coefficient of thermal expansion between the heat dissipation block 7 and the resin 6, the heat dissipation block 7
Since there is a gap 8 between the resin 6 and the resin 6, the stress generated in the resin 6 is relaxed. Therefore, generation of cracks in the resin 6 is prevented.

【0019】次に本発明の半導体装置の製造方法の実施
例を図2により説明する。本実施例の製造方法は、先ず
図2(a)の如くリードフレームのダイステージ部1に
半導体素子4をダイボンディングし、次いで該半導体素
子4の電極とリードフレームのインナーリード部2との
間をワイヤ5でワイヤボンディングする。
Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In the manufacturing method of this embodiment, the semiconductor element 4 is first die-bonded to the die stage part 1 of the lead frame as shown in FIG. are wire-bonded using wire 5.

【0020】次に図2(b)に示すように半導体素子4
とダイステージ部1及びインナーリード部2を樹脂にて
モールドする。このとき用いるモールド金型9は上型9
aと下型9bとよりなり、キャビティ9cと下型9b側
にはリードフレームのダイステージ部1を支承できる突
起10と、該突起10の表面に開口し、ダイステージ部
1を吸着できる真空吸引孔11とが設けられ、該真空吸
引孔11は真空ポンプ12に接続されている。そして突
起10にダイステージ部1を吸着した状態で半導体素子
4及びインナーリード2と共に樹脂モールドするのであ
る。
Next, as shown in FIG. 2(b), the semiconductor element 4
Then, the die stage part 1 and inner lead part 2 are molded with resin. The mold die 9 used at this time is the upper die 9.
a and a lower die 9b, and on the side of the cavity 9c and the lower die 9b there is a protrusion 10 that can support the die stage part 1 of the lead frame, and a vacuum suction opening on the surface of the protrusion 10 that can suck the die stage part 1. A hole 11 is provided, and the vacuum suction hole 11 is connected to a vacuum pump 12. Then, with the die stage part 1 attracted to the protrusion 10, the semiconductor element 4 and the inner leads 2 are resin-molded.

【0021】次に図2(c)の如く樹脂モールドした半
成品13を金型9より取り出し、次いで図2(d)の如
く放熱ブロック7を用意し、この放熱ブロック7を図2
(e)を示す如く、金型9の突起10により形成された
凹部に接着剤を用いて接着し、最後に加熱処理して樹脂
6及び接着剤を硬化させて完成するのである。
Next, the resin-molded semi-finished product 13 is taken out from the mold 9 as shown in FIG. 2(c), and then the heat radiation block 7 is prepared as shown in FIG. 2(d).
As shown in (e), adhesive is used to adhere to the recess formed by the protrusion 10 of the mold 9, and finally heat treatment is performed to harden the resin 6 and adhesive to complete the process.

【0022】なお放熱ブロックの位置決めのためと、接
着剤が外部から見えない様にするため、該放熱ブロック
7の外周側面と樹脂6の凹部側壁との間の間隙は50〜
 500μm程度とすることが好ましい。
In order to position the heat dissipation block and to prevent the adhesive from being seen from the outside, the gap between the outer peripheral side of the heat dissipation block 7 and the side wall of the recess of the resin 6 is set to 50 to 50 mm.
The thickness is preferably about 500 μm.

【0023】本実施例によれば、ダイステージ部1に放
熱ブロック7を接合する前にワイヤボンディングを行な
うため、リードフレームの加熱を充分に行なうことがで
き、ワイヤボンディングが容易となり、またハンドリン
グも容易となり、ワイヤの切断も発生しない。またモー
ルド樹脂6のポストキュアと、放熱ブロック7を接着し
た接着剤の硬化とを同時に行なうことができるので従来
に比して工数の節減ができる。
According to this embodiment, since wire bonding is performed before bonding the heat dissipation block 7 to the die stage section 1, the lead frame can be sufficiently heated, wire bonding becomes easy, and handling is also simplified. It is easy and there is no wire breakage. Further, since the post-curing of the mold resin 6 and the curing of the adhesive bonding the heat dissipating block 7 can be performed simultaneously, the number of man-hours can be reduced compared to the conventional method.

【0024】[0024]

【発明の効果】本発明に依れば、放熱ブロックを直接ダ
イステージ部に接合することにより、低熱抵抗の半導体
装置が実現できる。また放熱ブロックの周囲側面とモー
ルド樹脂との間に間隙を設けることにより、放熱ブロッ
クと樹脂との熱膨張率の差に起因して樹脂に生ずるクラ
ックの発生を防止することができる。さらにプラスチッ
クパッケージであること、及び製造段階での歩留りの向
上、工数の節減等によりローコスト化が実現できる。
According to the present invention, a semiconductor device with low thermal resistance can be realized by directly bonding the heat radiation block to the die stage section. Further, by providing a gap between the peripheral side surface of the heat radiation block and the molded resin, it is possible to prevent cracks from occurring in the resin due to the difference in coefficient of thermal expansion between the heat radiation block and the resin. Furthermore, because it is a plastic package, yields are improved in the manufacturing stage, and man-hours are reduced, costs can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の半導体装置の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の製造方法の実施例を説明
するための図である。
FIG. 2 is a diagram for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.

【図3】従来の低熱抵抗のプラスチックパッケージを示
す図である。
FIG. 3 is a diagram showing a conventional low thermal resistance plastic package.

【図4】発明が解決しようとする課題を説明するための
図である。
FIG. 4 is a diagram for explaining the problem to be solved by the invention.

【符号の説明】[Explanation of symbols]

1…ダイステージ部 2…インナーリード部 3…アウターリード部 4…半導体素子 5…ワイヤ 6…樹脂 7…放熱ブロック 8…隙間 9…モールド金型 10…突起 11…真空吸引孔 12…真空ポンプ 13…半成品 1...Die stage section 2...Inner lead part 3...Outer lead part 4...Semiconductor element 5...Wire 6...Resin 7... Heat dissipation block 8...Gap 9...Mold die 10...Protrusion 11...Vacuum suction hole 12...Vacuum pump 13...Semi-finished product

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  半導体素子を搭載するダイステージ部
(1)と、インナーリード部(2)及びアウターリード
部(3)を有するリードフレームの、該ダイステージ部
(1)に半導体素子(4)が搭載され、該半導体素子(
4)とリードフレームのインナーリード部(2)が樹脂
(6)にてモールドされて成る半導体装置において、上
記リードフレームのダイステージ部(1)の半導体素子
(4)が搭載された面の裏面に接して放熱ブロック(7
)が接合され、且つ該放熱ブロック(7)の外周側面と
樹脂(6)との間に間隙(8)が設けられて成ることを
特徴とする半導体装置。
1. A lead frame having a die stage part (1) on which a semiconductor element is mounted, an inner lead part (2) and an outer lead part (3), the semiconductor element (4) is mounted on the die stage part (1). is mounted, and the semiconductor element (
4) In a semiconductor device in which the inner lead portion (2) of the lead frame is molded with resin (6), the back side of the surface on which the semiconductor element (4) of the die stage portion (1) of the lead frame is mounted. Heat dissipation block (7
) are bonded to each other, and a gap (8) is provided between the outer peripheral side surface of the heat radiation block (7) and the resin (6).
【請求項2】  上記放熱ブロック(7)と樹脂(6)
との間隙(8)が50μm乃至 500μmであること
を特徴とする請求項1の半導体装置。
[Claim 2] The heat radiation block (7) and the resin (6)
2. The semiconductor device according to claim 1, wherein the gap (8) between the semiconductor device and the semiconductor device is 50 μm to 500 μm.
【請求項3】  リードフレームのダイステージ部(1
)の一方の面に半導体素子(4)をダイボンディングし
、さらに該半導体素子(4)の電極とリードフレームの
インナーリード部(2)との間をワイヤボンディングす
る工程と、上型(9a)と下型(9b)とよりなる金型
のキャビティ(9c)内に、前記リードフレームのダイ
ステージ部(1)を支承する突起(10)と、該突起(
10)の表面に開口する真空吸引孔(11)とが形成さ
れた金型(9)を用いて、前記半導体素子(4)及びリ
ードフレームのインナーリード部(2)を樹脂(6)に
てモールドする工程と、ダイステージ部(1)の半導体
素子搭載面の反対面に、放熱ブロック(7)を、その外
周側面と樹脂(6)との間に間隙(8)ができるように
接着する工程とによりなることを特徴とする半導体装置
の製造方法。
[Claim 3] Die stage part (1
) and die bonding the semiconductor element (4) to one surface of the upper die (9a), and further wire bonding between the electrode of the semiconductor element (4) and the inner lead part (2) of the lead frame. In the cavity (9c) of the mold consisting of a lower mold (9b) and a protrusion (10) that supports the die stage part (1) of the lead frame, the protrusion (
The semiconductor element (4) and the inner lead part (2) of the lead frame are made of resin (6) using a mold (9) in which a vacuum suction hole (11) is formed on the surface of the mold (10). In the molding process, a heat dissipation block (7) is bonded to the surface opposite to the semiconductor element mounting surface of the die stage section (1) so that a gap (8) is created between the outer peripheral side surface and the resin (6). 1. A method for manufacturing a semiconductor device, comprising the steps of:
JP6482991A 1990-11-01 1991-03-28 Semiconductor device and its manufacture Pending JPH04299848A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6482991A JPH04299848A (en) 1991-03-28 1991-03-28 Semiconductor device and its manufacture
EP91310135A EP0484180A1 (en) 1990-11-01 1991-11-01 Packaged semiconductor device having an optimized heat dissipation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6482991A JPH04299848A (en) 1991-03-28 1991-03-28 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH04299848A true JPH04299848A (en) 1992-10-23

Family

ID=13269529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6482991A Pending JPH04299848A (en) 1990-11-01 1991-03-28 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH04299848A (en)

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