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JPH04299595A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH04299595A
JPH04299595A JP3064214A JP6421491A JPH04299595A JP H04299595 A JPH04299595 A JP H04299595A JP 3064214 A JP3064214 A JP 3064214A JP 6421491 A JP6421491 A JP 6421491A JP H04299595 A JPH04299595 A JP H04299595A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
chip carrier
surface mount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3064214A
Other languages
Japanese (ja)
Inventor
Norimasa Takada
高田 教正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3064214A priority Critical patent/JPH04299595A/en
Publication of JPH04299595A publication Critical patent/JPH04299595A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/145Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To realize a hybrid integrated circuit device whose packaging density is higher than that of the conventional device. CONSTITUTION:Surface mounting devices 1 are packaged between two retaining boards 2, so as to be in parallel with each other and vertical to the two boards 2. A package having gull wing type leads, a leadless chip carrier, etc., are applied to the surface mounting device 1. The package occupied area on the retaining board 2 is 1/4-1/3 as compared with the conventional single-sided board mounting, and 1/2-2/3 as compared with the doubled-sided board mounting.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は混成集積回路装置に関し
、特に表面実装デバイスを搭載した混成集積回路装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device equipped with a surface-mounted device.

【0002】0002

【従来の技術】図4は、従来のSOPなどの表面実装デ
バイス1をプリント基板などの支持基板2a上に搭載し
た混成集積回路装置の断面構造を示している。この表面
実装デバイス1が支持基板2の両面に搭載されたもので
ある。
2. Description of the Related Art FIG. 4 shows a cross-sectional structure of a hybrid integrated circuit device in which a conventional surface mount device 1 such as an SOP is mounted on a support substrate 2a such as a printed circuit board. This surface mount device 1 is mounted on both sides of a support substrate 2.

【0003】0003

【発明が解決しようとする課題】この従来の混成集積回
路装置では、高い実装密度が得られないという問題点が
あった。支持基板2の上に多数個の表面実装デバイス1
を搭載する場合、支持基板2は両面搭載で、搭載パッケ
ージの合計面積の少なくとも1/2は必要で、今日のよ
うに混成集積回路装置が大規模になって搭載パッケージ
の数が増加すればするほど支持基板上でのパッケージ占
有面積が増大する。
SUMMARY OF THE INVENTION This conventional hybrid integrated circuit device has a problem in that high packaging density cannot be achieved. A large number of surface mount devices 1 are mounted on a support substrate 2.
, the support substrate 2 needs to be mounted on both sides and occupy at least 1/2 of the total area of the mounted packages, and as hybrid integrated circuit devices become large-scale and the number of mounted packages increases as seen today. The area occupied by the package on the support substrate increases accordingly.

【0004】本発明の目的は、このような問題を解決し
、表面実装デバイスの占有面積を小さくし、その実装密
度を向上させた混成集積回路装置を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device that solves these problems, reduces the area occupied by surface-mounted devices, and improves the packaging density.

【0005】[0005]

【課題を解決するための手段】本発明の混成集積回路装
置の構成は、複数個の表面実装デバイスを互いに平行に
、かつ2枚の支持基板の間に垂直に実装したことを特徴
とする。
A hybrid integrated circuit device according to the present invention is characterized in that a plurality of surface mount devices are mounted parallel to each other and perpendicularly between two supporting substrates.

【0006】また、本発明において表面実装デバイスが
リードレスチップキャリアであることもできる。
[0006] In the present invention, the surface mount device can also be a leadless chip carrier.

【0007】[0007]

【実施例】図1(a)は本発明の第1の実施例を示す側
面図である。複数個の表面実装デバイス1は互いに平行
に2枚の支持基板2に垂直に実装されている。各表面実
装デバイス1のガルウィング型のリードは、支持基板2
に挿入され、表面実装デバイス間の接続は、少なくとも
両側(場合によっては4方向)に配置した支持基板2の
上の配線で行なわれる。
Embodiment FIG. 1(a) is a side view showing a first embodiment of the present invention. A plurality of surface mount devices 1 are mounted parallel to each other and perpendicularly to two support substrates 2. The gull wing type leads of each surface mount device 1 are connected to the supporting substrate 2.
The surface mount devices are connected to each other by wiring on the supporting substrate 2 arranged on at least both sides (in four directions in some cases).

【0008】また、図1(b)に示すように、この混成
集積回路装置の支持基板2の端にクリップ端子3をつけ
、別の基板2bの上に挿入して実装することも可能であ
る。
Furthermore, as shown in FIG. 1(b), it is also possible to attach a clip terminal 3 to the end of the support substrate 2 of this hybrid integrated circuit device and insert it onto another substrate 2b for mounting. .

【0009】図2は本発明の第2の実施例を実装した側
断面図であり、表面実装デバイス1としてリードレスチ
ップキャリア12を使用した場合を示している。
FIG. 2 is a sectional side view of a second embodiment of the present invention, in which a leadless chip carrier 12 is used as the surface mount device 1.

【0010】通常のリードレスチップキャリアは、図3
(a),(b)の斜視図およびそのA−A′断面図のよ
うに示される。端面スルーホール電極4をもつ基板5上
に、樹脂枠6で制限される内側に封止樹脂7が塗布され
ている。また、基板5上に搭載されたICチップ8は、
ボンディングワイヤ9により、配線10を介して端面ス
ルーホール電極4に接続されており、またこの端面スル
ーホール電極4は、裏面電極11にも接続されている。 支持基板2上にリードレスチップキャリア12が実装さ
れ、リードレスチップキャリア12は、端面スルーホー
ル電極4を介して、例えば半田により支持基板2に接続
されている。
A typical leadless chip carrier is shown in FIG.
It is shown as a perspective view of (a), (b) and its AA' cross-sectional view. A sealing resin 7 is applied on the substrate 5 having the end surface through-hole electrodes 4 on the inner side defined by the resin frame 6. Moreover, the IC chip 8 mounted on the substrate 5 is
The bonding wire 9 is connected to the end surface through-hole electrode 4 via the wiring 10, and the end surface through-hole electrode 4 is also connected to the back surface electrode 11. A leadless chip carrier 12 is mounted on the support substrate 2, and the leadless chip carrier 12 is connected to the support substrate 2 by, for example, solder via the end surface through-hole electrode 4.

【0011】[0011]

【発明の効果】以上説明したように本発明は、表面実装
デバイスを互いに平行にかつ支持基板に垂直に実装した
ので、支持基板上の表面実装デバイスの占有面積を小さ
くでき実装密度を向上できるという効果がある。通常の
パッケージは、パッケージサイズに比べてパッケージの
厚みはおおむね1/4〜1/3なので、従来の片面実装
に比べて1/4〜1/3に、また従来の両面実装に比べ
て、1/2〜2/3程度に支持基板上での占有面積を小
さくすることができる。
[Effects of the Invention] As explained above, in the present invention, since the surface mount devices are mounted parallel to each other and perpendicular to the support substrate, the area occupied by the surface mount devices on the support substrate can be reduced and the mounting density can be improved. effective. In a normal package, the thickness of the package is approximately 1/4 to 1/3 compared to the package size, so it is 1/4 to 1/3 compared to conventional single-sided mounting, and 1/3 compared to conventional double-sided mounting. The area occupied on the support substrate can be reduced to about 2/2 to 2/3.

【0012】また、第1の実施例に比べて、第2の実施
例の場合は、リードレスチップキャリア12が支持基板
1への表面実装ゆえに、リードレスチップキャリアが搭
載された面とは反対側の支持基板上の面にも配線するこ
とができ、支持基板設計の自由度が増すとともに一層の
高密度配線を可能である。
Furthermore, compared to the first embodiment, in the case of the second embodiment, since the leadless chip carrier 12 is surface mounted on the support substrate 1, the surface on which the leadless chip carrier is mounted is opposite to the surface on which the leadless chip carrier is mounted. Wiring can also be done on the surface of the supporting substrate on the side, increasing the degree of freedom in designing the supporting substrate and enabling even higher density wiring.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】(a),(b)は本発明の第1の実施例を示す
側断面図およびその応用例の側面図。
FIGS. 1(a) and 1(b) are a side sectional view showing a first embodiment of the present invention and a side view of an application example thereof.

【図2】本発明の第2の実施例の側断面図。FIG. 2 is a side sectional view of a second embodiment of the invention.

【図3】(a),(b)は通常のリードレスチップキャ
リアの斜視図およびそのA−A′断面図。
FIGS. 3(a) and 3(b) are a perspective view and a sectional view taken along line AA' of a typical leadless chip carrier.

【図4】従来例を示す側断面図。FIG. 4 is a side sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1    表面実装デバイス 2    支持基板 3    クリップ端子 4    端面スルーホール電極 5    基板 6    樹脂枠 7    封止樹脂 8    ICチップ 9    ボンディングワイヤ 10    配線 11    裏面電極 1    Surface mount device 2 Support board 3 Clip terminal 4 End surface through-hole electrode 5     Substrate 6 Resin frame 7 Sealing resin 8 IC chip 9 Bonding wire 10 Wiring 11    Back electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  複数個の表面実装デバイスを互いに平
行に、かつ2枚の支持基板の間に垂直に実装したことを
特徴とする混成集積回路装置。
1. A hybrid integrated circuit device characterized in that a plurality of surface mount devices are mounted parallel to each other and perpendicularly between two supporting substrates.
【請求項2】  表面実装デバイスがリードレスチップ
キャリアである請求項1記載の混成集積回路装置。
2. The hybrid integrated circuit device of claim 1, wherein the surface mount device is a leadless chip carrier.
JP3064214A 1991-03-28 1991-03-28 Hybrid integrated circuit device Pending JPH04299595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3064214A JPH04299595A (en) 1991-03-28 1991-03-28 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3064214A JPH04299595A (en) 1991-03-28 1991-03-28 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04299595A true JPH04299595A (en) 1992-10-22

Family

ID=13251616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3064214A Pending JPH04299595A (en) 1991-03-28 1991-03-28 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04299595A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04345083A (en) * 1991-05-23 1992-12-01 Fujitsu Ltd Printed wiring board for three-dimensional mounting and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04345083A (en) * 1991-05-23 1992-12-01 Fujitsu Ltd Printed wiring board for three-dimensional mounting and its manufacture

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Effective date: 19990202