JPH04296899A - Musical interval controller - Google Patents

Abstract

PURPOSE:To suppress the generation of tremolo sound and the reverberation phenomenon in the musical interval control. CONSTITUTION:If the sampling cycle of the input audio signal data is TO, the value for representing the number of times of the cycle for skip reading or rereading the data from a memory in comparison with the sampling cycle TO is Jn, and the allowable time of the shift in time as the data between a plurality of read-out addresses is Tdmax, the max value Dmax of the address interval of a plurality of read-out addresses in case of the increase of musical interval is set as follows: Dmax=Tdmax/((1-1/Jn).TO), and in case of the reduction of musical interval, Dmax=Tdmax/((1+1/Jn).TO), and the allowable time Tdmax is set to 45-80msec where the reverberation phenomenon does not become conspicuous. The reverberation phenomenon can be suppressed by suppressing the generation of the tremolo sound, setting the size of a ring buffer memory large.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a pitch control device, and more particularly to a pitch control device that controls the pitch between an original sound and a reproduced sound by changing the frequency of an audio signal to a desired frequency.

0002

BACKGROUND ART Conventionally, a pitch control device sequentially writes data obtained by sampling an analog input signal into a ring buffer memory, reads the data at a cycle different from the write cycle, and stores the read data. - There is a system in which the pitch of the signal is changed by sequentially demodulating the data. In such a device, when the read cycle of data from the ring buffer memory is longer than the write cycle (that is, when the pitch is lowered), the data stored in the buffer memory is read at predetermined intervals, and the previously read data is - If some of the data is read out overlappingly, or if the data reading cycle is shorter than the writing cycle (in other words, when increasing the pitch), some of the data to be read out is skipped and subsequent data is read out. The amount of data to be read is adjusted by reading from. Note that if both the read cycle and the write cycle can be changed, there is no need to skip reading or read twice. When skipping or reading twice, if there is little correlation between the data contents before and after, discontinuities will occur in the reproduced sound. In order to alleviate this problem, a so-called cross-fade method is used. To explain when the read cycle is shorter than the write cycle, as shown in FIG. 6(a), dR-W, which indicates the difference between the write point W and the read point R of the ring buffer memory, is usually larger than a predetermined value dth. It is. It is assumed that each point advances clockwise. When dR-W < dth, as shown in Fig. 6(b), data is also read from a point R' by a predetermined value dth in the clockwise direction from the readout point R, and the data value from the readout point R is linearly Cross-fading is possible by performing fade-out processing, linearly fade-in processing the data values from the readout point R', and adding each data value.

[0003] During the cross-fade period, the number of reading points changes from one to two, so depending on the frequency components in the signal, they may be out of phase with each other and cancel out, or they may not be in phase with each other. The frequency component level increases, and as a result, the change in frequency characteristics over time becomes large as shown in FIG. 7, and so-called tremolo sound is generated. The larger the size, that is, the capacity, of the ring buffer memory, the larger the predetermined value dth can be, so the number of dips in the characteristics shown in FIG. 7 increases, but the intervals between the dips become narrower, and the width of the dips themselves become narrower. Therefore, the probability that the frequency of the audio signal becomes equal to the frequency of this dip becomes low, so it is thought that tremolo sound is less likely to occur.

[0004] However, even if a large number of reading points can be obtained, the time lag between each reading data becomes large. , after pitch control, a reverberation phenomenon occurs that sounds like being struck twice or more. In the conventional pitch control device described above, such a phenomenon can occur only during the crossfade period, but by constantly specifying multiple reading points in the ring buffer memory and reading the data individually, the read data value is In a pitch control device that obtains output data by multiplying coefficients and adding them to each other, if the size of the ring buffer memory is increased, reverberation may always occur.

[0005]

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a pitch control device that can suppress the generation of tremolo sound and the reverberation phenomenon.

[0006]

[Structure of the Invention] The pitch control device of the present invention is configured to store one part of the memory every sampling period T0 of input audio signal data.
write address specifying means for specifying write addresses in a predetermined order in a predetermined order, and write address specifying means for specifying a plurality of read addresses in the memory individually in a predetermined order every sampling period T0, and a predetermined multiple Jn of the sampling period T0.
(an integer greater than or equal to 2), when the pitch rises, the multiple read addresses are set to addresses after the sampling period T0 by at least 1, and when the pitch falls, the multiple read addresses are changed by at least 1 sampling period T0.
0 read addressing means for setting the previous address;
means for writing input audio signal data to storage locations at specified write addresses in said memory; and means for writing input audio signal data from storage locations at specified read addresses in said memory;
means for reading out the data for each of the data, means for setting a coefficient for each of the plurality of read addresses according to the address interval with the write address, and means for multiplying the data read for each of the plurality of read addresses by the corresponding coefficient. and an arithmetic means for adding the data values of the multiplication results to each other to obtain output data, the pitch control device having an allowable time for a time difference in data between a plurality of read addresses. If Tdmax is the maximum value Dmax of the address interval of multiple read addresses, when the pitch rises, Dmax = Tdmax/{(1-1/Jn)・T0
}, and when the pitch falls, Dmax = Tdmax/{(1+1/Jn)・T0
}, and the allowable time Tdmax is set to 45 to 80 msec.

[0007]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the pitch control device according to the present invention shown in FIG. 1, an audio signal output from an analog audio signal source 1 such as a tuner, tape deck, or microphone is supplied to an A/D converter 2. . A DSP (digital signal processor) 3 is connected to the output of the A/D converter 2. The DSP 3 is configured as described below and is controlled by a microcomputer 4. A ring buffer memory 9 is connected to the DSP 3. For example, the ring buffer memory 9 has storage locations of 3000 addresses (words) or more. A D/A converter 5 is connected to the output of the DSP 3, and the digital audio signal output from the DSP 3 is converted into an analog audio signal. A speaker 7 is connected to the output of the D/A converter 5 via a power amplifier 6. Note that in the case of a digital audio signal source such as a DAT, it can be connected to the DSP 3 without going through the A/D converter 2.

FIG. 2 schematically shows the configuration of the DSP 3. That is, the digital signal from the A/D converter 2 is supplied to the input interface 13 within the DSP 3. A data bus 14 is connected to the input interface 13, and this data bus 14 is connected to the data memory 1.
2. It is connected to the buffer memories 16 and 28 and the coefficient RAM 17. Multiplier 1 is connected to the output of buffer memory 28.
One input of 5 is connected. The output of the buffer memory 16 is connected to the other input of the multiplier 15. The buffer memory 16 is also connected to the coefficient RAM 17 and R
AM17 stores a plurality of coefficient data. One coefficient data is read out of the coefficient data group stored in the RAM 17 in response to a timing signal from the sequence controller 20, which will be described later, and is stored in the buffer memory 16.
is supplied and held. The coefficient data held in the buffer memory 16 is supplied to the multiplier 15. ALU(A
The calculation output of the multiplier 15 and the data bus 14 are connected to one input of the (rithmetic logic unit) 18.
is connected, and the other is connected to the data bus 14. ALU 18 adds or compares both input data. An accumulator 19 is connected to the calculation output of the ALU 18, and the output of the accumulator 19 is connected to the data bus 14. A memory control circuit 22 for controlling data writing and reading from the ring buffer memory 9 is connected to the data bus 14 . Further, a flag register 25 is connected to the ALU 18. Flag register 25
holds the result of the comparison operation of the ALU 18. A determination circuit 26 is connected to the flag register 25, and the determination circuit 2
6 compares the flag held in the flag register 25 with the data output from the sequence controller 20. The judgment output of the judgment circuit 26 is supplied to the memory control circuit 27. The memory control circuit 27 specifies the read address of the program memory 24, and normally generates a read address signal according to a predetermined order, but depending on the judgment output of the judgment circuit 26, the read address signal from the sequence controller 20 The supplied address signal is output as a read address signal.

An output interface 23 is connected to the data bus 14, and the digital audio signal output from the output interface 23 is supplied to the D/A converter 5 as an output signal of the DSP 3. be done. interface 1
3, 23, multiplier 15, coefficient RAM 17, ALU 18,
The operation timings of the accumulator 19 and memory control circuits 22 and 27 are controlled by a sequence controller 20. Sequence controller 20 operates according to a processing program written in program memory 24 and also operates according to instructions from microcomputer 4. Further, a keyboard 8 is connected to the microcomputer 4 in order to generate various commands by operation. The microcomputer 4 controls writing of coefficient data in the RAM 17 in response to key operations on the keyboard 8.

In this configuration, the analog audio signal supplied to the A/D converter 2 is converted into digital audio signal data at every predetermined sampling period T0, and is sent via the interface 13. Data memory 12
is supplied to and stored. Sequence controller 20
are the timing of reading data from the interface 13, the timing of selectively transferring data from the data memory 12 to the multiplier 15, the timing of outputting each coefficient data from the RAM 17, and the multiplication operation of the multiplier 15. Timing, ALU18 addition operation timing, accumulator 1
The timing is determined such as the output timing of 9 and the timing of outputting the data of the calculation result from the interface 23. By taking these timings appropriately,
The desired action is performed. For example, input audio signal data is transferred to the data memory 1 via the data bus 14.
2 and stored. The signal data stored in the data memory 12 is sequentially read out and transferred to the memory control circuit 22.
and is written to the storage location of the ring buffer memory 9 specified by the write address W. Further, data is read from the storage location in the ring buffer memory 9 specified by the read address RMn. The read data is supplied to the data memory 12 and stored therein. The coefficients are stored in the RAM 17, read out, and supplied to the buffer memory 16 where they are held. The data stored in the data memory 12 is read out and supplied to the buffer memory 28. Multiplier 15 includes buffer memories 16 and 28
are multiplied by the respective held coefficients and data values and output. Further, the data stored in the data memory 12, the variables, and the data values of the multiplication results of the multiplier 15 are supplied to the ALU 18, where addition and comparison operations are performed, and the addition results are sent to the accumulator 19. The comparison result is held in the flag register 25. Flag register 2
The read address of the program memory 24 is jumped in accordance with the flag held in the flag 5, and the steps of the processing program of the sequence controller 20 are changed.

The specific operation of the DSP 3 is shown in the routine shown in FIG. That is, first, a value Jn indicating how many times the sampling period T0 is the period at which continuous sampling data is skipped or read twice, and a value UD are initialized according to the pitch increase or decrease (step S1). . This is set according to input from the keyboard 8. For example, UD=1 is set to raise the pitch, and UD=-1 is set to lower the pitch. After executing step S1, the input data is written to the storage location of the ring buffer memory 9 specified by the write address W (
Step S2), the output data Do is made equal to 0, and the variable M is made equal to 0 (Step S3). The write address W changes by +1 address each time the variable n is added in step S17 (described later) (every sample). Variable M is a variable for setting read address RMn. After executing step S3, it is determined whether variable M is smaller than the number of reading points N (step S4). The number of read points N indicates the number of times data is read from the ring buffer memory 9 within the sampling period T0. If M<N, 1 is added to the variable M (step S5), and it is determined whether the remainder of the value obtained by dividing the variable n by the multiple Jn is 0 (step S6). If the remainder of n/Jn is not 0, it is determined whether the variable n is equal to 0 (step S7).

If the remainder of n/Jn is 0, the value UD is added to the previous read address RMn-1 to obtain the current read address RMn, and the previous value of the address interval value between the write address W and the read address RMn is The value UD is added to dRMn-1 to obtain the current address interval value dRMn (step S8). Here, FIG. 4 shows the relationship among the write address W, read address RMn, and address interval value dRMn in the ring buffer memory 9. It is determined whether the current address interval value dRMn is greater than 0 (step S9). dRMn>0
If so, it is determined whether the current address interval value dRMn is smaller than the total number of addresses Bs corresponding to the size of the ring buffer memory 9 (step S10). dRM
If n<Bs, the fade function f(
dRMn) is calculated, and the calculated value is set as the coefficient aM related to the read data (step S11), and the data (*RMn) is calculated from the storage location specified by the read address RMn.
is read out, the data (*RMn) is multiplied by a coefficient aM, and output data Do is added to obtain new output data Do (step S12). Any function can be used as the fade function as long as it satisfies f(0)=0 and f(Bs)=0. For example, f(d
RMn) is a linear function, or f(Bs/2)=1, f
This is a function that satisfies (Bs/4)=(1/2)2. In step S8, if the address of the ring buffer memory 9 is from address 1 to address Bs, if the previous read address RMn-1 is address Bs, the current read address RMn is address 1. Further, the data stored in the storage location specified by the read address RMn is indicated by (*RMn).

If it is determined in step S9 that dRMn≦0, the read address RMn has become the write address W or an earlier address due to the lowering of the pitch, so the total number of addresses Bs is added to the write address W. The address resulting from the addition is set as the read address RMn, and the total number of addresses Bs is set as the address interval value dRMn (step S13).
). After executing step S13, the process moves to step S11. Note that if UD=-1, dRMn<0 will not actually hold, but dRMn=0.

[0014] In step S10, dRMn≧Bs
If it is determined that the read address RMn has become the write address W or a later address by increasing the pitch, the address equal to the write address W is set as the read address RMn, and 0 is set as the address interval. The value is set as the value dRMn (step S14). After executing step S14, the process moves to step S11. Note that if UD=1, dRMn>Bs does not actually hold, but dRMn=Bs.

If it is determined in step S7 that n=0, it is the first sampling input data, so the process proceeds to step S11. If it is determined that n≠0, it is other than the first sampling input data. Therefore, step S12
Proceed to. If M≧N in step S4, the output data Do is obtained by reading data from the storage location specified by the read address by the number of read points N, so the output data Do is actually output ( Step S15)
. Then, it is determined whether or not the pitch control process has ended (
Step S16), if the process is not completed, 1 is added to the variable n (step S17), and the process proceeds to step S2. If the pitch control process is finished, this routine is finished.

Therefore, if the multiple Jn for skipping or reading twice is 3 and the number of reading points N is 2, then
The read addresses R1n and R2n are changed every time the input data is sampled three times. That is, when increasing the pitch, read addresses R1n and R2n are advanced by UD from the previous values R1n-1 and R2n-1, and when decreasing the pitch, read addresses R1n and R2n are advanced respectively by UD.
are each delayed by UD from the previous values R1n-1 and R2n-1. The fade function f(dR1n) determined by the address interval value dR1n between the read address R1n and the write address W is set as the coefficient a1, and the data read from the storage location specified by the read address R1n (
*R1n) is multiplied by the coefficient a1 and the output data Do
By adding (=0), the output data Do (=a
1 (*R1n)) is calculated. Also, the address interval value dR between the read address R2n and the write address W
The fade function f(dR2n) determined by 2n is the coefficient a2
The data (*R2n) read from the storage location specified by the read address R2n is multiplied by the coefficient a2 and output by adding the output data Do (=a1 (*R1n)). Data Do (=a1 (*R
1n)+a2 (*R2n)) is calculated. This calculated output data Do is supplied to the D/A converter 5 via the interface 23.

Since the read addresses R1n and R2n are advanced when increasing the pitch, the read address R1n
, R2n overtakes the write address W and the address interval values dR1n, dR2n exceed the total number of addresses Bs, the read address R1n, R2n
is made equal to the write address W. Also, because the read addresses R1n and R2n are delayed when lowering the pitch, the read addresses R1n and R2n fall below the write address W, and the address interval value dR1n,
When dR2n becomes 0 or less, read addresses R1n and R2n become write address W + total number of addresses B
is made equal to s.

Since there is no change in the address interval values dR1n and dR2n for input data during two consecutive samplings between samplings in which the above operation is performed, the coefficients a1 and a2 are maintained, and the read address R1n
, R2n, the output data Do is calculated as described above according to the data (*R1n) and (*R2n) read from the storage location specified by R2n.

Multiple read addresses (eg, R1n
, R2n) is the address interval value D between multiple read addresses, and when increasing the pitch, Td = D・(1-1/Jn)・T0

...(1) When lowering the pitch, Td = D・(1+1/Jn)・T0

...(2) It can be expressed as follows. This formula (1)
From (2), if D and Jn are constant, the time Td will be shorter when raising the pitch than when lowering it, so the above reverberation phenomenon will occur when raising the pitch than when lowering it. I know it's difficult. Maximum value Dm of address interval value D between multiple read addresses
ax is the allowable time for the data time difference Td
max, when increasing the pitch, from equation (1) Dmax = Tdmax/{(1-1/Jn)・T0
}
...(3), and when lowering the pitch, use formula (2)
From Dmax = Tdmax/{(1+1/Jn)・
T0 }
...(4) It can be done as follows. Allowable time Tdm
The ax should be set at 45 to 80 m to prevent reverberation from becoming noticeable.
sec.

For example, if a plurality of read addresses are equally spaced, the total number of addresses B in the ring buffer memory 9 is
Since s is N・Dmax, when raising the pitch, Bs = N・Tdmax/{(1-1/Jn)・
T0 }
...(5) When lowering the pitch, Bs = N・Tdmax/{(1+1/Jn)・T0
}...
(6) becomes. Therefore, in order to suppress the reverberation phenomenon and the tremolo sound, it is necessary to change the total number of addresses Bs of the ring buffer memory 9 in accordance with the rise and fall of the pitch. Total number of addresses B of ring buffer memory 9
When s is fixed, it is necessary to set the total number of addresses Bs in accordance with the sound that is most likely to cause reverberation. For example, if the pitch is to be shifted up to two and a half tones in semitone units (five steps up and down), and the total number of addresses Bs in the ring buffer memory 9 is fixed, the smaller the amount of pitch shift when raising the pitch, the lower the pitch will be. Sometimes, the larger the pitch shift amount, the longer the time lag Td of data between read addresses, and when the pitch is lowered, the time lag Td is longer than when the pitch is raised. Therefore, the total number of addresses Bs in the ring buffer memory 9 may be fixed to such an extent that the reverberation phenomenon is not noticeable when the pitch is lowered by two and a half notes. If the total number of addresses Bs is to be changed as the pitch increases or decreases, set it so that the reverberation phenomenon is not noticeable when raising the pitch by a half step, and when lowering the pitch by two and a half steps. Just set it to a level where it doesn't bother you.

[0021] In the above embodiment, the DSP
Although pitch control is possible using this, it is not limited to this. For example, there are multiple latch circuits that hold data read from the ring buffer memory, an arithmetic circuit that sets coefficients for each read address according to the address interval between the write address, and a latch circuit that stores the set coefficients. It is also possible to control the pitch by providing a plurality of multipliers that multiply the output data of the plurality of multipliers and an adder that adds the output data values of the plurality of multipliers.

[0022]

As described above, according to the present invention, the permissible time difference of data between a plurality of read addresses is
dmax, the maximum address interval Dmax of multiple read addresses is Dmax when the pitch rises.
=Tdmax/{(1-1/Jn)・T0},
When the pitch falls, Dmax = Tdmax/{(1+1/Jn)・T0
}, and the allowable time Tdmax is set to 45 to 80 msec, at which the reverberation phenomenon is not noticeable, so that it is possible to increase the size of the ring buffer memory and suppress the generation of tremolo sound while also suppressing the reverberation phenomenon.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a DSP in the device of FIG. 1;

FIG. 3 is a flow diagram showing the operation of the DSP.

FIG. 4 is a diagram showing a positional correspondence between a write address and each read address of a ring buffer memory.

FIG. 5 is a diagram showing changes in frequency characteristics over time of the pitch control device according to the present invention.

FIG. 6 is a diagram showing the positional correspondence between a write address and each read address of a ring buffer memory in a conventional pitch control device.

FIG. 7 is a diagram showing changes in frequency characteristics over time during a crossfade period of a conventional pitch control device.

[Explanation of symbols of main parts]

2 A/D converter 3 DSP 4. Microcomputer 5 D/A converter 9 Ring buffer memory

Claims (2)

[Claims] 1. Write address designating means for designating one write address in a memory in a predetermined order every sampling period T0 of input audio signal data, and a plurality of read addresses in the memory for each sampling period T0. are individually designated in accordance with the predetermined order, and when the pitch rises at every predetermined multiple Jn (an integer of 2 or more) of the sampling period T0, the plurality of read addresses are read by at least 1 during the sampling period T0.
0, and when the pitch falls, the plurality of read addresses are changed by at least 1 to the sampling period T.
0 read addressing means for setting the previous address;
means for writing the input audio signal data to a storage location of the designated write address in the memory;
means for reading data from storage locations of the plurality of designated read addresses in the memory; means for setting a coefficient for each of the plurality of read addresses according to an address interval between the plurality of read addresses and the write address; A pitch control device comprising calculation means for multiplying read data and a corresponding coefficient for each read address and adding the data values of the multiplication results to each other to obtain output data. , if the allowable time for the data time lag between the plurality of read addresses is Tdmax, then the maximum value Dmax of the address interval of the plurality of read addresses is set as Dmax = Tdmax/{(1-1/ J
n )・T0 }, and when the pitch falls, Dmax = Tdmax/{(1+1/Jn )・T0
}, and the allowable time Tdmax is 45 to 80 mse.
A pitch control device characterized in that the pitch control device is set to c. 2. The pitch control device according to claim 1, wherein the memory is a ring buffer memory, and the write address and the read address are specified by returning to the first address after the final address. .